So the function factor_out_conditional_conversion already supports
diamond shaped bb forms, just need to be called for such a thing.
harden-cond-comp.c needed to be changed as we would optimize out the
conversion now and that causes the compare hardening not needing to
split the block which it
So the function factor_out_conditional_conversion already supports
diamond shaped bb forms, just need to be called for such a thing.
harden-cond-comp.c needed to be changed as we would optimize out the
conversion now and that causes the compare hardening not needing to
split the block which it
After adding diamond shaped bb support to factor_out_conditional_conversion,
we can get a case where we have two conversions that needs factored out
and then would have another phiopt happen.
An example is:
```
static inline unsigned long long g(int t)
{
unsigned t1 = t;
return t1;
}
unsigned
After using factor_out_conditional_conversion with diamond bb,
we should be able do use it also for all normal unary gimple and not
just conversions. This allows to optimize PR 59424 for an example.
This is also a start to optimize PR 64700 and a few others.
OK? Bootstrapped and tested on
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the Croatian team of translators. The file is available at:
https://translationproject.org/latest/gcc/hr.po
(This file, 'gcc-13.1.0.hr.po', has
It looks like we cannot simply swap the code and mode in rtx_def, the code may
have to be the same bits as the tree_code in tree_base. Or we will meet ICE
like below.
rtx_def code 16 => 8 bits.
rtx_def mode 8 => 16 bits.
static inline decl_or_value
dv_from_value (rtx value)
{
decl_or_value
OK, you can go ahead commit patch.
I am gonna send another patch to fix this.
Besides, I saw you have commit some redundant incorrect codes, I will clean
them up in another patch.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-05-07 04:11
To: juzhe.zh...@rivai.ai; Robin Dapp; gcc-patches;
在 2023/5/7 上午1:05, Xi Ruoyao 写道:
On Wed, 2023-04-26 at 21:29 +0800, Xi Ruoyao via Gcc-patches wrote:
Do you have any questions about the test cases mentioned by
Guo
Jie? If there is no problem, modify the test case,
I think the code can be merged into the main branch.
I'll rewrite
在 2023/5/7 上午1:07, Xi Ruoyao 写道:
On Wed, 2023-04-26 at 18:21 +0800, WANG Xuerui wrote:
On 2023/4/26 18:14, Lulu Cheng wrote:
在 2023/4/26 下午6:02, WANG Xuerui 写道:
On 2023/4/26 17:53, Lulu Cheng wrote:
Hi, ruoyao:
The performance of spec2006 is finished. The fixed-point
400.perlbench
On Thu, Apr 27, 2023 at 5:47 PM Fangrui Song wrote:
>
> When using -mcmodel=medium, large data is placed into .l* sections. GNU ld
> places .l* sections into separate output sections. If small and medium
> code model object files are mixed, the .l* sections won't cause
> relocation overflow
On 5/3/23 11:31, Michael Collison wrote:
HI Kito,
I see there have been many comments on the
"riscv_vector_preferred_simd_mode" hook, is there an updated version?
I think there's a version on the trunk now. So if there's updates to
do, let's do them relative to what's on the trunk.
Jeff
On 5/3/23 23:07, juzhe.zh...@rivai.ai wrote:
This ideal of this patch looks good to me.
But I think this patch should be able to handle more cases (not only -16
~ 15) in case of CONST_VECTOR initialization.
Case 1 (Other constant value that is not -16 ~ 15):
void vmv_m##VAL (TYPE dst[],
It turns out a couple of bits submitted by Michael had already been
pushed to the trunk. These two patches removes the duplicated bits.
Jeffcommit b9b7981f3d6919518372daf4c7e8c40dfc58f49d
Author: Jeff Law
Date: Sat May 6 11:36:37 2023 -0600
Remove duplicated definition in risc-v
On Fri, 5 May 2023 10:55:41 +0200
Thomas Schwinge wrote:
> So I recently had re-created this patch independently, before remembering
> that Rainer had -- just eight years ago... ;-) -- already submitted this.
thanks to you both :)
> etc. (where "normal" is a libstdc++ detail), and regarding:
>
On 5/6/23 06:57, Roger Sayle wrote:
Following up on posts/reviews by Segher and Uros, there's some question
over why the middle-end's lower subreg pass emits a clobber (of a
multi-word register) into the instruction stream before emitting the
sequence of moves of the word-sized parts. This
On 5/5/23 09:46, Michael Collison wrote:
While working on autovectorizing for the RISCV port I encountered an issue
where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a
evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode),
where GET_MODE_NUNITS is
On 5/5/23 09:46, Michael Collison wrote:
2023-04-24 Michael Collison
Juzhe Zhong
* config/riscv/riscv.cc
(riscv_estimated_poly_value): Implement
TARGET_ESTIMATED_POLY_VALUE.
(riscv_preferred_simd_mode): Implement
Hi Jerry, Steve,
I think I have to pour a little water into the wine.
The patch fixes the reported issue only for a comma after
the namelist name, but we still accept a few other illegal
characters, e.g. ';', because:
#define is_separator(c) (c == '/' || c == ',' || c == '\n' || c == ' ' \
On 5/5/23 09:46, Michael Collison wrote:
2023-04-24 Michael Collison
Juzhe Zhong
* config/riscv/riscv-v.cc
(riscv_vector_preferred_simd_mode): New function.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
On Sat, May 6, 2023 at 10:26 AM Roger Sayle wrote:
>
>
> This patch proposes adding run-time library support for bit reversal,
> by adding a __bitrevsi2 function to libgcc. Thoughts/opinions?
Are you going to add a builtin for these functions too? If so that is
recorded as
This patch proposes adding run-time library support for bit reversal,
by adding a __bitrevsi2 function to libgcc. Thoughts/opinions?
I'm also tempted to add __popcount[qh]i2 and __parity[qh]i2 to libgcc,
to allow the RTL optimizers to perform narrowing operations, but I'm
curious to hear
On 5/5/23 09:46, Michael Collison wrote:
2023-03-02 Michael Collison
Juzhe Zhong
* config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):
Remove static declaration to to make externally visible.
(get_mask_policy_for_pred): Ditto.
*
On Wed, 2023-04-26 at 18:21 +0800, WANG Xuerui wrote:
> On 2023/4/26 18:14, Lulu Cheng wrote:
> >
> > 在 2023/4/26 下午6:02, WANG Xuerui 写道:
> > >
> > > On 2023/4/26 17:53, Lulu Cheng wrote:
> > > > Hi, ruoyao:
> > > >
> > > > The performance of spec2006 is finished. The fixed-point
> > > >
On Wed, 2023-04-26 at 21:29 +0800, Xi Ruoyao via Gcc-patches wrote:
> >
> > Do you have any questions about the test cases mentioned by
> > Guo
> > Jie? If there is no problem, modify the test case,
> >
> > I think the code can be merged into the main branch.
>
> I'll rewrite the test
On Sat, 2023-04-29 at 12:05 -0600, Jeff Law wrote:
>
>
> On 4/15/23 06:01, Xi Ruoyao via Gcc-patches wrote:
> > This prevents a spurious message building a cross-compiler when
> > target
> > libc is not installed yet:
> >
> > cc1: error: no include path in which to search for stdc-
> >
On 5/5/23 09:45, Michael Collison wrote:
2023-04-24 Michael Collison
Juzhe Zhong
* config/riscv/riscv-protos.h
(riscv_vector_preferred_simd_mode): New.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
An analysis of backend UNSPECs reveals that two of the most common UNSPECs
across target backends are for copysign and bit reversal. This patch
adds RTX codes for these expressions to allow their representation to
be standardized, and them to optimized by the middle-end RTL optimizers.
This
This patch adds support for (a pair of) bit reversal intrinsics
__builtin_nvptx_brev and __builtin_nvptx_brevll which perform 32-bit
and 64-bit bit reversal (using nvptx's brev instruction) matching
the __brev and __brevll instrinsics provided by NVidia's nvcc compiler.
On 5/5/23 21:43, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode): New function.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto.
(preferred_simd_mode): Ditto.
* config/riscv/riscv.cc
On 5/4/23 11:14, Raphael Moreira Zinsly wrote:
We were not able to match the CTZ sign extend pattern on RISC-V
because it get optimized to zero extend and/or to ANDI patterns.
For the ANDI case, combine scrambles the RTL and generates the
extension by using subregs.
So to provide a few more
Hi Uros,
This is a repost/respin of a patch that was conditionally approved:
https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609470.html
This patch adds a convenient post-reload splitter for setting/updating
the highpart of a TImode variable, using i386's previously added
(and it'd be useful to have it backported to the 13 branch)
Samuel Thibault, le sam. 06 mai 2023 13:50:36 +0200, a ecrit:
> We need the multilib paths in gcc to find e.g. glibc crt files on
> Debian. This is essentially based on t-linux64 version.
>
> gcc/ChangeLog:
>
> *
LGTM, thanks :)
於 2023年5月6日 週六，11:44寫道：
> From: Juzhe-Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (preferred_simd_mode): New function.
> * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto.
> (preferred_simd_mode): Ditto.
> *
Following up on posts/reviews by Segher and Uros, there's some question
over why the middle-end's lower subreg pass emits a clobber (of a
multi-word register) into the instruction stream before emitting the
sequence of moves of the word-sized parts. This clobber interferes
with (LRA) register
> > > diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
> > > index 9b767038452..c81b08e3cc5 100644
> > > --- a/gcc/config/riscv/iterators.md
> > > +++ b/gcc/config/riscv/iterators.md
> > > @@ -288,3 +288,8 @@ (define_int_iterator QUIET_COMPARISON
> > > [UNSPEC_FLT_QUIET
This fixes the Hurd spec in the default-pie case, and adds static-pie
support.
gcc/ChangeLog:
* gcc/config/i386/gnu.h: Use PIE_SPEC, add static-pie case.
* gcc/config/i386/gnu64.h: Use PIE_SPEC, add static-pie case.
diff --git a/gcc/config/i386/gnu.h b/gcc/config/i386/gnu.h
We need the multilib paths in gcc to find e.g. glibc crt files on
Debian. This is essentially based on t-linux64 version.
gcc/ChangeLog:
* gcc/config/i386/t-gnu64: New file.
* gcc/config.gcc [x86_64-*-gnu*): Add i386/t-gnu64 to
tmake_file.
diff --git a/gcc/config.gcc
From: Juzhe-Zhong
This patch is fixing: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109743.
This issue happens is because we are currently very conservative in
optimization of user vsetvli.
Consider this following case:
bb 1:
vsetvli a5,a4... (demand AVL = a4).
bb 2:
RVV insn use a5
On 2023-05-05 23:57 Sinan wrote:
>
>> hi Jiawei
>>
>> Please ignore my previous reply. I accidently sent the email before I
>> finished it.
>> Sorry for that!
>>
>> I downloaded the series of patches from you and found in some cases
>> it fails to generate zcmp push and pop insns.
>>
>> TC:
>>
Zcmp can share the same logic as save-restore in stack allocation:
pre-allocation
by cm.push, step 1 and step 2.
please be noted cm.push pushes ra, s0-s11 in reverse order than what
save-restore does.
So adaption has been done in .cfi directives in my patch.
gcc/ChangeLog:
*
zcmp aims to reduce code size, while shrink-wrap-separate prefers
speed to code size. So disable shrink-wrap-separate if zcmp
enabled, just like what save-restore has done.
author: Zhangjin Liao liaozhang...@eswincomputing.com
gcc/ChangeLog:
* config/riscv/riscv.cc
Before implementing Zcmp, I did some optimizations and restructures to
save-restore.
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a5b2a3bff8152aa34408d8ce40add82f4d22ff87
https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=60524be1e3929d83e15fceac6e2aa053c8a6fb20
On 4/19/23 03:57, Jin Ma wrote:
> This patch adds the 'Zfa' extension for riscv, which is based on:
>https://github.com/riscv/riscv-isa-manual/commits/zfb
>
https://github.com/riscv/riscv-isa-manual/commit/1f038182810727f5feca311072e630d6baac51da
>
> The binutils-gdb for 'Zfa'
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