[PATCH] Remove # from one_cmpl2 assemble output.

optimize_insn_for_speed () in assemble output is not aligned with splitter condition, and it cause an ICE when building SPEC2017 blender_r. Not sure if ctrl is supposed to be reliable in assemble output, the patch just remove that as a walkaround. Bootstrapped and regtested on

Re: [gcc r14-2455] riscv: Prepare backend for index registers

On Jul 17 2023, Christoph Müllner wrote: > My host compiler is: gcc version 13.1.1 20230614 (Red Hat 13.1.1-4) (GCC) Too old. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different."

RE: [PATCH] Fix bootstrap failure (with g++ 4.8.5) in tree-if-conv.cc.

> On Mon, Jul 17, 2023 at 12:21 AM Tamar Christina via Gcc-patches patc...@gcc.gnu.org> wrote: > > > > > -Original Message- > > > From: Richard Biener > > > Sent: Monday, July 17, 2023 7:19 AM > > > To: Roger Sayle > > > Cc: gcc-patches@gcc.gnu.org; Tamar Christina > > > > > > Subject:

Re: [gcc r14-2455] riscv: Prepare backend for index registers

On Mon, Jul 17, 2023 at 9:24 AM Andreas Schwab wrote: > > On Jul 17 2023, Christoph Müllner wrote: > > > The build process shows a lot of warnings. > > Then you are using a bad compiler. The build is 100% -Werror clean. My host compiler is: gcc version 13.1.1 20230614 (Red Hat 13.1.1-4) (GCC)

Re: [gcc r14-2455] riscv: Prepare backend for index registers

On Sun, Jul 16, 2023 at 11:49 PM Christoph Müllner wrote: > > On Fri, Jul 14, 2023 at 12:28 PM Andreas Schwab wrote: > > > > Why didn't you test that? > > Thanks for reporting, and sorry for introducing this warning. > > I test all patches before sending them. > In the case of RISC-V backend

Re: [PATCH] Fix bootstrap failure (with g++ 4.8.5) in tree-if-conv.cc.

On Mon, Jul 17, 2023 at 12:21 AM Tamar Christina via Gcc-patches wrote: > > > -Original Message- > > From: Richard Biener > > Sent: Monday, July 17, 2023 7:19 AM > > To: Roger Sayle > > Cc: gcc-patches@gcc.gnu.org; Tamar Christina > > Subject: Re: [PATCH] Fix bootstrap failure (with

Re: [gcc r14-2455] riscv: Prepare backend for index registers

On Jul 17 2023, Christoph Müllner wrote: > The build process shows a lot of warnings. Then you are using a bad compiler. The build is 100% -Werror clean. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something

RE: [PATCH] Fix bootstrap failure (with g++ 4.8.5) in tree-if-conv.cc.

> -Original Message- > From: Richard Biener > Sent: Monday, July 17, 2023 7:19 AM > To: Roger Sayle > Cc: gcc-patches@gcc.gnu.org; Tamar Christina > Subject: Re: [PATCH] Fix bootstrap failure (with g++ 4.8.5) in > tree-if-conv.cc. > > On Fri, Jul 14, 2023 at 8:56 PM Roger Sayle >

[COMMITTED] Normalize irange_bitmask before union/intersect.

The bit twiddling in union/intersect for the value/mask pair must be normalized to have the unknown bits with a value of 0 in order to make the math simpler. Normalizing at construction slowed VRP by 1.5% so I opted to normalize before updating the bitmask in range-ops, since it was the only

[COMMITTED] Add global setter for value/mask pair for SSA names.

This patch provides a way to set the value/mask pair of known bits globally, similarly to how we can use set_nonzero_bits for known 0 bits. This can then be used by CCP and IPA to set value/mask info instead of throwing away the known 1 bits. In further clean-ups, I will see if it makes sense to

Re: [PATCH] core: Support heap-based trampolines

> On 17 Jul 2023, at 07:58, Iain Sandoe wrote > >> On 17 Jul 2023, at 07:43, FX Coudert wrote: >> >> >> There is an alternate mechanism relying on system libraries that is possible >> on darwin specifically (I don’t know for other targets) but it will only >> work for signed binaries,

Re: [PATCH] RISC-V: Support non-SLP unordered reduction

> @@ -247,6 +248,7 @@ void emit_vlmax_cmp_mu_insn (unsigned, rtx *); > void emit_vlmax_masked_mu_insn (unsigned, int, rtx *); > void emit_scalar_move_insn (unsigned, rtx *); > void emit_nonvlmax_integer_move_insn (unsigned, rtx *, rtx); > +//void emit_vlmax_reduction_insn (unsigned, rtx *);

Re: [PATCH] core: Support heap-based trampolines

> On 17 Jul 2023, at 07:43, FX Coudert wrote: > > Hi, > >> Since this affects the ABI of libgcc I think we don't want that part >> to be user configurable but rather determined by >> some static list of targets that opt-in to this config. > > If I do that, do the Linux maintainers want

Re: [gcc r14-2455] riscv: Prepare backend for index registers

On Fri, Jul 14, 2023 at 12:28 PM Andreas Schwab wrote: > > Why didn't you test that? Thanks for reporting, and sorry for introducing this warning. I test all patches before sending them. In the case of RISC-V backend patches, I build a 2-stage cross-toolchain and run all regression tests for

Re: [PATCH] Add peephole to eliminate redundant comparison after cmpccxadd.

Ping. On Tue, Jul 11, 2023 at 5:16 PM liuhongt via Gcc-patches wrote: > > Similar like we did for CMPXCHG, but extended to all > ix86_comparison_int_operator since CMPCCXADD set EFLAGS exactly same > as CMP. > > When operand order in CMP insn is same as that in CMPCCXADD, > CMP insn can be

Re: [PATCH] core: Support heap-based trampolines

Hi, > Since this affects the ABI of libgcc I think we don't want that part > to be user configurable but rather determined by > some static list of targets that opt-in to this config. If I do that, do the Linux maintainers want Linux in or out? > You mention setjmp/longjmp - on darwin and

Re: [PATCH] x86: slightly enhance "vec_dupv2df"

On Mon, Jul 17, 2023 at 2:20 PM Jan Beulich wrote: > > On 17.07.2023 08:09, Hongtao Liu wrote: > > On Fri, Jul 14, 2023 at 5:40 PM Jan Beulich via Gcc-patches > > wrote: > >> > >> Introduce a new alternative permitting all 32 registers to be used as > >> source without AVX512VL, by broadcasting

Re: [PATCH] [gcc-wwwdocs]gcc-13/14: Mention Intel new ISA and march support

On Mon, Jul 17, 2023 at 5:34 AM Haochen Jiang via Gcc-patches wrote: > > Hi all, > > This patch adds documentation to wwwdocs to mention the recent introduction > of Intel new ISA and march. > > Ok for trunk? OK. > BRs, > Haochen > > --- > htdocs/gcc-13/changes.html | 4 >

Re: [PATCH] PR 95923: More (boolean) bitop simplifications in match.pd

On Mon, Jul 17, 2023 at 4:43 AM Andrew Pinski via Gcc-patches wrote: > > This adds the boolean version of some of the simplifications > that were added with r8-4395-ge268a77b59cb78. > > That are the following: > (a | b) & (a == b) --> a & b > a | (a == b) --> a | (b ^ 1) > (a & b) | (a ==

Re: [PATCH] vect: Initialize new_temp to avoid false positive warning [PR110652]

On Mon, Jul 17, 2023 at 4:22 AM Kewen.Lin wrote: > > Hi, > > As PR110652 and its duplicate PRs show, there could be one > build error > > error: 'new_temp' may be used uninitialized > > for some build configurations. It's a false positive warning > (or error at -Werror), but in order to make

Re: [WIP RFC] Add support for keyword-based attributes

On Fri, Jul 14, 2023 at 5:58 PM Richard Sandiford via Gcc-patches wrote: > > Summary: We'd like to be able to specify some attributes using > keywords, rather than the traditional __attribute__ or [[...]] > syntax. Would that be OK? > > In more detail: > > We'd like to add some new

Re: [PATCH] core: Support heap-based trampolines

On Sun, Jul 16, 2023 at 12:39 PM FX Coudert via Gcc-patches wrote: > > Hi, > > This is a reworked version (following review) of the patch by Maxim Blinov > and Iain Sandoe enabling heap-based trampolines. What has changed since the > last version: > > - wording changes, preferring to use

[PATCH V2] RISC-V: Add TARGET_MIN_VLEN > 4096 check

gcc/ChangeLog: * config/riscv/riscv.cc (riscv_option_override): Add TARGET_MIN_VLEN < 4096 check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvl-unimplemented.c: New test. --- gcc/config/riscv/riscv.cc | 8

Re: [PATCH V4] Optimize '(X - N * M) / N' to 'X / N - M' if valid

Hi Andrew, Aldy and Richard, Thanks a lot for all your very helpful comments! Andrew MacLeod writes: > On 7/14/23 09:37, Richard Biener wrote: >> On Fri, 14 Jul 2023, Aldy Hernandez wrote: >> >>> I don't know what you're trying to accomplish here, as I haven't been >>> following the PR, but

Re: [PATCH] Fix PR 110666: `(a != 2) == a` produces wrong code

On Fri, Jul 14, 2023 at 10:56 PM Andrew Pinski via Gcc-patches wrote: > > I had messed up the case where the outer operator is `==`. > The check for the resulting should have been `==` and not `!=`. > This patch fixes that and adds a full runtime testcase now for > all cases to make sure it

Re: [PATCH] x86: slightly enhance "vec_dupv2df"

On 17.07.2023 08:09, Hongtao Liu wrote: > On Fri, Jul 14, 2023 at 5:40 PM Jan Beulich via Gcc-patches > wrote: >> >> Introduce a new alternative permitting all 32 registers to be used as >> source without AVX512VL, by broadcasting to the full 512 bits in that >> case. (The insn would also permit

Re: [PATCH] Fix bootstrap failure (with g++ 4.8.5) in tree-if-conv.cc.

On Fri, Jul 14, 2023 at 8:56 PM Roger Sayle wrote: > > > > This patch fixes the bootstrap failure I'm seeing using gcc 4.8.5 as > > the host compiler. Ok for mainline? [I might be missing something] OK. Btw, while I didn't spot this during review I would appreciate if the code could use

Re: [PATCH] RISC-V: Add TARGET_MIN_VLEN > 4096 check

On Mon, Jul 17, 2023 at 2:05 PM Juzhe-Zhong wrote: > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_option_override): Report ERROR for > TARGET_MIN_VLEN > 4096 > > --- > gcc/config/riscv/riscv.cc | 8 > 1 file changed, 8 insertions(+) > > diff --git

Re: [PATCH] x86: avoid maybe_gen_...()

On Fri, Jul 14, 2023 at 5:42 PM Jan Beulich via Gcc-patches wrote: > > In the (however unlikely) event that no insn can be found for the > requested mode, using maybe_gen_...() without (really) checking its > result for being a null rtx would lead to silent bad code generation. Ok. > > gcc/ > >

[PATCH] RISC-V: Add TARGET_MIN_VLEN > 4096 check

gcc/ChangeLog: * config/riscv/riscv.cc (riscv_option_override): Report ERROR for TARGET_MIN_VLEN > 4096 --- gcc/config/riscv/riscv.cc | 8 1 file changed, 8 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6ed735d6983..ce523eea9ba 100644

Re: [PATCH] x86: slightly enhance "vec_dupv2df"

On Fri, Jul 14, 2023 at 5:40 PM Jan Beulich via Gcc-patches wrote: > > Introduce a new alternative permitting all 32 registers to be used as > source without AVX512VL, by broadcasting to the full 512 bits in that > case. (The insn would also permit all registers to be used as > destination, but

<    1   2