From: Pan Li
This patch would like to support the auto-vectorization from
the INT64 to FP16. We take below steps for the conversion.
* INT64 to FP32.
* FP32 to FP16.
Given sample code as below:
void
test_func (int64_t * __restrict a, _Float16 *b, unsigned n)
{
for (unsigned i = 0; i < n;
That sounds about right. The code I had in mind would perhaps look like:
#if defined(__AVX512BW__) && defined(__AVX512VL__)
#if defined(__EVEX256__) && !defined(__EVEX512__)
// compiled code is AVX10.1/256 and AVX512 compatible
#else
// compiled code is only AVX512
Hi,
Thanks for you reply.
I'd like to verify that our understanding of your requirements is correct, and
that __EVEX256__ can be considered a default macro to determine whether the
compiler supports the __EVEX***__ series of switches.
For example:
I have a segment of code like:
#if
Committed, thanks juzhe.
--
Li Xu
>LGTM. Thanks for fixing it.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-09-28 09:33
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
>From: xuli
>
>Consider the flowing
Hi,
"Kewen.Lin" writes:
> Hi Jeff,
>
> on 2023/8/30 15:43, Jiufu Guo wrote:
>> Hi,
>>
>> As mentioned in PR108338, on p9, we could use mtvsrws to implement
>> the bitcast from SI to SF (or lowpart DI to SF).
>>
>> For code:
>> *(long long*)buff = di;
>> float f = *(float*)(buff);
>>
>>
LGTM. Thanks for fixing it.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-28 09:33
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
From: xuli
Consider the flowing situation:
BB5: local_dem(RVV Insn 1, AVL(reg zero))
RVV
Hi,
"Kewen.Lin" writes:
> Hi Jeff,
>
> on 2023/8/30 15:43, Jiufu Guo wrote:
>> Hi,
>>
>> Currently, we have the pattern "movsf_from_si2" which was trying
>> to support moving high part DI to SF.
>>
>> The pattern looks like: XX:SF=bitcast:SF(subreg(YY:DI>>32),0)
>> It only accepts the
From: xuli
Consider the flowing situation:
BB5: local_dem(RVV Insn 1, AVL(reg zero))
RVV Insn 1: vmv.s.x, AVL (const_int 1)
RVV Insn 2: vredsum.vs, AVL(reg zero)
vmv.s.x has vl operand, the following code will get
avl (cosnt_int) from RVV Insn 1.
rtx avl = has_vl_op (insn->rtl ()) ? get_vl
Almost forget about this patch, sorry for disturbing and kindly ping again.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Li, Pan2 via Gcc-patches
Sent: Monday, September 11, 2023 4:37 PM
To: Jeff Law ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
Thanks for the new patch!
I see that there's a new __EVEX512__ define. Will there be some
__EVEX256__ (or maybe some max EVEX width) define, so that code can
detect whether the compiler supports AVX10.1/256 without resorting to
version checks?
Not to worry, I'm currently going through that process with the FSF, it
was confirmed that a pseudonym should be just fine. I don't know how
long the process takes but my goal is to get this in for GCC14, and
surely this won't take more than a month. One can only hope anyway.
On 2023-09-27 04:43
On 9/27/23 13:14, Jeff Law wrote:
It would help to describe how these patterns were under specified so
that folks don't continue to make the same mistake as new tests get
added.
dg-final scan-assembler, scan-assembler-not, and scan-assembler-times
use a tcl regular expression (often
> Date: Tue, 26 Sep 2023 01:56:55 +
> From: waffl3x
> Signed-off-by: waffl3x
I think I've read that you have to put your actual name in
the DCO; using an alias (presumably) as above would be
wrong.
Ah, it's on https://gcc.gnu.org/dco.html - the *second* DCO
link; under "Signed-off-by", on
On 9/20/23 07:09, Lehua Ding wrote:
This patch adds combine cond_len_op and vec_cond to cond_len_op like
cond_op.
gcc/ChangeLog:
* gimple-match.h (gimple_match_op::gimple_match_op):
Add interfaces for more arguments.
(gimple_match_op::set_op): Add interfaces for more
On 9/20/23 07:09, Lehua Ding wrote:
This patch makes cond autovec testcase checks more restrict.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c:
Assert of the number of vmerge.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto.
On Wed, Sep 27, 2023 at 1:14 PM Jeff Law wrote:
>
>
>
> On 9/27/23 12:22, Joern Rennecke wrote:
> > On Wed, 27 Sept 2023 at 18:22, Jeff Law wrote:
> >
> >> It would help to describe how these patterns were under specified so
> >> that folks don't continue to make the same mistake as new tests
On 9/26/23 17:08, 钟居哲 wrote:
Hi, Jeff.
I removed mem-to-mem patterns as you suggested that means we don't have
scalar move optimization for small size vector modes.
Is it ok for trunk?
Since it is a bug fix patch, I hope we can land it soon. We may will
find another way to optimize small
On 9/27/23 11:32, Palmer Dabbelt wrote:
IMO this is one of those places where we should just be as normal as
possible. So if the other big ports allow system headers then we
should, otherwise we should move everyone over to testing in some way
we'll catch these before commit.
Exactly.
On 9/27/23 11:48, Joern Rennecke wrote:
Regression tested for:
riscv-sim
riscv-sim/-march=rv32gcv_zfh/-mabi=ilp32d/-ftree-vectorize/--param=riscv-autovec-preference=scalable
riscv-sim/-march=rv32imac/-mabi=ilp32
On 9/26/23 12:56, Joern Rennecke wrote:
What ultimately pushed us to keep moving forward on this effort was
discovering numerous CRC loop implementations out in the wild, including
4 implementations (IIRC) in the kernel itself.
I have always assumed that such must exist (CRCs are useful
On 9/27/23 00:29, Vineet Gupta wrote:
Hi Jeff,
We touched upon this in our airport "rendezvous". I'm curious if you
have the wip bits lying around - (a) to get a feel for how this could be
done and (b) to see why REE and/or similar construct in CSE don't work
as expected.
Not in any
On 9/27/23 12:22, Joern Rennecke wrote:
On Wed, 27 Sept 2023 at 18:22, Jeff Law wrote:
It would help to describe how these patterns were under specified so
that folks don't continue to make the same mistake as new tests get added.
dg-final scan-assembler, scan-assembler-not, and
On Wed, 27 Sept 2023, 18:25 Tom Tromey via Libstdc++,
wrote:
> >> I have fixes for most of the issues that are worth fixing (I didn't
> >> bother with line lengths -- FWIW in gdb we just run 'black' and don't
> >> worry about these details),
>
> Jonathan> I used autopep8 and committed the result
Hi Ramana,
> Hope this helps.
Yes definitely!
>> Passes regress/bootstrap, OK for commit?
>
> Target ? armhf ? --with-arch , -with-fpu , -with-float parameters ?
> Please be specific.
I used --target=arm-none-linux-gnueabihf --host=arm-none-linux-gnueabihf
--build=arm-none-linux-gnueabihf
On Wed, 27 Sept 2023 at 18:22, Jeff Law wrote:
> It would help to describe how these patterns were under specified so
> that folks don't continue to make the same mistake as new tests get added.
dg-final scan-assembler, scan-assembler-not, and scan-assembler-times
use a tcl regular expression
On 9/27/23 19:31, Jeff Law wrote:
On 9/27/23 04:14, juzhe.zh...@rivai.ai wrote:
Since after removing mem-to-mem pattern.
program main
integer, dimension(:,:), allocatable :: a, b
integer, dimension(:), allocatable :: sh
allocate (a(2,2))
allocate (b(2,2))
allocate (sh(3))
a
On Wed, Sep 13, 2023 at 11:19 AM Fangrui Song wrote:
>
> On Tue, Aug 22, 2023 at 12:19 AM Fangrui Song wrote:
> >
> > On Tue, Aug 1, 2023 at 12:51 PM Fangrui Song wrote:
> > >
> > > When using -mcmodel=medium, large data objects larger than the
> > > -mlarge-data-threshold threshold are placed
On Wed, 27 Sep 2023 10:28:55 PDT (-0700), jeffreya...@gmail.com wrote:
On 9/25/23 15:17, Maciej W. Rozycki wrote:
On Mon, 25 Sep 2023, Maciej W. Rozycki wrote:
NB the use of this specific header, still in place elsewhere,
seems gratuitous to me. We don't need or indeed want to print
On 9/27/23 04:14, juzhe.zh...@rivai.ai wrote:
Since after removing mem-to-mem pattern.
program main
integer, dimension(:,:), allocatable :: a, b
integer, dimension(:), allocatable :: sh
allocate (a(2,2))
allocate (b(2,2))
allocate (sh(3))
a = 1
b = cshift(a,sh)
end
On 9/27/23 03:38, juzhe.zh...@rivai.ai wrote:
>> Why add `can_create_pseudo_p ()` here? this will split after reload,
but we forbid that pattern between reload and split2?
I have no ideal. Some fortran tests just need recognization of
mem-to-mem pattern before RA
I don't know the
On 9/25/23 15:17, Maciej W. Rozycki wrote:
On Mon, 25 Sep 2023, Maciej W. Rozycki wrote:
NB the use of this specific header, still in place elsewhere,
seems gratuitous to me. We don't need or indeed want to print anything in
the test cases (unless verifying something specific to the
>> I have fixes for most of the issues that are worth fixing (I didn't
>> bother with line lengths -- FWIW in gdb we just run 'black' and don't
>> worry about these details),
Jonathan> I used autopep8 and committed the result as
Jonathan> e08559271b2d797f658579ac8610dbf5e58bcfd8 so the line
On 9/27/23 03:26, Joern Rennecke wrote:
I got tired of scan tests failing when they have an underspecified
pattern that matches LTO information, so I did a global replace for
the most common form of such scan patterns in the gcc.target/riscv
testsuite.
regression tested for:
riscv-sim
On Wed, 27 Sept 2023 at 16:37, Tom Tromey wrote:
>
> > Jonathan Wakely via Gcc-patches writes:
>
> Replying to a quite old email...
>
> I ran a Python linter on the libstdc++ pretty-printers.
>
> I have fixes for most of the issues that are worth fixing (I didn't
> bother with line lengths
> Jonathan Wakely via Gcc-patches writes:
Replying to a quite old email...
I ran a Python linter on the libstdc++ pretty-printers.
I have fixes for most of the issues that are worth fixing (I didn't
bother with line lengths -- FWIW in gdb we just run 'black' and don't
worry about these
Hi Bernhard,
Thanks, I meant to fix this, but forgot.
The underlying problem here is that we want to detect which sub-testsuites had
failures. Current regex doesn't match go's case because there is no "..." at
the end: "Running foo" vs "Running foo ..." .
My preferred way of fixing this is
From: Sergei Trofimovich
r14-3459-g0c78240fd7d519 "Check that passes do not forget to define profile"
exposed check failures in cases when gcc produces uninitialized profile
probabilities. In case of PR/111559 uninitialized profile is generated
by edges executed 0 times during profile:
Hi,
This is a v4 patch to address Jason's feedback here:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630911.html
w.r.t. v3 it just removes a comment now that some uncertainty around
cxx_binary_literals has been resolved, and updates the documentation as
suggested to point to the
On Sat, 23 Sept 2023 at 08:30, Nathaniel Shead via Libstdc++
wrote:
>
> On Sat, Sep 23, 2023 at 07:40:48AM +0100, Jonathan Wakely wrote:
> > On Sat, 23 Sept 2023, 01:39 Nathaniel Shead via Libstdc++, <
> > libstd...@gcc.gnu.org> wrote:
> >
> > > Now that bootstrap has finished, I have gotten
On Tue, Sep 19, 2023 at 7:05 PM Ken Matsui
wrote:
> On Tue, Sep 19, 2023 at 9:59 AM Jason Merrill wrote:
> >
> > On 9/15/23 19:51, Ken Matsui via Gcc-patches wrote:
> > > Now that RID_MAX has reached 255, we need to update the bit sizes of
> every
> > > use of the enum rid from 8 to 16 to
This is the fix for the release branches, where std::to_array is
implemented differently.
Tested x86_64-linux. Pushed to gcc-13 and gcc-12. Will push to gcc-11
after testing.
-- >8 --
Qualify the calls to the __to_array helper to prevent ADL, so we don't
try to complete associated classes.
tested on x86_64-darwin21 (native) and with crosses from x86_64-linux-gnu
to powerpc-darwin, i686-darwin, x86_64-darwin and with
--enable-languages=all to powerpc-apple-darwin9 (this built the front ends
OK - but there seems to be an unrelated config error in that even with
all-host, some language
Applied to master (with fixups). Thanks!
Philipp.
On Wed, 27 Sept 2023 at 10:40, Kyrylo Tkachov wrote:
>
> Hi Manos,
>
> > -Original Message-
> > From: Manos Anagnostakis
> > Sent: Tuesday, September 26, 2023 2:52 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Kyrylo Tkachov ; Tamar
Hello,
Le 27/09/2023 à 12:46, Jakub Jelinek a écrit :
--- gcc/vec.h.jj2023-09-27 10:38:50.635845540 +0200
+++ gcc/vec.h 2023-09-27 12:11:56.665586490 +0200
@@ -1028,13 +1050,17 @@ template
inline void
vec::truncate (unsigned size)
{
- gcc_checking_assert (length () >= size);
+
Spec:
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett
Nandni Jamnadas
Pietra Ferreira
Charlie Keaney
Jessica Mills
Craig Blackmore
Simon Cook
Jeremy Bennett
Helene Chelin
gcc/ChangeLog:
*
Spec:
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett
Nandni Jamnadas
Pietra Ferreira
Charlie Keaney
Jessica Mills
Craig Blackmore
Simon Cook
Jeremy Bennett
Helene Chelin
gcc/ChangeLog:
*
This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are
On Tue, 26 Sep 2023, Jason Merrill wrote:
> On 9/25/23 16:43, Patrick Palka wrote:
> > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK
> > for trunk?
> >
> > -- >8 --
> >
> > This tree code dates all the way back to r69130[1] which implemented
> > typing of non-dependent
On Wed, 27 Sep 2023, Tamar Christina wrote:
> Hi All,
>
> When we have a vector conditional on a masked target which is doing a
> selection
> on the result of a conditional operation where one of the operands of the
> conditional operation is the other operand of the select, then we can fold
On Wed, 20 Sep 2023, Robin Dapp wrote:
> Hi,
>
> as described in PR111401 we currently emit a COND and a PLUS expression
> for conditional reductions. This makes it difficult to combine both
> into a masked reduction statement later.
> This patch improves that by directly emitting a COND_ADD
> > gcc/ChangeLog:
> >
> > * auto-profile.cc (afdo_calculate_branch_prob): Fix count
> > comparisons
> > * ipa-utils.cc (ipa_merge_profiles): Guard against zero count when
> > computing probabilities
> > * tree-vect-loop-manip.cc (vect_do_peeling): Guard against
On Tue, Sep 19, 2023 at 8:17 PM Eugene Rozenfeld
wrote:
>
> These .PHONY targets are always executed and were breaking `make install`
> for autoprofiledbootstrap build.
OK.
> gcc/ChangeLog:
>
> * c/Make-lang.in: Make create_fdas_for_cc1 target not .PHONY
> * cp/Make-lang.in:
On Tue, Sep 19, 2023 at 8:17 PM Eugene Rozenfeld
wrote:
>
> Verifier checks have recently been strengthened to check that
> all counts and probabilities are initialized. The checks fired
> during autoprofiledbootstrap build and this patch fixes it.
OK if Honza doesn't have any comments this
On Thu, Sep 14, 2023 at 5:12 AM Kewen Lin wrote:
>
> For VMAT_CONTIGUOUS_REVERSE, the transform code in function
> vectorizable_store generates a VEC_PERM_EXPR stmt before
> storing, but it's never considered in costing.
>
> This patch is to make it consider vec_perm in costing, it
> adjusts the
On Thu, Sep 14, 2023 at 5:12 AM Kewen Lin wrote:
>
> This patch is to eventually get rid of vect_model_store_cost,
> it adjusts the costing for the remaining memory access types
> VMAT_CONTIGUOUS{, _DOWN, _REVERSE} by moving costing close
> to the transform code. Note that in
On Thu, Sep 14, 2023 at 5:12 AM Kewen Lin wrote:
>
> This patch adjusts the cost handling on VMAT_CONTIGUOUS_PERMUTE
> in function vectorizable_store. We don't call function
> vect_model_store_cost for it any more. It's the case of
> interleaving stores, so it skips all stmts excepting for
>
On Thu, Sep 14, 2023 at 5:12 AM Kewen Lin wrote:
>
> This patch adjusts the cost handling on VMAT_LOAD_STORE_LANES
> in function vectorizable_store. We don't call function
> vect_model_store_cost for it any more. It's the case of
> interleaving stores, so it skips all stmts excepting for
>
On Thu, Sep 14, 2023 at 5:12 AM Kewen Lin wrote:
>
> This patch adjusts the cost handling on VMAT_ELEMENTWISE
> and VMAT_STRIDED_SLP in function vectorizable_store. We
> don't call function vect_model_store_cost for them any more.
>
> Like what we improved for PR82255 on load side, this change
>
On Thu, Sep 14, 2023 at 5:12 AM Kewen Lin wrote:
>
> This patch is to simplify the costing on the case
> vectorizable_scan_store without calling function
> vect_model_store_cost any more.
>
> I considered if moving the costing into function
> vectorizable_scan_store is a good idea, for doing
>
On Thu, Sep 14, 2023 at 5:12 AM Kewen Lin wrote:
>
> This patch adjusts the cost handling on VMAT_GATHER_SCATTER
> in function vectorizable_store (all three cases), then we
> won't depend on vect_model_load_store for its costing any
> more. This patch shouldn't have any functional changes.
OK.
On Thu, Sep 14, 2023 at 5:12 AM Kewen Lin wrote:
>
> This patch is an initial patch to move costing next to the
> transform, it still adopts vect_model_store_cost for costing
> but moves and duplicates it down according to the handlings
> of different vect_memory_access_types or some special
>
On Thu, Sep 14, 2023 at 5:12 AM Kewen Lin wrote:
>
> When making/testing patches to move costing next to the
> transform code for vectorizable_store, some ICEs got
> exposed when I further refined the costing handlings on
> VMAT_ELEMENTWISE. The apparent cause is triggering the
> assertion in
On Wed, 27 Sep 2023, Jakub Jelinek wrote:
> On Wed, Sep 27, 2023 at 07:17:22AM +, Richard Biener wrote:
> > OK I guess. Can you summarize the limitations for non-POD types
> > in the big comment at the start of vec.h?
>
> Still haven't done that, but will do after we flesh out the details
>
"Kewen.Lin" writes:
> Hi,
>
> on 2023/9/20 16:49, HAO CHEN GUI wrote:
>> Hi,
>> This patch enables vector compare for 16-byte memory equality compare.
>> The 16-byte memory equality compare can be efficiently implemented by
>> instruction "vcmpequb." It reduces one branch and one compare
Andrea Corallo writes:
> Hi all,
>
> this is to allow for spaces before "cons:" in the definitions of
> patterns using the new compact syntax, ex:
>
> (define_insn "aarch64_simd_dup"
> [(set (match_operand:VDQ_I 0 "register_operand")
> (vec_duplicate:VDQ_I
> (match_operand: 1
Andrea Corallo writes:
> From: Richard Sandiford
>
> Hi all,
>
> this is to add support to the new compact pattern syntax for the case
> where the constraints do appear unsorted like:
>
> (define_insn "*si3_insn_uxtw"
> [(set (match_operand:DI 0 "register_operand")
> (zero_extend:DI
The following adds simplification of abs (copysign (x, y)) to abs (x).
Bootstrap & regtest in progress on x86_64-unknown-linux-gnu.
Richard.
* match.pd (abs (copysign (x, y)) -> abs (x)): New pattern.
* gcc.dg/fold-abs-6.c: New testcase.
---
gcc/match.pd |
On Wed, Sep 27, 2023 at 07:17:22AM +, Richard Biener wrote:
> OK I guess. Can you summarize the limitations for non-POD types
> in the big comment at the start of vec.h?
Still haven't done that, but will do after we flesh out the details
below.
> (can we put in static_asserts
> in the
Tamar Christina writes:
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Wednesday, September 27, 2023 9:50 AM
>> To: Tamar Christina
>> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
>> ; Marcus Shawcroft
>> ; Kyrylo Tkachov
>> Subject: Re: [PATCH]AArch64: Use SVE
Tamar Christina writes:
> Hi All,
>
> This rewrites the simd MOV patterns to use the new compact syntax.
> No change in semantics is expected. This will be needed in follow on patches.
>
> This also merges the splits into the define_insn which will also be needed
> soon.
>
> Bootstrapped
Tamar Christina writes:
> Hi All,
>
> This adds a way to generate special sequences for creation of constants for
> which we don't have single instructions sequences which would have normally
> lead to a GP -> FP transfer or a literal load.
>
> The patch starts out by adding support for creating
Since after removing mem-to-mem pattern.
program main
integer, dimension(:,:), allocatable :: a, b
integer, dimension(:), allocatable :: sh
allocate (a(2,2))
allocate (b(2,2))
allocate (sh(3))
a = 1
b = cshift(a,sh)
end program main
This case will failed if we don't change mov
I can understand why remove mem to mem pattern, but why the normal mov
pattern for VLS_AVL_IMM need to change too?
On Wed, Sep 27, 2023 at 10:39 AM juzhe.zh...@rivai.ai
wrote:
>
> >> Why add `can_create_pseudo_p ()` here? this will split after reload,
> >> but we forbid that pattern between
On Wed, 27 Sep 2023, Tamar Christina wrote:
> > -Original Message-
> > From: Tamar Christina
> > Sent: Wednesday, September 27, 2023 8:57 AM
> > To: Richard Biener
> > Cc: Andrew Pinski ; gcc-patches@gcc.gnu.org; nd
> > ; j...@ventanamicro.com
> > Subject: RE: [PATCH]middle-end
>> Why add `can_create_pseudo_p ()` here? this will split after reload,
>> but we forbid that pattern between reload and split2?
I have no ideal. Some fortran tests just need recognization of mem-to-mem
pattern before RA.
I don't know the reason.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date:
> -Original Message-
> From: Tamar Christina
> Sent: Wednesday, September 27, 2023 8:57 AM
> To: Richard Biener
> Cc: Andrew Pinski ; gcc-patches@gcc.gnu.org; nd
> ; j...@ventanamicro.com
> Subject: RE: [PATCH]middle-end match.pd: optimize fneg (fabs (x)) to x | (1 <<
> signbit(x))
> (define_insn_and_split "*mov"
>[(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
>"TARGET_VECTOR
> - && (register_operand (operands[0], mode)
> + && (can_create_pseudo_p ()
Why add
I got tired of scan tests failing when they have an underspecified
pattern that matches LTO information, so I did a global replace for
the most common form of such scan patterns in the gcc.target/riscv
testsuite.
regression tested for:
riscv-sim
This patch implements the following TODO in gcc/config/aarch64/aarch64.cc
to provide the requested behaviour for handling ldp and stp:
/* Allow the tuning structure to disable LDP instruction formation
from combining instructions (e.g., in peephole2).
TODO: Implement fine-grained
On Wed, 27 Sep 2023, Andre Vieira (lists) wrote:
>
>
> On 26/09/2023 17:37, Andrew Stubbs wrote:
> > I don't have authority to approve anything, but here's a review anyway.
> >
> > Thanks for working on this.
>
> Thank you for reviewing and apologies for the mess of a patch, may have rushed
>
Thanks Kyrill!
Submitting the obvious v5.
Manos.
On Wed, Sep 27, 2023 at 11:40 AM Kyrylo Tkachov
wrote:
> Hi Manos,
>
> > -Original Message-
> > From: Manos Anagnostakis
> > Sent: Tuesday, September 26, 2023 2:52 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Kyrylo Tkachov ; Tamar
On 27/09/2023 08:56, Andre Vieira (lists) wrote:
On 26/09/2023 17:37, Andrew Stubbs wrote:
I don't have authority to approve anything, but here's a review anyway.
Thanks for working on this.
Thank you for reviewing and apologies for the mess of a patch, may have
rushed it ;)
diff --git
Hi Jeff,
on 2023/8/30 15:43, Jiufu Guo wrote:
> Hi,
>
> As mentioned in PR108338, on p9, we could use mtvsrws to implement
> the bitcast from SI to SF (or lowpart DI to SF).
>
> For code:
> *(long long*)buff = di;
> float f = *(float*)(buff);
>
> "sldi 9,3,32 ; mtvsrd 1,9 ; xscvspdpn 1,1"
> -Original Message-
> From: Richard Sandiford
> Sent: Wednesday, September 27, 2023 9:50 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; Kyrylo Tkachov
> Subject: Re: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions
> when
Hi Jeff,
on 2023/8/30 15:43, Jiufu Guo wrote:
> Hi,
>
> Currently, we have the pattern "movsf_from_si2" which was trying
> to support moving high part DI to SF.
>
> The pattern looks like: XX:SF=bitcast:SF(subreg(YY:DI>>32),0)
> It only accepts the "ashiftrt" for ">>", but "lshiftrt" is also
Tamar Christina writes:
> Hi All,
>
> SVE has much bigger immediate encoding range for bitmasks than Advanced SIMD
> has
> and so on a system that is SVE capable if we need an Advanced SIMD
> Inclusive-OR
> by immediate and would require a reload then an unpredicated SVE ORR instead.
>
> This
Hi Manos,
> -Original Message-
> From: Manos Anagnostakis
> Sent: Tuesday, September 26, 2023 2:52 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Tamar Christina
> ; Philipp Tomsich ;
> Manos Anagnostakis
> Subject: [PATCH v4] aarch64: Fine-grained policies to control ldp-stp
>
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, September 27, 2023 4:24 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Support FP roundeven auto-vectorization
LGTM
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-27 16:20
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP roundeven auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
roundeven API in
Juzhe-Zhong writes:
> hen doing fortran test with 'V' extension enabled on RISC-V port.
> I saw multiple ICE: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111590
>
> The root cause is on DSE:
>
> internal compiler error: in smallest_mode_for_size, at stor-layout.cc:356
> 0x1918f70
From: Pan Li
This patch would like to support auto-vectorization for the
roundeven API in math.h. It depends on the -ffast-math option.
When we would like to call roundeven like v2 = roundeven (v1), we will
convert it into below insns (reference the implementation of llvm).
* vfcvt.x.f v3, v1,
> -Original Message-
> From: Richard Biener
> Sent: Wednesday, September 27, 2023 8:12 AM
> To: Tamar Christina
> Cc: Andrew Pinski ; gcc-patches@gcc.gnu.org; nd
> ; j...@ventanamicro.com
> Subject: RE: [PATCH]middle-end match.pd: optimize fneg (fabs (x)) to x | (1 <<
> signbit(x))
On 26/09/2023 17:37, Andrew Stubbs wrote:
I don't have authority to approve anything, but here's a review anyway.
Thanks for working on this.
Thank you for reviewing and apologies for the mess of a patch, may have
rushed it ;)
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-19.c
On Wed, Sep 27, 2023 at 7:39 AM Kewen.Lin wrote:
>
> Hi,
>
> The uninitialized variable a in pr60510.f can cause some
> random failures as exposed in PR111427, see the details
> there. This patch is to make it initialized accordingly.
>
> As verified, it can fix the reported -m32 failures on
>
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, September 27, 2023 3:18 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com; jeffreya...@gmail.com
Subject: Re: [PATCH] ifcvt: Fix comments
On Wed, 27 Sep 2023, Juzhe-Zhong
On Wed, 27 Sep 2023, Juzhe-Zhong wrote:
> Fix comments since original comment is confusing.
OK
> gcc/ChangeLog:
>
> * tree-if-conv.cc (is_cond_scalar_reduction): Fix comments.
>
> ---
> gcc/tree-if-conv.cc | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git
On Wed, 27 Sep 2023, Jakub Jelinek wrote:
> Hi!
>
> We have some very limited support for non-POD types in vec.h
> (in particular grow_cleared will invoke default ctors on the
> cleared elements and vector copying invokes copy ctors.
>
> My pending work on wide_int/widest_int which makes those
On Wed, 27 Sep 2023, Tamar Christina wrote:
> > -Original Message-
> > From: Andrew Pinski
> > Sent: Wednesday, September 27, 2023 2:17 AM
> > To: Tamar Christina
> > Cc: gcc-patches@gcc.gnu.org; nd ; rguent...@suse.de;
> > j...@ventanamicro.com
> > Subject: Re: [PATCH]middle-end
Fix comments since original comment is confusing.
gcc/ChangeLog:
* tree-if-conv.cc (is_cond_scalar_reduction): Fix comments.
---
gcc/tree-if-conv.cc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc
index
Tamar Christina writes:
> Hi All,
>
> Following the Neoverse N/V and Cortex-A optimization guides SIMD 0 immediates
> should be created with a movi of 0.
>
> At the moment we generate an `fmov .., xzr` which is slower and requires a
> GP -> FP transfer.
>
> Bootstrapped Regtested on
1 - 100 of 101 matches
Mail list logo
