Re: [PATCH] RISC-V: Fix ICE in non-canonical march parsing

On Thu, Nov 16, 2023 at 2:32 AM Patrick O'Neill wrote: > > Does relax mean no longer enforcing the canonical order of extensions? Yes, we've discussed that a long time ago, but we just didn't have enough people to moving that forward:

Re: [PATCH] RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]

ohhh, thanks for fixing that, LGTM! On Thu, Nov 16, 2023 at 7:31 AM Edwin Lu wrote: > > Fix __riscv_unaligned_fast/slow/avoid macro name to > __riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec > > gcc/ChangeLog: > > * config/riscv/riscv-c.cc

[PATCH v2] LoongArch: Add code generation support for call36 function calls.

When compiling with '-mcmodel=medium', the function call is made through 'pcaddu18i+jirl' if binutils supports call36, otherwise the native implementation 'pcalau12i+jirl' is used. gcc/ChangeLog: * config.in: Regenerate. * config/loongarch/loongarch-opts.h

Re: [PATCH] i386: Fix mov imm,%rax; mov %rdi,%rdx; mulx %rax -> mov imm,%rdx; mulx %rdi peephole2 [PR112526]

On Thu, Nov 16, 2023 at 8:16 AM Jakub Jelinek wrote: > > Hi! > > The following testcase is miscompiled on x86_64 since PR110551 r14-4968 > commit. That commit added 2 peephole2s, one for > mov imm,%rXX; mov %rYY,%rax; mulq %rXX -> mov imm,%rax; mulq %rYY > which I believe is ok, and another one

Re: [PATCH] LoongArch: Increase cost of vector aligned store/load.

On 11/16/23 14:17, Jiahao Xu wrote: Based on SPEC2017 performance evaluation results, making them equal to the cost of unaligned store/load to avoid odd alignment peeling is better. Paraphrasing a bit to shorten the subject of the sentence: "it's better to make them equal to ... so as to

Re: [PATCH] VECT: Add MASK_LEN_STRIDED_LOAD/MASK_LEN_STRIDED_STORE into loop vectorizer

Just finished X86 bootstrap && regtest no regression And tested on aarch64 no regression. juzhe.zh...@rivai.ai From: Juzhe-Zhong Date: 2023-11-14 11:46 To: gcc-patches CC: richard.sandiford; rguenther; Juzhe-Zhong Subject: [PATCH] VECT: Add MASK_LEN_STRIDED_LOAD/MASK_LEN_STRIDED_STORE into

Re: [PATCH] DOC/IFN/OPTAB: Add mask_len_strided_load/mask_len_strided_store DOC/OPTAB/IFN

Update just finished test CI. Tested on aarch64 QEMU no regression. juzhe.zh...@rivai.ai From: Juzhe-Zhong Date: 2023-11-14 11:39 To: gcc-patches CC: richard.sandiford; rguenther; Juzhe-Zhong Subject: [PATCH] DOC/IFN/OPTAB: Add mask_len_strided_load/mask_len_strided_store DOC/OPTAB/IFN This

[PATCH] i386: Fix mov imm,%rax; mov %rdi,%rdx; mulx %rax -> mov imm,%rdx; mulx %rdi peephole2 [PR112526]

Hi! The following testcase is miscompiled on x86_64 since PR110551 r14-4968 commit. That commit added 2 peephole2s, one for mov imm,%rXX; mov %rYY,%rax; mulq %rXX -> mov imm,%rax; mulq %rYY which I believe is ok, and another one for mov imm,%rXX; mov %rYY,%rdx; mulx %rXX, %rZZ, %rWW -> mov

Re: [PATCH] tree-optimization: Add register pressure heuristics

On Thu, Nov 16, 2023 at 7:12 AM Ajit Agarwal wrote: > > Hello Richard: > > With the below decison making I get the performance at par with trunk > changes and better than trunk for FP and INT SPEC 2017 benchmarks. > > int best_bb_liveout_cnt > = bitmap_count_bits (>liveout[best_bb->index]); >

Re: [PATCH] slp: Fix handling of IFN_CLZ/CTZ [PR112536]

On Thu, 16 Nov 2023, Jakub Jelinek wrote: > Hi! > > We ICE on the following testcase now that IFN_C[LT]Z calls can have one or > two arguments (where 2 mean it is well defined at zero). > The following patch makes us create child node only for the first argument > and compatible_calls_p ensures

Re: [PATCH] tree-optimization/112282 - wrong-code with ifcvt hoisting

On Thu, 16 Nov 2023, Dimitar Dimitrov wrote: > On Wed, Nov 15, 2023 at 12:11:50PM +, Richard Biener wrote: > > The following avoids hoisting of invariants from conditionally > > executed parts of an if-converted loop. That now makes a difference > > since we perform bitfield lowering even

Re: [committed] i386: Return CCmode from ix86_cc_mode for unknown RTX code [PR112494]

On Tue, Nov 14, 2023 at 6:51 PM Jakub Jelinek wrote: > > On Mon, Nov 13, 2023 at 10:49:23PM +0100, Uros Bizjak wrote: > > Combine wants to combine following instructions into an insn that can > > perform both an (arithmetic) operation and set the condition code. During > > the conversion a new

[PATCH] slp: Fix handling of IFN_CLZ/CTZ [PR112536]

Hi! We ICE on the following testcase now that IFN_C[LT]Z calls can have one or two arguments (where 2 mean it is well defined at zero). The following patch makes us create child node only for the first argument and compatible_calls_p ensures the other argument is the same, which at least

Re: [PATCH]middle-end: skip checking loop exits if loop malformed [PR111878]

On Wed, 15 Nov 2023, Tamar Christina wrote: > Hi All, > > Before my refactoring if the loop->latch was incorrect then find_loop_location > skipped checking the edges and would eventually return a dummy location. > > It turns out that a loop can have > loops_state_satisfies_p

Re: [PATCH] VECT: Clear LOOP_VINFO_USING_SELECT_VL_P when loop is not partial vectorized

On Thu, 16 Nov 2023, Juzhe-Zhong wrote: > This patch fixes ICE: > https://godbolt.org/z/z8T6o6qov > > : In function 'b': > :2:6: error: missing definition > 2 | void b() { > | ^ > for SSA_NAME: loop_len_8 in statement: > _1 = -loop_len_8; > during GIMPLE pass: vect > :2:6:

Re: [PATCH] tree-optimization/112282 - wrong-code with ifcvt hoisting

On Wed, Nov 15, 2023 at 12:11:50PM +, Richard Biener wrote: > The following avoids hoisting of invariants from conditionally > executed parts of an if-converted loop. That now makes a difference > since we perform bitfield lowering even when we do not actually > if-convert the loop.

[PATCH] LoongArch: Increase cost of vector aligned store/load.

Based on SPEC2017 performance evaluation results, making them equal to the cost of unaligned store/load to avoid odd alignment peeling is better. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_builtin_vectorization_cost): Adjust. diff --git

[PATCH] aarch64: Add support for Ampere-1B (-mcpu=ampere1b) CPU

This patch adds initial support for Ampere-1B core. The Ampere-1B core implements ARMv8.7 with the following (compiler visible) extensions: - CSSC (Common Short Sequence Compression instructions), - MTE (Memory Tagging Extension) - SM3/SM4 gcc/ChangeLog: *

[PATCH] aarch64: costs: update for TARGET_CSSC

With the addition of CSSC (Common Short Sequence Compression) instructions, a number of idioms match to single instructions (e.g., abs) that previously expanded to multi-instruction sequences. This recognizes (some of) those idioms that are now misclassified and returns a cost of a single

Re: [PATCH] tree-optimization: Add register pressure heuristics

Hello Richard: With the below decison making I get the performance at par with trunk changes and better than trunk for FP and INT SPEC 2017 benchmarks. int best_bb_liveout_cnt = bitmap_count_bits (>liveout[best_bb->index]); int early_bb_liveout_cnt = bitmap_count_bits

[PATCH] Fix ICE of unrecognizable insn.

The new added splitter will generate (insn 58 56 59 2 (set (reg:V4HI 20 xmm0 [129]) (vec_duplicate:V4HI (reg:HI 22 xmm2 [123]))) "testcase.c":16:21 -1 But we only have (define_insn "*vec_dupv4hi" [(set (match_operand:V4HI 0 "register_operand" "=y,Yw") (vec_duplicate:V4HI

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

> On Nov 16, 2023, at 14:33, Fangrui Song wrote: > > On Wed, Nov 15, 2023 at 9:23 PM Jeff Law wrote: >> >> >> >> On 11/15/23 18:51, Tatsuyuki Ishi wrote: On Nov 16, 2023, at 10:07, Jeff Law wrote: >> >>> >>> Based on what I have read in the AArch64 backend, there are two ways to >>>

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

On 11/15/23 22:33, Fangrui Song wrote: I have used this to check rtld and linker behavior. I think we need some `scan-assembler`. To make it a runnable test, some assembler feature check may be needed. Perhaps Jeff can make some suggestion or contribute code! TLS isn't really on my radar

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

On Wed, Nov 15, 2023 at 9:23 PM Jeff Law wrote: > > > > On 11/15/23 18:51, Tatsuyuki Ishi wrote: > >> On Nov 16, 2023, at 10:07, Jeff Law wrote: > > > > > Based on what I have read in the AArch64 backend, there are two ways to > > do this: introduce a custom calling convention, or put in a RTX

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

On 11/15/23 18:51, Tatsuyuki Ishi wrote: On Nov 16, 2023, at 10:07, Jeff Law wrote: Based on what I have read in the AArch64 backend, there are two ways to do this: introduce a custom calling convention, or put in a RTX insn that covers the whole sequence. Ideally we should do the

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

On 11/15/23 18:39, Tatsuyuki Ishi wrote: As mentioned in the commit message, the use of relaxation-only labels does not seem well supported in current GCC. Creating a label seems to force a basic block and I’m not sure how we can avoid it. If there’s a better way to implement this I’m

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

On 11/15/23 18:17, Fangrui Song wrote: It seems that x86-64 supports non-adjacent code sequence. Writing the pattern this way does not allow interleaving, but I assume interleaving doesn't enable much. It's of marginal benefit. We could always split them before scheduling if it turned out

Re: [PATCH] Reduce false positives for -Wnonnull for VLA parameters [PR98541]

> From: Martin Uecker > Date: Tue, 07 Nov 2023 06:56:25 +0100 > Am Montag, dem 06.11.2023 um 21:01 -0700 schrieb Jeff Law: > > > > On 11/6/23 20:58, Hans-Peter Nilsson wrote: > > > This patch caused a testsuite regression: there's now an > > > "excess error" failure for gcc.dg/Wnonnull-4.c for

[PATCH] VECT: Clear LOOP_VINFO_USING_SELECT_VL_P when loop is not partial vectorized

This patch fixes ICE: https://godbolt.org/z/z8T6o6qov : In function 'b': :2:6: error: missing definition 2 | void b() { | ^ for SSA_NAME: loop_len_8 in statement: _1 = -loop_len_8; during GIMPLE pass: vect :2:6: internal compiler error: verify_ssa failed 0x7f1b56331082

Re: [PATCH] [i386] APX: Fix EGPR usage in several patterns.

On Wed, Nov 15, 2023 at 5:43 PM Hongyu Wang wrote: > > Hi, > > For vextract/insert{if}128 they cannot adopt EGPR in their memory operand, all > related pattern should be adjusted to disable EGPR usage on them. > Also fix a wrong gpr16 attr for insertps. > > Bootstrapped/regtested on

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

> On Nov 16, 2023, at 10:07, Jeff Law wrote: > > > > On 9/8/23 04:49, Tatsuyuki Ishi via Gcc-patches wrote: >> This implements TLS Descriptors (TLSDESC) as specified in [1]. >> In TLSDESC instruction sequence, the first instruction relocates against >> the target TLS variable, while subsequent

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

> On Nov 16, 2023, at 10:17, Fangrui Song wrote: > > On Mon, Oct 2, 2023 at 7:10 AM Kito Cheng > wrote: >> >> Just one nit and one more comment for doc: >> >> Could you add some doc something like that? mostly I grab from other >> target, so you can just included

Re: [PATCH v2] LoongArch: Remove redundant barrier instructions before LL-SC loops

在 2023/11/15 下午7:38, Xi Ruoyao 写道: Pushed r14-5486. /* snip */ * gcc.target/loongarch/cas-acquire.c: New test. This test fails with GCC 12/13 on LA664, and it indicates a correctness issue. May I backport this patch to 12/13 as well? I think we can backport. Thanks!

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

On Mon, Oct 2, 2023 at 7:10 AM Kito Cheng wrote: > > Just one nit and one more comment for doc: > > Could you add some doc something like that? mostly I grab from other > target, so you can just included in the patch. > > diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi > index

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

On 9/8/23 04:49, Tatsuyuki Ishi via Gcc-patches wrote: This implements TLS Descriptors (TLSDESC) as specified in [1]. In TLSDESC instruction sequence, the first instruction relocates against the target TLS variable, while subsequent instructions relocates against the address of the first.

[PING] [PATCH] gfortran: Rely on dg-do-what-default to avoid running pr85853.f90, pr107254.f90 and vect-alias-check-1.F90 on non-vector targets

Ping. Testsuite fixup similar to: https://inbox.sourceware.org/gcc-patches/974e9e5e-8f07-46dd-b9b9-db8aa4685...@gmail.com/T/#t https://inbox.sourceware.org/gcc-patches/7e78cd70-70c9-41b1-8a98-6977a1034...@rivosinc.com/T/#t Patrick On Thu, Nov 2, 2023 at 12:09 PM Patrick O'Neill wrote:

Re: [PATCH v2] RISC-V: Implement target attribute

On Tue, Nov 14, 2023 at 3:15 PM Kito Cheng wrote: > > The target attribute which proposed in [1], target attribute allow user > to specify a local setting per-function basis. > > The syntax of target attribute is `__attribute__((target("")))`. > > and the syntax of `` describes below: > ``` >

[PATCH] rs6000: Disassemble opaque modes using subregs to allow optimizations [PR109116]

PR109116 exposes an issue where using unspecs to access each vector component of an opaque mode variable leads to unneeded register copies, because our rtl optimizers cannot handle unspecs. Instead, use subregs to access each vector component of the opaque mode variable, which our optimizers know

Re: [PATCH 0/3] Option handling: add documentation URLs

On Wed, 15 Nov 2023, David Malcolm wrote: > As mentioned, I'm currently investigating capturing per-language option > URLs (to address Iain's and Marc's comments about D and Ada); if I get > that working, I may need to add a similar note for adding a new > frontend. > > Hope the overall approach

Re: [PATCH] Fix crash in libcc1

On 11/14/23 22:30, Tom Tromey wrote: The gdb tests of the libcc1 plugin have been failing lately. I tracked this down to a crash trying to access an enum's underlying type. This patch fixes the crash by setting this type. libcc1/ChangeLog * libcc1plugin.cc

Re: [PATCH 0/4] gcov: Improve -fprofile-update=atomic

On 11/14/23 15:08, Sebastian Huber wrote: Sebastian Huber (4): gcov: Remove TARGET_GCOV_TYPE_SIZE target hook Add TARGET_HAVE_LIBATOMIC gcov: Add gen_counter_update() gcov: Improve -fprofile-update=atomic gcc/c-family/c-cppbuiltin.cc | 4 +- gcc/config/rtems.h |

[PATCH] RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]

Fix __riscv_unaligned_fast/slow/avoid macro name to __riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): update macro name gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-1.c:

Re: [PATCH] c++: constantness of call to function pointer [PR111703]

On 11/15/23 13:03, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/13/12 (to match the PR107939 / r13-6525-ge09bc034d1b4d6 backports)? -- >8 -- potential_constant_expression for a CALL_EXPR to a non-overload tests FUNCTION_POINTER_TYPE_P on

Re: [PATCH] RISC-V: Save/restore ra register correctly [PR112478]

On Tue, Nov 14, 2023 at 3:15 PM Kito Cheng wrote: > > We set ra to fixed register now, but we still need to save/restore that at > prologue/epilogue if that has used. So before 71f906498ada9 $ra was neither a fixed nor a used register. Therefore, riscv_save_reg_p returned true in the first test

Re: [PATCH v3] c++: fix parsing with auto(x) [PR112410]

On 11/15/23 17:24, Marek Polacek wrote: On Tue, Nov 14, 2023 at 05:27:03PM -0500, Jason Merrill wrote: On 11/14/23 10:58, Marek Polacek wrote: On Mon, Nov 13, 2023 at 09:26:41PM -0500, Jason Merrill wrote: On 11/10/23 20:13, Marek Polacek wrote: On Thu, Nov 09, 2023 at 07:07:03PM -0500,

Re: [PATCH 0/3] Option handling: add documentation URLs

On Tue, 2023-11-14 at 00:12 +, Joseph Myers wrote: > On Fri, 10 Nov 2023, David Malcolm wrote: > > > The .opt.urls files it generates become part of the source tree, > > and > > would be regenerated by maintainers whenever new options are added. > > Forgetting to update the files (or not

Re: building GNU gettext on AIX

David Edelsohn wrote: > I am using my own install of GCC for a reason. I have built GNU gettext 0.22.3 in various configurations on the AIX 7.1 and 7.3 machines in the compilefarm, and haven't encountered issues with 'max_align_t' nor with 'getpeername'. So, from my point of view, GNU gettext

[PATCH v3] c++: fix parsing with auto(x) [PR112410]

On Tue, Nov 14, 2023 at 05:27:03PM -0500, Jason Merrill wrote: > On 11/14/23 10:58, Marek Polacek wrote: > > On Mon, Nov 13, 2023 at 09:26:41PM -0500, Jason Merrill wrote: > > > On 11/10/23 20:13, Marek Polacek wrote: > > > > On Thu, Nov 09, 2023 at 07:07:03PM -0500, Jason Merrill wrote: > > > > >

Re: Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

OK. Make sense。 LGTM as long as you remove all GET_MODE_BITSIZE (GET_MODE_INNER (mode)) <= GET_MODE_BITSIZE (Pmode) juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-16 04:30 To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: Disallow 64-bit

Re: building GNU gettext on AIX

On Wed, Nov 15, 2023 at 4:22 PM Bruno Haible wrote: > David Edelsohn wrote: > > When I try to configure gettext-0.22.3, I receive the following error: > > > > checking for socklen_t equivalent... configure: error: Cannot find a type > > to use in place of socklen_t > > > > configure: error: > >

[committed] i386: Optimize strict_low_part QImode insn with high input registers

Following testcase: struct S1 { unsigned char val; unsigned char pad1; unsigned short pad2; }; struct S2 { unsigned char pad1; unsigned char val; unsigned short pad2; }; struct S1 test_add (struct S1 a, struct S2 b, struct S2 c) { a.val = b.val + c.val; return a; } compiles

Re: building GNU gettext on AIX

David Edelsohn wrote: > When I try to configure gettext-0.22.3, I receive the following error: > > checking for socklen_t equivalent... configure: error: Cannot find a type > to use in place of socklen_t > > configure: error: > /nasfarm/edelsohn/src/gettext-0.22.3/libtextstyle/configure failed

Re: Darwin: Replace environment runpath with embedded [PR88590]

> So I currently see the following in my build logs: > >[...] >mkdir -p -- ./fixincludes >Configuring in ./fixincludes >configure: creating cache ./config.cache >[...]/source-gcc/fixincludes/configure: line 3030: >

Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

On 11/15/23 15:29, 钟居哲 wrote: > Could you show me the example ? > > It's used by handling SEW = 64 on RV32. I don't know why this patch touch > this code. Use gather_load_run-1.c with the 64-bit index patterns disabled on rv32. We insert (mem:DI (reg:SI)) into a vector so use the SEW = 64

[COMMITTED] Regenerate libiberty/aclocal.m4 with aclocal 1.15.1

There is a new buildbot check that all autotool files are generated with the correct versions (automake 1.15.1 and autoconf 2.69). https://builder.sourceware.org/buildbot/#/builders/gcc-autoregen Correct one file that was generated with the wrong version. libiberty/ * aclocal.m4:

Re: Darwin: Replace environment runpath with embedded [PR88590]

Hi! On 2023-10-30T19:08:18+, Iain Sandoe wrote: >> On 30 Oct 2023, at 16:31, FX Coudert wrote: >> >>> +enable_darwin_at_rpath_$1=no >> >> I actually don’t understand why this one would have $1 in the name, unlike >> all other regenerated configure files. What value do we expect for $1 at

Re: [PATCH v3 0/2] Replace intl/ with out-of-tree GNU gettext

On Wed, Nov 15, 2023 at 9:22 AM Arsen Arsenović wrote: > > David Edelsohn writes: > > > GCC had been working on AIX with NLS, using "--with-included-gettext". > > --disable-nls gets past the breakage, but GCC does not build for me on > AIX > > with NLS enabled. > > That should still work with

Re: building GNU gettext on AIX

When I try to configure gettext-0.22.3, I receive the following error: checking for socklen_t equivalent... configure: error: Cannot find a type to use in place of socklen_t configure: error: /nasfarm/edelsohn/src/gettext-0.22.3/libtextstyle/configure failed for libtextstyle configure:43943:

Re: [PATCH] RISC-V: Fix ICE in non-canonical march parsing

Does relax mean no longer enforcing the canonical order of extensions? Patrick On 11/14/23 17:52, Kito Cheng wrote: LGTM, and BTW...I am thinking we could relax the canonical order during parsing, did you have interesting and time working on that item? On Wed, Nov 15, 2023 at 9:35 AM Patrick

[Committed] RISC-V: Fix ICE in non-canonical march parsing

Updated testcase names and committed. Thanks, Patrick --- Passing in a base extension in non-canonical order (i, e, g) causes GCC to ICE: xgcc: error: '-march=rv64ge': ISA string is not in canonical order. 'e' xgcc: internal compiler error: in add, at common/config/riscv/riscv-common.cc:671

[PATCH] c++: constantness of call to function pointer [PR111703]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/13/12 (to match the PR107939 / r13-6525-ge09bc034d1b4d6 backports)? -- >8 -- potential_constant_expression for a CALL_EXPR to a non-overload tests FUNCTION_POINTER_TYPE_P on the callee rather than on the type of the

Re: [PATCH 04/14] c++: use _P() defines from tree.h

On Tue, 8 Aug 2023 16:31:39 -0400 Jason Merrill wrote: > On 8/2/23 12:51, Patrick Palka via Gcc-patches wrote: > > On Thu, Jun 1, 2023 at 2:11 PM Bernhard Reutner-Fischer > > wrote: > >> > >> Hi David, Patrick, > >> > >> On Thu, 1 Jun 2023 18:33:46 +0200 > >> Bernhard Reutner-Fischer wrote:

[Committed] RISC-V: fix vsetvli pass testsuite failure [PR/112447]

From: Juzhe-Zhong Fixes: f0e28d8c1371 ("RISC-V: Fix failed hoist in LICM of vmv.v.x instruction") Since above commit, we have following failure: FAIL: gcc.c-torture/execute/memset-3.c -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions execution test FAIL:

[Committed] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

RV64 compare and branch instructions only support 64-bit operands. At Expand time, the backend conservatively zero/sign extends its operands even if not needed, such as incoming function args which ABI/ISA guarantee to be sign-extended already (this is true for SI, HI, QI operands) And

Re: [PATCH v3 0/2] Replace intl/ with out-of-tree GNU gettext

On Wed, Nov 15, 2023 at 9:22 AM Arsen Arsenović wrote: > > David Edelsohn writes: > > > GCC had been working on AIX with NLS, using "--with-included-gettext". > > --disable-nls gets past the breakage, but GCC does not build for me on > AIX > > with NLS enabled. > > That should still work with

[PATCH 4/6]AArch64: Add new generic-armv9-a CPU and make it the default for Armv9

Hi All, This patch adds a new generic scheduling model "generic-armv9-a" and makes it the default for all Armv9 architectures. -mcpu=generic and -mtune=generic is kept around for those that really want the deprecated cost model. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.

[PATCH 6/6]AArch64: only emit mismatch error when features would be disabled.

Hi All, At the moment we emit a warning whenever you specify both -march and -mcpu and the architecture of them differ. The idea originally was that the user may not be aware of this change. However this has a few problems: 1. Architecture revisions is not an observable part of the

[PATCH 3/6]AArch64: Add new generic-armv8-a CPU and make it the default.

Hi All, This patch adds a new generic scheduling model "generic-armv8-a" and makes it the default for all Armv8 architectures. -mcpu=generic and -mtune=generic is kept around for those that really want the deprecated cost model. This shows on SPECCPU 2017 the following: generic: SPECINT 1.0%

[PATCH 2/6]AArch64: Remove special handling of generic cpu.

Hi All, In anticipation of adding new generic turning values this removes the hardcoding of the "generic" CPU and instead just specifies it as a normal CPU. No change in behavior is expected. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar

[PATCH]AArch64: only discount MLA for vector and scalar statements

Hi All, In testcases gcc.dg/tree-ssa/slsr-19.c and gcc.dg/tree-ssa/slsr-20.c we have a fairly simple computation. On the current generic costing we generate: f: add w0, w0, 2 maddw1, w0, w1, w1 lsl w0, w1, 1 ret but on any other cost model but

Re: [PATCH] Add support for function attributes and variable attributes

David: another thing I remember you mentioned when you reviewed an earlier version of this patch is the usage of `std::pair`. I can't find where you said that, but I remember you mentioned that we should use a struct instead. Can you please elaborate again? Thanks. On Wed, 2023-11-15 at 17:53

[PATCH] Add support for function attributes and variable attributes

Hi, This patch adds the (incomplete) support for function and variable attributes. The added attributes are the ones we're using in rustc_codegen_gcc but all the groundwork is done to add more (and we will very likely add more as we didn't add all the ones we use in rustc_codegen_gcc yet). The

[PATCH] Fortran: fix reallocation on assignment of polymorphic variables [PR110415]

This patch adds the testcase from PR110415 and fixes the bug. The problem is that in a couple of places in trans_class_assignment in trans-expr.cc, we need to get the run-time size of the polymorphic object from the vtbl, but we are currently getting that vtbl from the lhs of the assignment

Re: [PATCH v3 0/2] Replace intl/ with out-of-tree GNU gettext

On Wed, 2023-11-15 at 15:14 +0100, Arsen Arsenović wrote: > That is interesting.  They should be using the same checks.  I've > checked trunk and regenerated files on it, and saw no significant diff > (some whitespace changes only).  Could you post the config.log of > both? You did not regenerate

Re: PR111754

On Wed, 8 Nov 2023 at 21:57, Prathamesh Kulkarni wrote: > > On Thu, 26 Oct 2023 at 09:43, Prathamesh Kulkarni > wrote: > > > > On Thu, 26 Oct 2023 at 04:09, Richard Sandiford > > wrote: > > > > > > Prathamesh Kulkarni writes: > > > > On Wed, 25 Oct 2023 at 02:58, Richard Sandiford > > > >

[committed] i386: Fix strict_low_part QImode insn with high input register patterns [PR112540]

PR target/112540 gcc/ChangeLog: * config/i386/i386.md (*addqi_ext_1_slp): Correct operand numbers in split pattern. Replace !Q constraint of operand 1 with !qm. Add insn constrain. (*subqi_ext_1_slp): Ditto. (*qi_ext_1_slp): Ditto. Bootstrapped and regression tested on

[PATCH]AArch64 Add pattern for unsigned widenings (uxtl) to zip{1,2}

Hi All, This changes unpack instructions to use zip{1,2} when doing a zero-extending widening operation. Permutes generally have a higher throughput than the widening operations. Zeros are shuffled into the top half of the registers. The testcase void d2 (unsigned * restrict a, unsigned short

[PATCH]middle-end: skip checking loop exits if loop malformed [PR111878]

Hi All, Before my refactoring if the loop->latch was incorrect then find_loop_location skipped checking the edges and would eventually return a dummy location. It turns out that a loop can have loops_state_satisfies_p (LOOPS_HAVE_RECORDED_EXITS) but also not have a latch in which case

nvptx: Fix copy'n'paste-o in '__builtin_nvptx_brev' description (was: [PATCH] nvptx: Add suppport for __builtin_nvptx_brev instrinsic)

Hi! On 2023-05-06T17:04:57+0100, "Roger Sayle" wrote: > This patch adds support for (a pair of) bit reversal intrinsics > __builtin_nvptx_brev and __builtin_nvptx_brevll which perform 32-bit > and 64-bit bit reversal (using nvptx's brev instruction) matching > the __brev and __brevll instrinsics

Re: [nvptx PATCH] Update nvptx's bitrev2 pattern to use BITREVERSE rtx.

Hi! On 2023-06-08T00:09:00+0100, "Roger Sayle" wrote: > This minor tweak to the nvptx backend switches the representation of > of the brev instruction from an UNSPEC to instead use the new BITREVERSE > rtx. ACK. > This allows various RTL optimizations including evaluation (constant > folding)

Re: Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

Could you show me the example ? It's used by handling SEW = 64 on RV32. I don't know why this patch touch this code. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-15 22:27 To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: Disallow 64-bit

nvptx: Extend 'brev' test cases (was: [PATCH] nvptx: Add suppport for __builtin_nvptx_brev instrinsic)

Hi! On 2023-05-06T17:04:57+0100, "Roger Sayle" wrote: > This patch adds support for (a pair of) bit reversal intrinsics > __builtin_nvptx_brev and __builtin_nvptx_brevll which perform 32-bit > and 64-bit bit reversal (using nvptx's brev instruction) matching > the __brev and __brevll instrinsics

Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

> Looks wrong. Recover back. When we demote we use two elements where there was one before. Therefore the vector needs to be able to hold twice as many elements. We adjust vl correctly but the mode is not here. Regards Robin

RE: [PATCH 8/21]middle-end: update vectorizable_live_reduction with support for multiple exits and different exits

> -Original Message- > From: Richard Biener > Sent: Wednesday, November 15, 2023 1:42 PM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com > Subject: RE: [PATCH 8/21]middle-end: update vectorizable_live_reduction > with support for multiple exits and

Re: [PATCH v3 0/2] Replace intl/ with out-of-tree GNU gettext

David Edelsohn writes: > GCC had been working on AIX with NLS, using "--with-included-gettext". > --disable-nls gets past the breakage, but GCC does not build for me on AIX > with NLS enabled. That should still work with gettext 0.22+ extracted in-tree (it should be fetched by

RE: [PATCH 7/21]middle-end: update IV update code to support early breaks and arbitrary exits

> -Original Message- > From: Richard Biener > Sent: Wednesday, November 15, 2023 1:23 PM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com > Subject: RE: [PATCH 7/21]middle-end: update IV update code to support early > breaks and arbitrary exits > > On Wed,

[committed] amdgcn: Add Accelerator VGPR registers

AMD GPUs since CDNA1 have had a new register file with an additional 256 32-bit-by-64-lane vector registers. This doubles the number of vector registers on the device, compared to previous models. The way the hardware works is that the register file is divided between all the running

[committed] amdgcn: simplify secondary reload patterns

This patch makes no functional changes, but cleans up the code a little to make way for my next patch. The confusung "reload_in" and "reload_out" define_expand were used solely for secondary reload and were nothing more than aliases for the "sgprbase" instructions. I've now learned that the

RE: [PATCH 8/21]middle-end: update vectorizable_live_reduction with support for multiple exits and different exits

On Wed, 15 Nov 2023, Tamar Christina wrote: > Patch updated to trunk. > > This adds support to vectorizable_live_reduction to handle multiple exits by vectorizable_live_operation, but I do wonder how you handle reductions? > doing a search for which exit the live value should be materialized

Re: [PATCH] s390: Fix generation of s390-gen-builtins.h

On 11/15/23 14:29, Stefan Schulze Frielinghaus wrote: > By default the preprocessed output includes linemarkers. This leads to > an error if -pedantic is used as e.g. during bootstrap: > > s390-gen-builtins.h:1:3: error: style of line directive is a GCC extension > [-Werror] > > Fixed by

[PATCH] s390: Fix generation of s390-gen-builtins.h

By default the preprocessed output includes linemarkers. This leads to an error if -pedantic is used as e.g. during bootstrap: s390-gen-builtins.h:1:3: error: style of line directive is a GCC extension [-Werror] Fixed by omitting linemarkers while generating s390-gen-builtins.h.

RE: [PATCH 7/21]middle-end: update IV update code to support early breaks and arbitrary exits

On Wed, 15 Nov 2023, Tamar Christina wrote: > > -Original Message- > > From: Richard Biener > > Sent: Wednesday, November 15, 2023 1:01 PM > > To: Tamar Christina > > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com > > Subject: RE: [PATCH 7/21]middle-end: update IV update code

[PATCH] s390: implement flags output

Implement flags output for inline assemblies. Only use one output constraint that captures the whole condition code. No breakout into different condition codes is allowed. Also, only one condition code variable is allowed. Add further logic to canonicalize various cases where we combine

[PATCH] s390: split int128 load

Issue two loads when using GPRs instead of one load-multiple. Bootstrapped and tested on s390. OK for mainline? gcc/ChangeLog: * config/s390/s390.md: Split TImode loads. gcc/testsuite/ChangeLog: * gcc.target/s390/int128load.c: New test. Signed-off-by: Juergen Christ ---

[PATCH] s390: Fix ICE in testcase pr89233

When using GNU vector extensions, an access outside of the vector size caused an ICE on s390. Fix this by aligning with the vec_extract builtin, i.e., computing constant index modulo number of lanes. Fixes testcase gcc.target/s390/pr89233.c. Bootstrapped and tested on s390. OK for mainline?

RE: [PATCH 7/21]middle-end: update IV update code to support early breaks and arbitrary exits

> -Original Message- > From: Richard Biener > Sent: Wednesday, November 15, 2023 1:01 PM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com > Subject: RE: [PATCH 7/21]middle-end: update IV update code to support early > breaks and arbitrary exits > > On Wed,

RE: [PATCH 7/21]middle-end: update IV update code to support early breaks and arbitrary exits

On Wed, 15 Nov 2023, Tamar Christina wrote: > Patch updated to latest trunk: > > Hi All, > > This changes the PHI node updates to support early breaks. > It has to support both the case where the loop's exit matches the normal loop > exit and one where the early exit is "inverted", i.e. it's an

RE: [PATCH 4/21]middle-end: update loop peeling code to maintain LCSSA form for early breaks

On Wed, 15 Nov 2023, Tamar Christina wrote: > Patch updated to latest trunk, > > This splits the part of the function that does peeling for loops at exits to > a different function. In this new function we also peel for early breaks. > > Peeling for early breaks works by redirecting all early

Re: building GNU gettext on AIX

[CCing bug-gettext] David Edelsohn wrote in : > The current gettext-0.22.3 fails to build for me on AIX. Here are some hints to get a successful build of GNU gettext on AIX: 1. Set the recommended environment variables before

Re: [PATCH v4] gcc: Introduce -fhardened

On Fri, Nov 03, 2023 at 06:51:16PM -0400, Marek Polacek wrote: > + if (flag_hardened) > + { > + if (!fortify_seen_p && optimize > 0) > + { > + if (TARGET_GLIBC_MAJOR == 2 && TARGET_GLIBC_MINOR >= 35) > + cpp_define (parse_in, "_FORTIFY_SOURCE=3"); > +

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