On Fri, 8 Dec 2023, Filip Kastl wrote:
> > > Hi,
> > >
> > > this is a patch that I submitted two months ago as an RFC. I added some
> > > polish
> > > since.
> > >
> > > It is a new lightweight pass that removes redundant PHI functions and as a
> > > bonus does basic copy propagation. With
LGTM.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2023-12-13 19:12
To: gcc-patches@gcc.gnu.org
CC: juzhe.zh...@rivai.ai; pan2...@intel.com
Subject: [PATCH v2] RISC-V: Fix dynamic lmul tests depended on abi
Some toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file or
Some toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file or directory
Fix method suggested by Juzhe-Zhong
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/riscv_vector.h: New file.
Signed-off-by: demin.han
---
On Wed, Dec 13, 2023 at 11:03:50AM +, Andre Vieira (lists) wrote:
> Hmm I think I understand what you are saying, but I'm not sure I agree.
> So before I enabled simdclone testing for aarch64, this test had no target
> selectors. So it checked the same for 'all simdclone test targets'.
Several typos have been found and fixed: missing semicolons, using
variable name instead of type and wrong types.
gcc/ChangeLog:
* doc/extend.texi(__lsx_vabsd_di): remove extra `i' in name.
(__lsx_vfrintrm_d, __lsx_vfrintrm_s, __lsx_vfrintrne_d,
__lsx_vfrintrne_s,
On 13/12/2023 10:55, Jakub Jelinek wrote:
On Wed, Dec 13, 2023 at 10:43:16AM +, Andre Vieira (lists) wrote:
Hi,
Apologies for the delay and this mixup. I need to do something different
This is to fix testisms initially introduced by:
commit f5fc001a84a7dbb942a6252b3162dd38b4aae311
On Wed, Dec 13, 2023 at 11:55:52AM +0100, Jakub Jelinek wrote:
> On Wed, Dec 13, 2023 at 10:43:16AM +, Andre Vieira (lists) wrote:
> > --- a/libgomp/testsuite/libgomp.c/declare-variant-1.c
> > +++ b/libgomp/testsuite/libgomp.c/declare-variant-1.c
> > @@ -40,16 +40,17 @@ f04 (int a)
> > int
>
On Wed, Dec 13, 2023 at 10:43:16AM +, Andre Vieira (lists) wrote:
> Hi,
>
> Apologies for the delay and this mixup. I need to do something different
>
> This is to fix testisms initially introduced by:
> commit f5fc001a84a7dbb942a6252b3162dd38b4aae311
> Author: Andre Vieira
> Date: Mon
On Linux/x86_64,
788e0d48ec639d44294434f4f20ae94023c3759d is the first bad commit
commit 788e0d48ec639d44294434f4f20ae94023c3759d
Author: Peter Bergner
Date: Tue Dec 12 16:46:16 2023 -0600
testsuite: Add testcase for already fixed PR [PR112822]
caused
FAIL: g++.dg/pr112822.C
On Linux/x86_64,
a01462ae8bafa86e7df47a252917ba6899d587cf is the first bad commit
commit a01462ae8bafa86e7df47a252917ba6899d587cf
Author: Jonathan Wakely
Date: Mon Dec 11 15:33:59 2023 +
libstdc++: Fix std::format output of %C for negative years
caused
FAIL: std/time/year/io.cc
Hi,
Apologies for the delay and this mixup. I need to do something different
This is to fix testisms initially introduced by:
commit f5fc001a84a7dbb942a6252b3162dd38b4aae311
Author: Andre Vieira
Date: Mon Dec 11 14:24:41 2023 +
aarch64: enable mixed-types for aarch64 simdclones
On 12/12/2023 15:58, Richard Sandiford wrote:
> Alex Coplan writes:
> > Hi,
> >
> > This is a v2 version which addresses feedback from Richard's review
> > here:
> >
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637648.html
> >
> > I'll reply inline to address specific comments.
> >
Hi Roger,
It looks good to me.
Thank you for your contribution,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Tuesday, December 5, 2023 4:00 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Add *extvsi_n_0 define_insn_and_split for PR 110717.
This
Hi, Kito.
Vector crypto ISA is ratifed, but intrinsics is not.
I wonder what the schedule of vector crypto intrinsic ?
Will it be ratified before GCC-14 release
(I personally think intrinsics stuff can be considered to be merged until the
end of GCC-14, like I did in GCC-13 push
+multiple_p (GET_MODE_BITSIZE (e.arg_mode (0)),
+GET_MODE_BITSIZE (e.arg_mode (1)), );
Change it into gcc_assert (multiple_p (...))
+/* A list of all Vector Crypto intrinsic functions. */
+static function_group_info cryoto_function_groups[] = {
+#define
On Wed, 13 Dec 2023, Juzhe-Zhong wrote:
> Hi, before this patch, a simple conversion case for RVV codegen:
>
> foo:
> ble a2,zero,.L8
> addiw a5,a2,-1
> li a4,6
> bleua5,a4,.L6
> srliw a3,a2,3
> sllia3,a3,3
> add
On Wed, 13 Dec 2023, Jakub Jelinek wrote:
> Hi!
>
> The following testcase ICEs, because a PHI argument from latch edge
> uses a SSA_NAME set only in a conditionally executed block inside of the
> loop.
> This happens when we have some outer cast which lowers its operand several
> times, under
LGTM
On Wed, Dec 13, 2023 at 5:14 PM Feng Wang wrote:
>
> Patch v2: Change the implied ISA info using the minimum set and add
> dependencies info into the python script.
>
> Due to the crypto vector entension is depend on the Vector extension,
> so the "v" info is added into implied ISA info
Hi!
The following testcase ICEs, because a PHI argument from latch edge
uses a SSA_NAME set only in a conditionally executed block inside of the
loop.
This happens when we have some outer cast which lowers its operand several
times, under some condition with variable index, under different
Hi!
With valgrind checking, there are various errors reported on some C++26
libstdc++ tests, like:
==2009913== Conditional jump or move depends on uninitialised value(s)
==2009913==at 0x914C59: gt_ggc_mx_lang_tree_node(void*) (gt-cp-tree.h:107)
==2009913==by 0x8AB7A5:
+(define_insn "@pred_vandn_scalar"
+ [(set (match_operand:VI 0 "register_operand" "=vd, vr,vd, vr")
+(if_then_else:VI
+ (unspec:
+[(match_operand: 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
+ (match_operand 5 "vector_length_operand"" rK,
Hi!
The following patch makes most of x86 MD builtins nothrow,leaf
(like most middle-end builtins are). For -fnon-call-exceptions it
doesn't nothrow, better might be to still add it if the builtins
don't read or write memory and can't raise floating point exceptions,
but we don't have such
Hi, before this patch, a simple conversion case for RVV codegen:
foo:
ble a2,zero,.L8
addiw a5,a2,-1
li a4,6
bleua5,a4,.L6
srliw a3,a2,3
sllia3,a3,3
add a3,a3,a0
mv a5,a0
mv a4,a1
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vector ins into RATIO attr and use vr as
destination register.
This patch add the crypto machine descriptions(vector-crypto.md) and
some new iterators which are used by crypto vector ext.
Co-Authored by: Songhe Zhu
Co-Authored
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic
Patch v2: Change the implied ISA info using the minimum set and add
dependencies info into the python script.
Due to the crypto vector entension is depend on the Vector extension,
so the "v" info is added into implied ISA info with the corresponding
crypto vector extension.
gcc/ChangeLog:
When investigating PR111591 with respect to TBAA and stack slot sharing
I noticed we're eventually scrapping a [TARGET_]MEM_REF offset when
rewriting the VAR_DECL base of the MEM_EXPR to use a pointer to the
partition instead. The following makes sure to preserve that.
Bootstrapped and tested on
On Wed, Dec 13, 2023 at 9:22 AM Liao Shihua wrote:
>
> In Scalar Crypto Built-In functions, some require immediate parameters,
> But register_operand are incorrectly used in the pattern.
>
> E.g.:
>__builtin_riscv_aes64ks1i(rs1,1)
>Before:
> li a5,1
> aes64ks1i a0,a0,a5
>
>
On Wed, Dec 13, 2023 at 9:14 AM Di Zhao OS
wrote:
>
> Hello Richard,
>
> > -Original Message-
> > From: Richard Biener
> > Sent: Monday, December 11, 2023 7:01 PM
> > To: Di Zhao OS
> > Cc: gcc-patches@gcc.gnu.org
> > Subject: Re: [PATCH v4] [tree-optimization/110279] Consider FMA in
>
On 2023/12/13 16:48, Dan Li wrote:
> + Likun
>
> On Tue, 28 Mar 2023 at 06:18, Sami Tolvanen wrote:
>> On Mon, Mar 27, 2023 at 2:30 AM Peter Zijlstra wrote:
>>> On Sat, Mar 25, 2023 at 01:54:16AM -0700, Dan Li wrote:
>>>
In the compiler part[4], most of the content is the same as Sami's
On Wed, Dec 13, 2023 at 4:05 AM Alexandre Oliva wrote:
>
> On Dec 12, 2023, Richard Biener wrote:
>
> > On Tue, Dec 12, 2023 at 3:03 AM Alexandre Oliva wrote:
>
> >> DECL_NOT_GIMPLE_REG_P (arg) = 0;
>
> > I wonder why you clear this at all?
>
> That code seems to be inherited from expand_thunk.
On Tue, Dec 12, 2023 at 04:17:47PM +, Andrew Stubbs wrote:
> On 12/12/2023 10:05, Tobias Burnus wrote:
> > Hi Andrew,
> >
> > On 11.12.23 18:04, Andrew Stubbs wrote:
> > > This creates a new predefined allocator as a shortcut for using pinned
> > > memory with OpenMP. The name uses the
+ Likun
On Tue, 28 Mar 2023 at 06:18, Sami Tolvanen wrote:
>
> On Mon, Mar 27, 2023 at 2:30 AM Peter Zijlstra wrote:
> >
> > On Sat, Mar 25, 2023 at 01:54:16AM -0700, Dan Li wrote:
> >
> > > In the compiler part[4], most of the content is the same as Sami's
> > > implementation[3], except for
On Wed, 13 Dec 2023, Jakub Jelinek wrote:
> Hi!
>
> The r14-6076 change changed the allocation of attribute tables from
> table = new attribute_spec[2];
> to
> table = new attribute_spec { ... };
> with
> ignored_attributes_table.safe_push (table);
> later in both cases, but didn't change the
On Wed, Dec 13, 2023 at 4:44 PM Jakub Jelinek wrote:
>
> Hi!
>
> The following patch fixes ICE on the testcase in similar way to how
> other folded builtins are handled in ix86_gimple_fold_builtin when
> they don't have a lhs; these builtins are const or pure, so normally
> DCE would remove them
The following avoids creating an unsupported VEC_PERM after vector
lowering from the pattern merging a bit-insert from a bit-field-ref
to a VEC_PERM. For the already existing s390 testcase we get
TImode vectors which later ICE during attempted expansion of
a vec_perm_const.
Pushed accidentially
Hi!
The following patch fixes ICE on the testcase in similar way to how
other folded builtins are handled in ix86_gimple_fold_builtin when
they don't have a lhs; these builtins are const or pure, so normally
DCE would remove them later, but with -O0 that isn't guaranteed to
happen, and during
The following does away with the fake edge adding as in the original
PR112961 fix and instead exposes handling of entry PHIs as additional
parameter of the region VN run.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
PR tree-optimization/112991
PR
Hi!
On the c-c++-common/cpp/pr88974.c testcase I'm seeing
==600549== Conditional jump or move depends on uninitialised value(s)
==600549==at 0x1DD3A05: cpp_get_token_1(cpp_reader*, unsigned int*)
(macro.cc:3050)
==600549==by 0x1DBFC7F: _cpp_parse_expr (expr.cc:1392)
==600549==by
Thanks for the suggestion.
The target selector method can not cover some cases.
On 2023/12/12 18:05, juzhe.zh...@rivai.ai wrote:
> A more reasonable solution is the add riscv_vector.h into
> gcc.dg/vect/costmodel/riscv/rvv
> with the following codes in riscv_vector.h:
>
> /* Wrapper of
> -Original Message-
> From: Gerald Pfeifer
> Sent: Wednesday, December 13, 2023 2:20 PM
> To: Jiang, Haochen
> Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ;
> ubiz...@gmail.com
> Subject: Re: [gcc-wwwdocs PATCH] gcc-13/14: Mention recent update for
> x86_64 backend
>
> On Fri, 8 Dec
Hi!
The r14-6076 change changed the allocation of attribute tables from
table = new attribute_spec[2];
to
table = new attribute_spec { ... };
with
ignored_attributes_table.safe_push (table);
later in both cases, but didn't change the corresponding delete in
free_attr_data, which means valgrind is
In Scalar Crypto Built-In functions, some require immediate parameters,
But register_operand are incorrectly used in the pattern.
E.g.:
__builtin_riscv_aes64ks1i(rs1,1)
Before:
li a5,1
aes64ks1i a0,a0,a5
Assembler messages:
Error: instruction aes64ks1i
Hello Richard,
> -Original Message-
> From: Richard Biener
> Sent: Monday, December 11, 2023 7:01 PM
> To: Di Zhao OS
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH v4] [tree-optimization/110279] Consider FMA in
> get_reassociation_width
>
> On Wed, Nov 29, 2023 at 3:36 PM Di Zhao
On Wed, Dec 13, 2023 at 08:51:16AM +0100, Richard Biener wrote:
> On Tue, 12 Dec 2023, Peter Bergner wrote:
>
> > On 12/12/23 8:36 PM, Jason Merrill wrote:
> > > This test is failing for me below C++17, I think you need
> > >
> > > // { dg-do compile { target c++17 } }
> > > or
> > > // {
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