Re: [PATCH] RISC-V: fix scalar crypto pattern

On 12/14/23 02:48, Christoph Müllner wrote: On Thu, Dec 14, 2023 at 1:40 AM Jeff Law wrote: On 12/13/23 02:03, Christoph Müllner wrote: On Wed, Dec 13, 2023 at 9:22 AM Liao Shihua wrote: In Scalar Crypto Built-In functions, some require immediate parameters, But register_operand are inco

Re: [PATCH v7 4/5] OpenMP/OpenACC: Unordered/non-constant component offset runtime diagnostic

On 19.08.23 00:47, Julian Brown wrote: This patch adds support for non-constant component offsets in "map" clauses for OpenMP (and the equivalants for OpenACC), which are not able to be sorted into order at compile time. Normally struct accesses in such clauses are gathered together and sorted i

Re: [pushed 1/4] c++: copy location to AGGR_INIT_EXPR

On Wed, Dec 13, 2023 at 08:38:12PM -0500, Jason Merrill wrote: > On 12/13/23 19:00, Marek Polacek wrote: > > On Wed, Dec 13, 2023 at 11:47:37AM -0500, Jason Merrill wrote: > > > Tested x86_64-pc-linux-gnu, applying to trunk. > > > > > > -- 8< -- > > > > > > When building an AGGR_INIT_EXPR from a

[pushed] analyzer: cleanups [PR112655]

Avoid copying eedges in infinite_loop::infinite_loop. Use initializer lists in the various places reported in PR analyzer/112655 (apart from coord_test's ctor, which would require nontrivial refactoring). Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-6549-g

Re: [PATCH v3 5/5] aarch64: Add function multiversioning support

Andrew Carlotti writes: > This adds initial support for function multiversioning on aarch64 using > the target_version and target_clones attributes. This loosely follows > the Beta specification in the ACLE [1], although with some differences > that still need to be resolved (possibly as follow-u

Re: Re: [PATCH] Middle-end: Adjust decrement IV style partial vectorization COST model

Thanks a lot for the clarification. I send a patch to remove address memory cost: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640595.html for decremnt IV/SELECT_VL. And I have tested various cases that are all get better codegen in RVV. juzhe.zh...@rivai.ai From: Richard Biener

[PATCH] aarch64: Improve handling of accumulators in early-ra

Being very simplistic, early-ra just models an allocno's live range as a single interval. This doesn't work well for single-register accumulators that are updated multiple times in a loop, since in SSA form, each intermediate result will be a separate SSA name and will remain separate from the acc

[PATCH] Middle-end: Do not model address cost for SELECT_VL style vectorization

Follow Richard's suggestions, we should not model address cost in the loop vectorizer for select_vl or decrement IV since other style vectorization doesn't do that. To make cost model comparison apple to apple. This patch set COST from 2 to 1 which turns out have better codegen in various codegen

[committed] Fix m68k testcase for c99

More fallout from the c99 conversion. The m68k specific test pr63347.c calls exit and abort without a prototype in scope. This patch turns them into __builtin calls avoiding the error. Bootstrapped and regression tested on m68k-linux-gnu, pushed to the trunk. Jeffcommit 679adb2396a911b599

Re: [PATCH] middle-end: Fix up constant handling in emit_conditional_move [PR111260]

On Wed, Dec 13, 2023 at 5:51 PM Andrew Pinski wrote: > > After r14-2667-gceae1400cf24f329393e96dd9720, we force a constant to a > register > if it is shared with one of the other operands. The problem is used the > comparison > mode for the register but that could be different from the operand m

In 'gcc/gimple-ssa-sccopy.cc', '#define INCLUDE_ALGORITHM' instead of '#include ' (was: [PATCH v4] A new copy propagation and PHI elimination pass)

Hi! On 2023-12-13T17:12:11+0100, Filip Kastl wrote: > --- /dev/null > +++ b/gcc/gimple-ssa-sccopy.cc > +#include Pushed to master branch commit 65e41f4fbfc539c5cc429c684176f8ea39f4b8f2 "In 'gcc/gimple-ssa-sccopy.cc', '#define INCLUDE_ALGORITHM' instead of '#include '", see attached. Grüße

RE: [PATCH 9/21]middle-end: implement vectorizable_early_exit for codegen of exit code

On Wed, 13 Dec 2023, Tamar Christina wrote: > > > > else if (vect_use_mask_type_p (stmt_info)) > > > > { > > > > unsigned int precision = stmt_info->mask_precision; > > > > scalar_type = build_nonstandard_integer_type (precision, 1); > > > > vectype = get_mask_type_for_scal

[committed] Revert "RISC-V: Add avail interface into function_group_info"

This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc. Will refactor this part in the same way as aarch64 sve. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Revert changes.

Re: Re: [PATCH] Middle-end: Adjust decrement IV style partial vectorization COST model

On Thu, 14 Dec 2023, juzhe.zh...@rivai.ai wrote: > Thanks Richard. > > Let me clarify again to make sure I understand your comments correctly: > > Do you suggest not to model address cost here like other partial > vectorization style (while_ult, avx512...etc). Then set COST = 1 since > we only

[PATCH v2] LoongArch: Fix incorrect code generation for sad pattern

When I attempt to enable vect_usad_char effective target for LoongArch, slp-reduc-sad.c and vect-reduc-sad*.c tests fail. These tests fail because the sad pattern generates bad code. This patch to fixed them, for sad patterns, use zero expansion instead of sign expansion for reduction. Currentl

Re: [PATCH] Revert "RISC-V: Add avail interface into function_group_info"

ok On Thu, Dec 14, 2023 at 8:08 PM Feng Wang wrote: > > This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc. > Will refactor this part in the same way as aarch64 sve. > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): >

Re: [PATCH v7] libgfortran: Replace mutex with rwlock

On Thu, Dec 14, 2023 at 01:29:01PM +0100, Thomas Schwinge wrote: > > Sure, I will look into that. > > > > BTW, I didn’t have the PowerPC in hands, do you mind granting the access of > > your > > test environment to me to help reproduce the issue? > > That's unfortunately not possible: it's behind

RE: [PATCH v7] libgfortran: Replace mutex with rwlock

Hi, Thomas Schwinge wrote:   On 2023-12-14T02:28:22+, "Zhu, Lipeng" wrote: On 2023/12/14 4:52, Thomas Schwinge wrote: >> I've just filed > Would

RE: [PATCH v7] libgfortran: Replace mutex with rwlock

Hi Lipeng! On 2023-12-14T02:28:22+, "Zhu, Lipeng" wrote: > On 2023/12/14 4:52, Thomas Schwinge wrote: >> On 2023-12-12T02:05:26+, "Zhu, Lipeng" wrote: >> > On 2023/12/12 1:45, H.J. Lu wrote: >> >> On Sat, Dec 9, 2023 at 7:25 PM Zhu, Lipeng >> wrote: >> >> > On 2023/12/9 23:23, Jakub Jel

[PATCH] Revert "RISC-V: Add avail interface into function_group_info"

This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc. Will refactor this part in the same way as aarch64 sve. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Revert changes.

Re: [PATCH] expmed: Get vec_extract element mode from insn_data, [PR112999]

Robin Dapp writes: > Hi, > > this is a bit of a follow up of the latest expmed change. > > In extract_bit_field_1 we try to get a better vector mode before > extracting from it. Better refers to the case when the requested target > mode does not equal the inner mode of the vector to extract from

[PATCH] LoongArch: Fix incorrect code generation for sad pattern

When I attempt to enable vect_usad_char effective target for LoongArch, some tests fail. These tests fail because the sad pattern generates bad code. This patch to fixed them, for sad patterns, use zero expansion instead of sign expansion for reduction. Currently, we are fixing failed vectorized t

Re: [PATCH] RISC-V: fix scalar crypto pattern

Sorry, I was not aware of this patch. Since Jeff's patch was here first and also includes more tests, I propose to move forward with his patch (but I'm not a maintainer!). Therefore, I've reviewed Jeff's patch and replied to his email. FWIW: Jeff's patch can be found here: https://gcc.gnu.org/

Re: Re: [PATCH] Middle-end: Adjust decrement IV style partial vectorization COST model

Thanks Richard. Let me clarify again to make sure I understand your comments correctly: Do you suggest not to model address cost here like other partial vectorization style (while_ult, avx512...etc). Then set COST = 1 since we only have SELECT_VL since beginning. At various cases we saw, COST=1

Re: [PATCH] Middle-end: Adjust decrement IV style partial vectorization COST model

Am 14.12.2023 um 09:28 schrieb juzhe.zh...@rivai.ai: Hi, Richard.I have a question about the decrement IV costing since I find the reduction case is generating inferior codegen.reduc_plus_int: mv a3,a0 ble a1,zero,.L7 addiw a5,a1,-1 li a4,2 bleu a5,a4,.L8 vsetivli zero,4,e32,m1,ta,ma srliw a4,a1,2

Re: [PATCH] match.pd: Simplify (t * u) / (t * v) [PR112994]

> Am 14.12.2023 um 08:37 schrieb Jakub Jelinek : > > Hi! > > On top of the previously posted patch, this simplifies say (x * 16) / (x * 4) > into 4. Unlike the previous pattern, this is something we didn't fold > previously on GENERIC, so I think it shouldn't be all wrapped with #if > GIMPLE

Re: [PATCH] match.pd: Simplify (t * u) / v -> t * (u / v) [PR112994]

> Am 14.12.2023 um 08:35 schrieb Jakub Jelinek : > > Hi! > > The following testcase is optimized just on GENERIC (using > strict_overflow_p = false; > if (TREE_CODE (arg1) == INTEGER_CST > && (tem = extract_muldiv (op0, arg1, code, NULL_TREE, >

Re: [PATCH v4] A new copy propagation and PHI elimination pass

Successfully bootstrapped and regtested on x86_64-linux. Will push to master. Filip

Re: [committed] testsuite: Fix up target-enter-data-1.c on 32-bit targets

On Thu, 14 Dec 2023 08:14:56 +0100 Jakub Jelinek wrote: > On Wed, Nov 29, 2023 at 11:43:05AM +, Julian Brown wrote: > > * c-c++-common/gomp/target-enter-data-1.c: Adjust scan > > output. > > struct bar { int num_vectors; double *vectors; }; > > is 16 bytes only on 64-bit targets, on 3

Re: [PATCH] RISC-V: fix scalar crypto pattern

On Thu, Dec 14, 2023 at 1:40 AM Jeff Law wrote: > On 12/13/23 02:03, Christoph Müllner wrote: > > On Wed, Dec 13, 2023 at 9:22 AM Liao Shihua wrote: > >> > >> In Scalar Crypto Built-In functions, some require immediate parameters, > >> But register_operand are incorrectly used in the pattern. > >

Re: [PR target/110201] Fix operand types for various scalar crypto insns

On Tue, Jun 20, 2023 at 12:34 AM Jeff Law via Gcc-patches wrote: > > > A handful of the scalar crypto instructions are supposed to take a > constant integer argument 0..3 inclusive. A suitable constraint was > created and used for this purpose (D03), but the operand's predicate is > "register_ope

Re: Re: [PATCH 5/5] [ifcvt] optimize extension for x=c ? (y op z) : y by RISC-V Zicond like insns

On 2023-12-11 13:46  Jeff Law wrote: > > > >On 12/5/23 01:12, Fei Gao wrote: >> SIGN_EXTEND, ZERO_EXTEND and SUBREG has been considered >> to support SImode in 64-bit machine. >> >> Co-authored-by: Xiao Zeng >> >> gcc/ChangeLog: >> >> * ifcvt.cc (noce_cond_zero_binary_op_supported): add support fo

Re: Re: [PATCH 4/5] [ifcvt] optimize x=c ? (y op const_int) : y by RISC-V Zicond like insns

On 2023-12-11 13:38  Jeff Law wrote: > > > >On 12/5/23 01:12, Fei Gao wrote: >> op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT, AND] >> >> Co-authored-by: Xiao Zeng >> >> gcc/ChangeLog: >> >>  * ifcvt.cc (noce_cond_zero_shift_op_supported): check if OP is >>shift

Re: Re: [PATCH] Middle-end: Adjust decrement IV style partial vectorization COST model

Hi, Richard. I have a question about the decrement IV costing since I find the reduction case is generating inferior codegen. reduc_plus_int: mv a3,a0 ble a1,zero,.L7 addiw a5,a1,-1 li a4,2 bleu a5,a4,.L8 vsetivli zero,4,e32,m1,ta,ma srliw a4,a1,2 vmv.v.i v1,0 slli a4,a4,4 add a4,a4,a0 mv a5,a0

Re: [PATCH] i386: Remove RAO-INT from Grand Ridge

On Thu, Dec 14, 2023 at 10:55 AM Haochen Jiang wrote: > > Hi all, > > According to ISE050 published at the end of September, RAO-INT will not > be in Grand Ridge anymore. This patch aims to remove it. > > The documentation comes following: > > https://cdrdv2.intel.com/v1/dl/getContent/671368 > > R

[PATCH] expmed: Get vec_extract element mode from insn_data, [PR112999]

Hi, this is a bit of a follow up of the latest expmed change. In extract_bit_field_1 we try to get a better vector mode before extracting from it. Better refers to the case when the requested target mode does not equal the inner mode of the vector to extract from and we have an equivalent tieabl

Re: [PATCH] LoongArch: Use the movcf2gr instruction to implement cstore4

On Thu, 2023-12-14 at 15:44 +0800, Jiahao Xu wrote: > The implementation of this patch has some issues. When I compile 521.wrf with > -Ofast -mlasx -flto -muse-movcf2gr, it results in an ICE: Indeed, creating CCCmode pseudos without a complete movfcc implementation is buggy. This patch needs a

<    1   2