[PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): New function. * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. *

[PATCH v3 3/6] RISC-V: Introduce XTheadVector as a subset of V1.0.0

This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Add new vendor

[PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns.

This patch splits the definition of csr_operand in predicates.md. The newly defined vector_csr_operand has the same functionality as csr_operand but can only be used in vector patterns, so that changes for vector will not affect scalar patterns in files like riscv.md. gcc/ChangeLog: *

[PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc

This patch moves the definition of the enums lst_type and frm_op_type into riscv-vector-builtins-bases.h and removes the static visibility of fold_fault_load(), so these can be used in other compile units. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (enum lst_type):

RE: [PATCH 3/21]middle-end: Implement code motion and dependency analysis for early breaks

On Wed, 20 Dec 2023, Tamar Christina wrote: > > > + /* If we've moved a VDEF, extract the defining MEM and update > > > + usages of it. */ > > > + tree vdef; > > > + /* This statement is to be moved. */ > > > + if ((vdef = gimple_vdef (stmt))) > > > +

[PATCH v3 0/6] RISC-V: Support XTheadVector extension

This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in order not to generate instructions that xtheadvector does

RE: Re: [PATCH] RISC-V: Fix calculation of max live vregs

Committed, thanks all. Pan From: juzhe.zh...@rivai.ai Sent: Wednesday, December 20, 2023 7:18 PM To: demin.han ; gcc-patches Cc: Li, Pan2 Subject: Re: Re: [PATCH] RISC-V: Fix calculation of max live vregs I see. LGTM. Thanks for explanation. I will ask Li Pan commit it for you. Thanks.

[PATCH] Support libcall __float{, un}sibf by SF when it is not supported for _bf16

We don't have SI -> BF library functions, use SI -> SF -> BF instead. Although this can also be implemented in a target machine description, it is more appropriate to move into target independent code. gcc/ChangeLog: * optabs.cc (expand_float): Split SI -> BF into SI -> SF -> BF. ---

Re: Re: [PATCH] RISC-V: Fix calculation of max live vregs

I see. LGTM. Thanks for explanation. I will ask Li Pan commit it for you. Thanks. juzhe.zh...@rivai.ai From: Demin Han Date: 2023-12-20 19:10 To: juzhe.zh...@rivai.ai; gcc-patches CC: pan2.li Subject: Re: [PATCH] RISC-V: Fix calculation of max live vregs Hi juzhe, The live ranges are

Re: [PATCH] RISC-V: Fix calculation of max live vregs

Hi juzhe, The live ranges are represented as [def_point, last_use_point] in code. For example: 0: _2 = _x1 + _x2 1: _3 = _y1 + _y2 2: _1 = _2 + _3 3: _4 = _1 + x1 Origin: live ranges: _1: [2, 3] _2: [0, 2] _3: [1, 2] _x1:[0, 3] max live regs calc: _1 _2 _3 _x1 0 x x 1

[no subject]

Greetings, I noticed you from LinkedIn? Can I share an idea on this email?

RE: [PATCH 3/21]middle-end: Implement code motion and dependency analysis for early breaks

> > + /* If we've moved a VDEF, extract the defining MEM and update > > +usages of it. */ > > + tree vdef; > > + /* This statement is to be moved. */ > > + if ((vdef = gimple_vdef (stmt))) > > + LOOP_VINFO_EARLY_BRK_CONFLICT_STMTS >

Re: [PATCH] i386: Make most MD builtins nothrow, leaf [PR112962]

On Wed, Dec 13, 2023 at 10:21 AM Jakub Jelinek wrote: > > Hi! > > The following patch makes most of x86 MD builtins nothrow,leaf > (like most middle-end builtins are). For -fnon-call-exceptions it > doesn't nothrow, better might be to still add it if the builtins > don't read or write memory and

Patch ping (Re: [PATCH] i386: Make most MD builtins nothrow, leaf [PR112962])

Hi! On Wed, Dec 13, 2023 at 10:21:43AM +0100, Jakub Jelinek wrote: > The following patch makes most of x86 MD builtins nothrow,leaf > (like most middle-end builtins are). For -fnon-call-exceptions it > doesn't nothrow, better might be to still add it if the builtins > don't read or write memory

Re: [PATCH 5/5] OpenMP: Add prettyprinter support for context selectors.

On 17.12.23 20:03, Sandra Loosemore wrote: With the change to use enumerators instead of strings to represent context selector and selector-set names, the default tree-list output for dumping selectors is less helpful for debugging and harder to use in test cases. This patch adds support for

Re: [PATCH] lower-bitint: Fix up handling of nested casts in mergeable stmt handling [PR112941]

On Wed, 20 Dec 2023, Jakub Jelinek wrote: > Hi! > > The following patch fixes 2 issues in handling of casts for mergeable > stmts. > The first hunk fixes the case when we have two nested casts (typically > after optimization that is zero-extension of a sign-extension because > everything else

Re: [PATCH] tree-optimization/113073 - amend PR112736 fix

On Wed, 20 Dec 2023, Thomas Schwinge wrote: > Hi! > > On 2023-12-19T13:30:58+0100, Richard Biener wrote: > > The PR112736 testcase fails on RISC-V because the aligned exception > > uses the wrong check. The alignment support scheme can be > > dr_aligned even when the access isn't aligned to

[PATCH] lower-bitint: Fix up handling of nested casts in mergeable stmt handling [PR112941]

Hi! The following patch fixes 2 issues in handling of casts for mergeable stmts. The first hunk fixes the case when we have two nested casts (typically after optimization that is zero-extension of a sign-extension because everything else should have been folded into a single cast). If the

Re: [PATCH] fold-const: Handle AND, IOR, XOR with stepped vectors [PR112971].

On Wed, 20 Dec 2023, Richard Sandiford wrote: > Richard Biener writes: > > On Tue, 19 Dec 2023, Andrew Pinski wrote: > > > >> On Tue, Dec 19, 2023 at 2:40?AM Richard Sandiford > >> wrote: > >> > > >> > Richard Biener writes: > >> > > On Tue, 19 Dec 2023, juzhe.zh...@rivai.ai wrote: > >> > > >

Re: [PATCH] RISC-V: Fix calculation of max live vregs

Hi, Han. It's awesome that some one want to optimize dynamic LMUL feature of GCC. I knew this feature is not stable yet and I failed to find the time to optimize it (Still busy with fixing bugs). Could you give me more details why this patch can refine those 2 cases with picking larger LMUL

Re: [PATCH] tree-optimization/113073 - amend PR112736 fix

Hi! On 2023-12-19T13:30:58+0100, Richard Biener wrote: > The PR112736 testcase fails on RISC-V because the aligned exception > uses the wrong check. The alignment support scheme can be > dr_aligned even when the access isn't aligned to the vector size > but some targets are happy with element

Re: [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

Hi, This has been tested with the following configurations: rv64gcv_zvl128b rv64gcv_zvl256b rv32imafd_zve32x1p0 rv32gc_zve64f_zvl128b I'll drop the constraints and add the testing info to the cover email in v3. I'll hold off submitting v3 until gcc-15 as requested. On Wed, Dec 20, 2023 at 5:38 

Re: [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension

Hi, this patchset has been tested with the following configurations: rv64gcv_zvl128b rv64gcv_zvl256b rv32imafd_zve32x1p0 rv32gc_zve64f_zvl128b Will fix the formatting in v3. Thanks On Wed, Dec 20, 2023 at 5:28 AM Jeff Law wrote: > > > On 12/19/23 02:53, Sergei Lewis wrote: > > gcc/ChangeLog

Re: [PATCH v3] RISC-V: Bugfix for the const vector in single steps

OK。 juzhe.zh...@rivai.ai From: pan2.li Date: 2023-12-20 17:35 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng; jeffreyalaw Subject: [PATCH v3] RISC-V: Bugfix for the const vector in single steps From: Pan Li This patch would like to fix the below execution failure when

[PATCH v3] RISC-V: Bugfix for the const vector in single steps

From: Pan Li This patch would like to fix the below execution failure when build with "-march=rv64gcv_zvl512b -mabi=lp64d -mcmodel=medlow --param=riscv-autovec-lmul=m8 -ftree-vectorize -fno-vect-cost-model -O3" FAIL: gcc.dg/vect/pr92420.c -flto -ffat-lto-objects execution test The will be one

Re: [PATCH v2] aarch64: Validate register operands early in ldp fusion pass [PR113062]

Alex Coplan writes: > This is a v2 addressing Richard's feedback, v1 was posted here: > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640957.html > > Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk? > > Thanks, > Alex > > -- >8 -- > > We were missing validation of the

Re: [PATCH] fold-const: Handle AND, IOR, XOR with stepped vectors [PR112971].

Richard Biener writes: > On Tue, 19 Dec 2023, Andrew Pinski wrote: > >> On Tue, Dec 19, 2023 at 2:40?AM Richard Sandiford >> wrote: >> > >> > Richard Biener writes: >> > > On Tue, 19 Dec 2023, juzhe.zh...@rivai.ai wrote: >> > > >> > >> Hi, Richard. >> > >> >> > >> After investigating the codes:

[PATCH v2] aarch64: Validate register operands early in ldp fusion pass [PR113062]

This is a v2 addressing Richard's feedback, v1 was posted here: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640957.html Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk? Thanks, Alex -- >8 -- We were missing validation of the candidate register operands in the ldp/stp

[PATCH] sched: Don't skip empty block by removing no_real_insns_p [PR108273]

Hi, This patch follows Richi's suggestion "scheduling shouldn't special case empty blocks as they usually do not appear" in [1], it removes function no_real_insns_p and its uses completely. There is some case that one block previously has only one INSN_P, but while scheduling some other blocks

[Patch, rs6000] Call library for block memory compare when optimizing for size

Hi, This patch call library function for block memory compare when it's optimized for size. Bootstrapped and tested on x86 and powerpc64-linux BE and LE with no regressions. Is this OK for trunk? Thanks Gui Haochen ChangeLog rs6000: Call library for block memory compare when optimizing for

[Patchv3, rs6000] Correct definition of macro of fixed point efficient unaligned

Hi, The patch corrects the definition of TARGET_EFFICIENT_OVERLAPPING_UNALIGNED and replace it with the call of slow_unaligned_access. Compared with last version, https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640832.html the main change is to pass alignment measured by bits to

[PATCH] RISC-V: Fix RISCV_FUSE_ZEXTWS fusion condition

From: wangpc The condition is RISCV_FUSE_ZEXTH, which is a mistake. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix condition. --- gcc/config/riscv/riscv.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc

[Committed] RISC-V: Fix ICE of moving SUBREG of vector mode to DImode scalar register on RV32 system.

This patch fixes following ICE on full coverage testing of RV32. Running target riscv-sim/-march=rv32gc_zve32f/-mabi=ilp32d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic FAIL: gcc.c-torture/compile/930120-1.c -O2 (internal compiler error: in emit_move_insn, at expr.cc:4606) FAIL:

[PATCH FYI] www: new AdaCore-contributed hardening features in gcc 13 and 14

On Nov 30, 2023, Richard Biener wrote: >> >> Here are changes.html entries for this and for the other newly-added >> >> features: >> >> > LGTM. (sorry, I should be following up two messages upthread, but I don't seem to have saved that one) I've finally put in the www changes. Mention

[PATCH] RISC-V: Fix calculation of max live vregs

For the stmt _1 = _2 + _3, assume that _2 or _3 not used after this stmt. _1 can use same register with _2 or _3 if without early clobber. Two registers are needed, but current calculation is three. This patch preserves point 0 for bb entry and excludes its def when calculates live regs of

Re: Re: [PATCH v4 2/3] RISC-V: Add crypto machine descriptions

>> The description in the spec is"Each bit of Op1 is inverted and logically >> ANDed with the corresponding bits in vs2", >> so I think the "and" should be placed outside. Ah. Yes. juzhe.zh...@rivai.ai From: Feng Wang Date: 2023-12-20 16:09 To: juzhe.zh...@rivai.ai; gcc-patches CC:

Re: Re: [PATCH v4 2/3] RISC-V: Add crypto machine descriptions

2023-12-20 15:12 juzhe.zhong wrote: >+   (and:VI >+ (match_operand:VI 3 "register_operand" "vr, vr, vr, vr") >+ (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr"))) >Swap the order: > >(not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr")

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