Re: RISC-V sign extension query

Vineet, Your understanding of the ABI is correct; both int and unsigned int arguments must already be sign-extended. The sext.w is semantically unnecessary; the bltu could correctly reference a1 instead of a6. Good luck eliminating it! Andrew On Mon, Sep 18, 2023 at 12:45 PM Vineet Gupta

Re: RISC-V: Replace not + bitwise_imm with li + bitwise_not

Note this is a size-speed tradeoff, as the Zcb extension has a 16-bit-wide C.NOT instruction. Might want to suppress this optimization when Zcb is present and the function is being optimized for size. On Mon, Sep 11, 2023 at 9:52 AM Jivan Hakobyan via Gcc-patches wrote: > > In the case when we

Re: [RFC PATCH 0/2] RISC-V: __builtin_riscv_pause for all environment

On Sun, Aug 13, 2023 at 12:53 PM Philipp Tomsich wrote: > > On Sat, 12 Aug 2023 at 01:31, Jeff Law via Gcc-patches > wrote: > > > > > > > > On 8/9/23 16:39, Tsukasa OI wrote: > > > On 2023/08/10 5:05, Jeff Law wrote: > > > > >> I'd tend to think we do not want to expose the intrinsic unless the

Re: [PATCH] RISC-V: improve codegen for repeating large constants [3]

On Sat, Jul 1, 2023 at 7:04 AM Jeff Law wrote: > > > > On 7/1/23 02:00, Andrew Waterman wrote: > > > > > Yeah, that might end up being a false economy for superscalars. > > > > In general, I wouldn't recommend spending too many cleverness beans on > > non-Zba+Zbb implementations. Going forward,

Re: [PATCH] RISC-V: improve codegen for repeating large constants [3]

On Fri, Jun 30, 2023 at 5:36 PM Palmer Dabbelt wrote: > > On Fri, 30 Jun 2023 17:25:54 PDT (-0700), Andrew Waterman wrote: > > On Fri, Jun 30, 2023 at 5:13 PM Vineet Gupta wrote: > >> > >> > >> > >> On 6/30/23 16:50, Andrew Waterman wrote: > >> > I don't believe this is correct; the subtraction

Re: [PATCH] RISC-V: improve codegen for repeating large constants [3]

On Fri, Jun 30, 2023 at 5:13 PM Vineet Gupta wrote: > > > > On 6/30/23 16:50, Andrew Waterman wrote: > > I don't believe this is correct; the subtraction is needed to account > > for the fact that the low part might be negative, resulting in a > > borrow from the high part. See the output for

Re: [PATCH] RISC-V: improve codegen for repeating large constants [3]

I don't believe this is correct; the subtraction is needed to account for the fact that the low part might be negative, resulting in a borrow from the high part. See the output for your test case below: $ cat test.c #include int main() { unsigned long result, tmp; asm ( "li

Re: [PATCH] RISC-V: Synthesize power-of-two constants.

This turns out to be a de-optimization for implementations with any amount of temporal execution (which is most machines with LMUL > 1 and even some machines with LMUL <= 1). Scalar instructions are generally cheaper than multi-cycle-occupancy vector operations, so reducing scalar work by

Re: [RFC] RISC-V: Add proposed Ztso atomic mappings

On Fri, May 5, 2023 at 2:42 PM Hans Boehm wrote: > > I think A.6-tso also needs to change the last line in the table from lr.aqrl > ... sc to lr.aq ... sc.rl, otherwise I think we have problems with a > subsequent A.7-tso generated l.aq . Otherwise I agree. > > I certainly agree that, given the

Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET

On Sat, Apr 29, 2023 at 8:06 AM Jeff Law via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > > > > On 4/28/23 20:55, Li, Pan2 wrote: > > Thanks Jeff for comments. > > > > It makes sense to me. For the EQ operator we should have CONSTM1. > That's not the way I interpret the RVV documentation. Of

Re: [PATCH v1] [RFC] Improve folding for comparisons with zero in tree-ssa-forwprop.

On Fri, Mar 17, 2023 at 6:16 AM Philipp Tomsich wrote: > > On Fri, 17 Mar 2023 at 09:31, Richard Biener > wrote: > > > > On Thu, Mar 16, 2023 at 4:27 PM Manolis Tsamis > > wrote: > > > > > > For this C testcase: > > > > > > void g(); > > > void f(unsigned int *a) > > > { > > > if (++*a ==

Re: RISC-V: Add divmod instruction support

On Sat, Feb 18, 2023 at 1:30 PM Palmer Dabbelt wrote: > > On Sat, 18 Feb 2023 13:06:02 PST (-0800), jeffreya...@gmail.com wrote: > > > > > > On 2/18/23 11:26, Palmer Dabbelt wrote: > >> On Fri, 17 Feb 2023 06:02:40 PST (-0800), gcc-patches@gcc.gnu.org wrote: > >>> Hi all, > >>> If we have

Re: [PATCH] RISC-V: Zihintpause: add __builtin_riscv_pause

I've got a contrary opinion: Since HINTs are guaranteed to execute as no-ops--e.g., this one is just a FENCE instruction, which is already a mandatory part of the base ISA--they don't _need_ to be called out as separate extensions in the toolchain. Although there's nothing fundamentally wrong