I don't have any objection, but the patch is FreeBSD-specific. You
are sending the patch from the FreeBSD organization, but I don't know
the authority structure within the organization. Andreas Tobler is
the FreeBSD maintainer for GCC, but I don't know his current status.
Thanks, David
On
On Tue, Mar 1, 2022 at 12:41 AM HAO CHEN GUI wrote:
>
> Hi,
>This patch enables absolute jump tables on PPC AIX and Linux. For AIX, the
> jump
> table is placed in data section. For Linux, it is placed in RELRO section when
> relocation is needed.
>
>Bootstrapped and tested on AIX,Linux
redundant target clause when modifying any testcase, please).
>
> Okay.
> >
> >> /* { dg-require-effective-target powerpc_p9vector_ok } */
> >> /* { dg-options "-mdejagnu-cpu=power9" } */
> >> +/* { dg-additional-options "-mbig" { target powe
On Tue, Feb 8, 2022 at 12:25 PM Jakub Jelinek wrote:
>
> Hi!
>
> The following testcase ICEs, because
> (const_vector:V4SI [
> (const_int 0 [0]) repeated x3
> (const_int -2147483648 [0x8000])
> ])
> is recognized as valid
On Mon, Feb 7, 2022 at 8:20 AM Jakub Jelinek wrote:
>
> On Fri, Feb 04, 2022 at 12:00:57PM -0500, David Edelsohn via Gcc-patches
> wrote:
> > > The following testcase FAILs when configured with
> > > --with-long-double-format=ieee . Only happens in the -std=c* mode
On Fri, Feb 4, 2022 at 11:58 AM Jakub Jelinek wrote:
>
> Hi!
>
> The following testcase FAILs when configured with
> --with-long-double-format=ieee . Only happens in the -std=c* modes, not the
> GNU modes; while the glibc headers have __asm redirects of
> vsnprintf and __vsnprinf_chk to
On Thu, Feb 3, 2022 at 6:09 PM Martin Sebor wrote:
>
> On 2/3/22 15:56, David Edelsohn wrote:
> > This series of patches has exploded memory usage and I can no longer
> > bootstrap GCC on AIX.
> >
> > As with the Ranger problem exposed by Aldy's patch last September
This series of patches has exploded memory usage and I can no longer
bootstrap GCC on AIX.
As with the Ranger problem exposed by Aldy's patch last September,
something is not freeing memory.
Even on systems where GCC still bootstrap, this excessive memory usage
severely damages GCC compile
On Wed, Jan 26, 2022 at 3:45 PM Jakub Jelinek wrote:
>
> Hi!
>
> r12-4717-g7d37abedf58d66 added immintrin.h and x86gprintrin.h headers
> to rs6000, these headers are on x86 standalone headers that various
> programs include directly rather than including them through
> .
> Unfortunately, for that
This patch broke bootstrap on AIX. It may have broken Darwin. I have
applied the following patch. AIX doesn't need to distinguish between
different Linux libc implementations.
Bootstrapped on powerpc-ibm-aix7.2.3.0
Thanks, David
aix: AIX is not GLIBC.
A recent patch added tests for
On Fri, Jan 21, 2022 at 2:56 PM Michael Meissner wrote:
>
> Ping patch
> https://gcc.gnu.org/pipermail/gcc-patches/2022-January/587924.html
>
> | Date: Fri, 7 Jan 2022 16:05:53 -0500
> | From: Michael Meissner
> | Subject: [PATCH] PR 103763, Fix fold-vec-splat-floatdouble on power10.
> |
On Thu, Jan 20, 2022 at 2:36 AM HAO CHEN GUI wrote:
>
> Hi,
>This patch adds a combine pattern for "CA minus one". As CA only has two
> values (0 or 1), we could convert following pattern
> (sign_extend:DI (plus:SI (reg:SI 98 ca)
> (const_int -1 [0x]
On Wed, Jan 19, 2022 at 2:12 AM HAO CHEN GUI wrote:
>
> Hi,
>This patch adds a combine pattern for "CA minus one". As CA only has two
> values (0 or 1), we could convert following pattern
> (sign_extend:DI (plus:SI (reg:SI 98 ca)
> (const_int -1 [0x]
On Wed, Jan 19, 2022 at 2:12 AM HAO CHEN GUI wrote:
>
> Hi,
>This patch adds a combine pattern for "CA minus one". As CA only has two
> values (0 or 1), we could convert following pattern
> (sign_extend:DI (plus:SI (reg:SI 98 ca)
> (const_int -1 [0x]
This patch introduced new AIX testsuite failures.
PR libstdc++/104101
Thanks, David
On Fri, Jan 14, 2022 at 5:42 AM Kewen.Lin wrote:
>
> on 2022/1/13 下午11:15, David Edelsohn wrote:
> > On Thu, Jan 13, 2022 at 7:40 AM Kewen.Lin wrote:
> >>
> >> Hi David,
> >>
> >> on 2022/1/13 上午11:12, David Edelsohn wrote:
> >>> On Wed
On Thu, Jan 13, 2022 at 7:28 AM Kewen.Lin wrote:
>
> on 2022/1/13 上午11:56, Kewen.Lin via Gcc-patches wrote:
> > on 2022/1/13 上午11:44, David Edelsohn wrote:
> >> On Wed, Jan 12, 2022 at 10:38 PM Kewen.Lin wrote:
> >>>
> >>> Hi David,
> >
On Thu, Jan 13, 2022 at 7:40 AM Kewen.Lin wrote:
>
> Hi David,
>
> on 2022/1/13 上午11:12, David Edelsohn wrote:
> > On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin wrote:
> >>
> >> Hi,
> >>
> >> This patch is to clean up some codes with GET_MODE_
On Wed, Jan 12, 2022 at 10:38 PM Kewen.Lin wrote:
>
> Hi David,
>
> on 2022/1/13 上午11:07, David Edelsohn wrote:
> > On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin wrote:
> >>
> >> Hi,
> >>
> >> This patch is to fix register constraint v wit
On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin wrote:
>
> Hi,
>
> This patch is to clean up some codes with GET_MODE_UNIT_SIZE or
> GET_MODE_NUNITS, which can use known constant instead.
I'll let Segher decide, but often the additional code is useful
self-documentation instead of magic constants. Or
On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin wrote:
>
> Hi,
>
> This patch is to fix register constraint v with
> rs6000_constraints[RS6000_CONSTRAINT_v] instead of ALTIVEC_REGS,
> just like some other existing register constraints with
> RS6000_CONSTRAINT_*.
>
> I happened to see this and hope it's
On Wed, Jan 12, 2022 at 8:40 PM HAO CHEN GUI wrote:
>
> Hi David,
>
> On 12/1/2022 下午 10:44, David Edelsohn wrote:
> > On Wed, Jan 12, 2022 at 7:22 AM HAO CHEN GUI wrote:
> >>
> >> Hi,
> >>This patch enables absolute jump table by default on rs
On Wed, Jan 12, 2022 at 7:22 AM HAO CHEN GUI wrote:
>
> Hi,
>This patch enables absolute jump table by default on rs6000. The relative
> jump tables are used when
>it's explicit set by "rs6000_relative_jumptables",
>or jump tables are placed in text section but global relocation is
The recent patch to support Power IEEE128 causes a bootstrap failure
on AIX and possibly all non-GLIBC systems.
+#if defined(__powerpc64__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ \
+&& defined __GLIBC_PREREQ && __GLIBC_PREREQ (2, 32)
+#define POWER_IEEE128 1
+#endif
__GLIBC_PREREQ is
Suppress exceptions (when specified), by saving, manipulating, and
restoring the FPSCR. Similarly, save, set, and restore the floating-point
rounding mode when required.
No attempt is made to optimize writing the FPSCR (by checking if the new
value would be the same), other than using lighter
On Tue, Jan 11, 2022 at 12:06 PM Bill Schmidt wrote:
>
> Hi Mike,
>
> This looks fine to me. Maintainers?
Okay.
Thanks, David
>
> Thanks,
> Bill
>
> On 1/7/22 6:33 PM, Michael Meissner wrote:
> > Fix pr101384-1.c code generation test.
> >
> > Add support for the compiler using XXSPLTIB
On Tue, Jan 11, 2022 at 2:27 AM Xionghu Luo wrote:
>
> On 2022/1/11 06:55, David Edelsohn wrote:
> >>> +(define_insn_and_split "sldoi_to_mov_"
> > It would be more consistent with the naming convention to use
> > "sldoi_to_mov" without t
On Mon, Jan 10, 2022 at 12:37 AM Xionghu Luo wrote:
>
> Ping, thanks.
>
>
> On 2021/12/13 13:16, Xionghu Luo wrote:
> > Add specialized version to combine two instructions from
> >
> > 9: {r123:CC=cmp(r124:DI&0x6,0);clobber scratch;}
> >REG_DEAD r124:DI
> > 10:
On Wed, Dec 29, 2021 at 4:37 AM Kewen.Lin wrote:
>
> Hi,
>
> Option -mpower10 was made as "WarnRemoved" since commit r11-2318,
> so -mno-power10 doesn't take effect any more. This patch is to
> remove one line useless code which still respects it.
>
> Bootstrapped and regtested on
On Sun, Jan 9, 2022 at 10:16 PM HAO CHEN GUI wrote:
>
> Hi,
>
> Gentle ping this:
> https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587051.html
>
> Thanks
>
> On 17/12/2021 上午 9:55, HAO CHEN GUI wrote:
> > Hi,
> >This patch defines a new split pattern for TI to V1TI move.
On Mon, Jan 10, 2022 at 12:04 AM Xionghu Luo wrote:
>
> Gentle ping, thanks.
>
>
> On 2021/12/29 09:27, Xionghu Luo wrote:
> > 7: r120:V4SI=const_vector
> > 8: r121:V4SI=unspec[r120:V4SI,r120:V4SI,0xc] 260
> >
> > with r121:v4SI = r120:V4SI when r120 is a vector with same element.
> >
> >
On Sat, Jan 8, 2022 at 1:59 PM Michael Meissner wrote:
>
> On Sat, Jan 08, 2022 at 03:18:07PM +0100, Jakub Jelinek wrote:
> > On Sat, Jan 08, 2022 at 03:13:10PM +0100, Thomas Koenig wrote:
> > >
> > > On 08.01.22 15:02, Jakub Jelinek via Fortran wrote:
> > > > Note, as for byteswapping,
On Fri, Jan 7, 2022 at 3:57 PM Paul A. Clarke wrote:
>
> On Fri, Jan 07, 2022 at 02:40:51PM -0500, David Edelsohn via Gcc-patches
> wrote:
> > +#ifdef __LITTLE_ENDIAN__
> > + /* Sum across four integers with two integer results. */
> > + asm ("vsum2sws %0,%1
On Fri, Jan 7, 2022 at 3:35 PM Paul A. Clarke wrote:
>
> On Fri, Jan 07, 2022 at 02:23:14PM -0500, David Edelsohn wrote:
> > > Power10 ISA added `vextract*` instructions which are realized in the
> > > `vec_extractm` instrinsic.
> > >
> > &g
On Fri, Jan 7, 2022 at 3:32 PM Paul A. Clarke wrote:
>
> On Fri, Jan 07, 2022 at 02:15:22PM -0500, David Edelsohn wrote:
> > > Power10 ISA added `xxblendv*` instructions which are realized in the
> > > `vec_blendv` instrinsic.
> > >
> > > Use `vec_ble
+#ifdef __LITTLE_ENDIAN__
+ /* Sum across four integers with two integer results. */
+ asm ("vsum2sws %0,%1,%2" : "=v" (result) : "v" (vsum), "v" (zero));
+ /* Note: vec_sum2s could be used here, but on little-endian, vector
+ shifts are added that are not needed for this use-case.
+ A
> Power10 ISA added `vextract*` instructions which are realized in the
> `vec_extractm` instrinsic.
>
> Use `vec_extractm` for `_mm_movemask_ps`, `_mm_movemask_pd`, and
> `_mm_movemask_epi8` compatibility intrinsics, when `_ARCH_PWR10`.
>
> 2021-10-21 Paul A. Clarke
>
> gcc
> *
> Power10 ISA added `xxblendv*` instructions which are realized in the
> `vec_blendv` instrinsic.
>
> Use `vec_blendv` for `_mm_blendv_epi8`, `_mm_blendv_ps`, and
> `_mm_blendv_pd` compatibility intrinsics, when `_ARCH_PWR10`.
>
> Also, copy a test from i386 for testing `_mm_blendv_ps`.
> This
Hi, Jeff
Is the revised patch from Clement okay?
Thanks, David
On Tue, Aug 24, 2021 at 3:59 AM CHIGOT, CLEMENT wrote:
>
> >>> So my worry here is this is really a host property -- ie, this is
> >>> behavior of where GCC runs, not the target for which GCC is generating
> >>> code.
> >>>
> >>>
On Mon, Dec 20, 2021 at 6:55 PM Segher Boessenkool
wrote:
>
> On Mon, Dec 20, 2021 at 11:45:45AM -0500, David Edelsohn wrote:
> > On Mon, Dec 20, 2021 at 3:24 AM Xionghu Luo wrote:
> > > These four UNSPECS seems could be replaced with native RTL, and why
> >
On Mon, Dec 20, 2021 at 3:24 AM Xionghu Luo wrote:
>
> These four UNSPECS seems could be replaced with native RTL, and why
> "(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))"
> in the RTL pattern, per ISA of VSCR bit 127(VECTOR Saturation, SAT):
>
> This bit is sticky;
On Mon, Dec 20, 2021 at 12:56 AM HAO CHEN GUI wrote:
>
> Hi,
> I modified the patch according to David and Segher's advice.
>
> This patch defines a pattern for mffscrni. If the RN is a constant, it can
> call
> gen_rs6000_mffscrni directly. The "rs6000-builtin-new.def" defines prototype
>
On Thu, Dec 16, 2021 at 9:43 PM HAO CHEN GUI wrote:
>
> Hi,
>This patch defines a pattern for mffscrni. If the RN is a constant, it can
> call
> gen_rs6000_mffscrni directly. The "rs6000-builtin-new.def" defines prototype
> for builtin arguments.
> The pattern "rs6000_set_fpscr_rn" is then
Siddhesh,
This patch series seems to have caused testsuite regressions for
memcpy-chk, etc. in 32 bit mode (i386, x86-64 -m32 and -mx32, AIX 32
bit).
I have opened PR 103759.
Thanks, David
On Mon, Dec 6, 2021 at 3:49 PM Bill Schmidt wrote:
>
> Hi!
>
> While we had two sets of built-in infrastructure at once, I added _x as a
> suffix to two arrays to disambiguate the old and new versions. Time to fix
> that also.
>
> Bootstrapped and tested on powerpc64le-linux-gnu with no
On Mon, Dec 6, 2021 at 3:49 PM Bill Schmidt wrote:
>
> Hi!
>
> While we had two sets of built-in functionality at the same time, I put "new"
> in the names of quite a few functions. Time to undo that.
>
> Bootstrapped and tested on powerpc64le-linux-gnu with no regressions. Is this
> okay for
On Mon, Dec 6, 2021 at 3:49 PM Bill Schmidt wrote:
>
> Hi!
>
> The old rs6000-builtin.def file is no longer needed. Remove it and the code
> that depends on it.
>
> Bootstrapped and tested on powerpc64le-linux-gnu with no regressions. Is this
> okay for trunk?
>
> Thanks!
> Bill
>
> 2021-12-02
On Mon, Dec 6, 2021 at 3:49 PM Bill Schmidt wrote:
>
> Hi!
>
> This patch just renames a file and updates the build machinery accordingly.
>
> Bootstrapped and tested on powerpc64le-linux-gnu with no regressions. Is this
> okay for trunk?
>
> Thanks!
> Bill
>
> 2021-12-02 Bill Schmidt
>
>
On Mon, Dec 6, 2021 at 3:49 PM Bill Schmidt wrote:
>
> Hi!
>
> This patch just removes the huge altivec_overloaded_builtins array.
>
> Bootstrapped and tested on powerpc64le-linux-gnu with no regressions. Is this
> okay for trunk?
>
> Thanks!
> Bill
>
> 2021-12-02 Bill Schmidt
>
> gcc/
>
On Fri, Nov 5, 2021 at 3:38 PM will schmidt wrote:
>
> On Fri, 2021-11-05 at 00:11 -0400, Michael Meissner wrote:
> > Generate XXSPLTIDP for scalars on power10.
> >
> > This patch implements XXSPLTIDP support for SF, and DF scalar constants.
> > The previous patch added support for vector
On Fri, Nov 5, 2021 at 3:24 PM will schmidt wrote:
>
> On Fri, 2021-11-05 at 00:10 -0400, Michael Meissner wrote:
> > Generate XXSPLTIDP for vectors on power10.
> >
> > This patch implements XXSPLTIDP support for all vector constants. The
> > XXSPLTIDP instruction is given a 32-bit immediate
On Fri, Nov 5, 2021 at 2:50 PM will schmidt wrote:
>
> On Fri, 2021-11-05 at 00:09 -0400, Michael Meissner wrote:
> > Generate XXSPLTIW on power10.
> >
>
> Hi,
>
>
> > This patch adds support to automatically generate the ISA 3.1 XXSPLTIW
> > instruction for V8HImode, V4SImode, and V4SFmode
On Fri, Nov 5, 2021 at 2:13 PM Michael Meissner wrote:
>
> On Fri, Nov 05, 2021 at 12:01:43PM -0500, will schmidt wrote:
> > On Fri, 2021-11-05 at 00:04 -0400, Michael Meissner wrote:
> > > Add new constant data structure.
> > >
> > > This patch provides the data structure and function to convert
On Fri, Nov 5, 2021 at 2:01 PM Michael Meissner wrote:
>
> On Fri, Nov 05, 2021 at 12:52:51PM -0500, will schmidt wrote:
> > > diff --git a/gcc/config/rs6000/predicates.md
> > > b/gcc/config/rs6000/predicates.md
> > > index 956e42bc514..e0d1c718e9f 100644
> > > ---
Hi, Roger!
Thanks very much for investigating this issue and developing a patch
to leverage this feature of the PowerPC architecture.
2021-12-03 Roger Sayle
gcc/ChangeLog
PR target/43892
* config/rs6000/rs6000.md (*add3_carry_in_0_2): New
define_insn to recognize
On Sun, Dec 12, 2021 at 10:00 PM HAO CHEN GUI wrote:
>
> Hi,
>This patch defines a new split pattern for TI to V1TI move. The pattern
> concatenates two subreg:DI of
> a TI to a V2DI, then move the V2DI to V1TI. With the pattern, the subreg pass
> can do register split for
> TI when there
On Mon, Dec 13, 2021 at 10:48 AM Bill Schmidt wrote:
>
> Hi!
>
> PR103624 observes that we get segfaults for the 64-bit darn builtins when
> compiled
> on a 32-bit architecture. The old built-in infrastructure requires
> TARGET_64BIT, and
> this was missed in the new support. Moving these two
On Mon, Dec 13, 2021 at 11:02 AM Bill Schmidt wrote:
>
> Hi!
>
> PR103625 observes that we ICE when doing vector compares on doublewords.
> The original built-in function support requires Power8 vector support for
> these, but this was missed in the new built-in support. Moving these
> functions
On Tue, Nov 30, 2021 at 3:46 AM HAO CHEN GUI wrote:
>
> Hi,
>
> This patch modifies the combine pattern with a helper -
> change_pseudo_and_mask when recog fails. The helper converts a single pseudo
> to the pseudo and with a mask if the outer operator is IOR/XOR/PLUS and the
> inner
On Wed, Sep 15, 2021 at 4:12 AM CHIGOT, CLEMENT wrote:
>
> As gcc on 64bit for AIX is built with "MULTILIB_MATCHES= .=maix32",
> "-print-multi-directory" and similar flags aren't returning the
> correct directory when used with -maix32: "." is returned instead
> of "ppc32".
> Libgcc installation
On Mon, Nov 22, 2021 at 10:58 AM Bill Schmidt wrote:
>
> Hi!
>
> On 11/19/21 8:49 AM, Michael Meissner wrote:
> > The next set of 3 patches add zero cycle move support to the Power10. Zero
> > cycle moves are where the move to LR/CTR/TAR register that is adjacent to
> > the
> > jump to
On Wed, Nov 17, 2021 at 3:28 AM HAO CHEN GUI wrote:
>
> Hi,
>
> The patch optimized for vec_reve builtin on rs6000. For V2DI and V2DF, it
> is implemented by xxswapd on all targets. For V16QI, V8HI, V4SI and V4SF, it
> is implemented by quadword byte reverse plus halfword/word byte reverse
On Thu, Nov 18, 2021 at 2:07 PM Jan Hubicka wrote:
>
> > --- a/gcc/config/rs6000/predicates.md
> > +++ b/gcc/config/rs6000/predicates.md
> > @@ -1086,7 +1086,9 @@ (define_predicate "current_file_function_operand"
> > (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
> >
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1086,7 +1086,9 @@ (define_predicate "current_file_function_operand"
(match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
&& (SYMBOL_REF_LOCAL_P (op)
||
For -mcpu=native, GCC needs to detect the processor. This
patch adds the processor value for Power10.
Suggested by Kevin Alder.
* config/rs6000/driver-rs6000.c (detect_processor_aix): Add
power10.
Bootstrapped on powerpc-ibm-aix7.2.3.0
diff
On Wed, Nov 17, 2021 at 3:02 PM Segher Boessenkool
wrote:
>
> > It's not a strong objection, since specifying "-mno-vsx" should be
> > uncommon. (Right?) And, specifying "-mcpu=power8 -mvsx" is harmless.
>
> Maybe the warning could say "requires -mcpu=power8 (and -mvsx)"? Is
> that clearer, to
On Tue, Nov 9, 2021 at 4:40 PM Bill Schmidt wrote:
>
> Hi! Over the last month or so, Haochen made a couple of changes to the
> builtins
> support that need to be reflected into the new builtin support:
>
> 14e355df Disable gimple folding for vector min/max without fast-math
> 91419baf
powerpc: Fix vsx_splat_v4si in 32 bit mode
Tamar's recent patch to teach CSE to perform vector extract exercises
VSX splat more frequently, which exposed a constraint error for the
vsx_splat patterns. The pattern could be created for Power9, but
the "we constraint only
I just noticed that Iain adjusted the tsvc.h for Darwin in the same
way that I need to adjust it for AIX. Are we trying to keep the
testcase directory pristine and in sync with its upstream source or
can we fix it locally?
Thanks, David
On Fri, Nov 5, 2021 at 8:24 PM David Edelsohn wrote
Hi, Martin
These testcases rely on memalign in tsvc.h. memalign is provided in
Linux and Solaris, but is not part of Posix, and it is not available
in AIX. Posix defines posix_memalign, which also is available in AIX.
Should the tsvc.h use posix_memalign? Always? Only when memalign is
not
On Thu, Nov 4, 2021 at 8:50 PM Xionghu Luo wrote:
> [PATCH] rs6000: Fix incorrect fusion constraint [PR102991]
>
> gcc/ChangeLog:
>
> * config/rs6000/fusion.md: Regenerate.
> * config/rs6000/genfusion.pl: Fix incorrect clobber constraint.
Okay.
Thanks, David
On Wed, Nov 3, 2021 at 9:46 PM Xionghu Luo wrote:
>
> On 2021/11/3 23:13, David Edelsohn wrote:
> > Did you manually change fusion.md or did you regenerate it after
> > fixing genfusion.pl?
> >
> > If you regenerated it, the ChangeLog entry should be "Rege
Did you manually change fusion.md or did you regenerate it after
fixing genfusion.pl?
If you regenerated it, the ChangeLog entry should be "Regenerated" and
the "Fix incorrect clobber constraint." should refer to the
genfusion.pl change.
I want to ensure that genfusion.pl generates the correct
On Mon, Nov 1, 2021 at 10:40 PM HAO CHEN GUI wrote:
>
> David,
>
> My patch file was broken. I am sorry for it. Here is the correct one.
> Thanks a lot.
>
> ChangeLog
>
> 2021-11-01 Haochen Gui
>
> gcc/
> * config/rs6000/rs6000-call.c (rs6000_gimple_fold_builtin): Disable
>
Hi, Hao
Neither the inlined patch nor the attached patch seem to contain the
change to rs6000-call.c. I only see the new testcases.
Please resend the complete patch.
Thanks David
On Mon, Nov 1, 2021 at 2:48 AM HAO CHEN GUI wrote:
>
> Hi,
>
> This patch disables gimple folding for
On Thu, Oct 28, 2021 at 1:39 AM Xionghu Luo wrote:
>
> On 2021/10/27 21:24, David Edelsohn wrote:
> > On Sun, Oct 24, 2021 at 10:51 PM Xionghu Luo wrote:
> >>
> >> If the second operand of __builtin_shuffle is const vector 0, and with
> >> specific mask, i
On Wed, Oct 27, 2021 at 9:30 PM Kewen.Lin wrote:
>
> Hi David,
>
> Thanks for the review!
>
> on 2021/10/27 下午9:12, David Edelsohn wrote:
> > On Sun, Oct 24, 2021 at 11:04 PM Kewen.Lin wrote:
> >>
> >> Hi,
> >>
> >> As PR1
On Sun, Oct 24, 2021 at 10:51 PM Xionghu Luo wrote:
>
> If the second operand of __builtin_shuffle is const vector 0, and with
> specific mask, it can be optimized to vspltisw+xxpermdi instead of lxv.
>
> gcc/ChangeLog:
>
> * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Add
>
This patch series is okay.
Thanks, David
On Thu, Oct 21, 2021 at 11:25 PM Xionghu Luo wrote:
>
> Ping^3, thanks.
>
> https://gcc.gnu.org/pipermail/gcc-patches/2021-September/579637.html
>
>
> On 2021/10/15 14:28, Xionghu Luo via Gcc-patches wrote:
> > Ping^2, thanks.
> >
> >
On Sun, Oct 24, 2021 at 11:04 PM Kewen.Lin wrote:
>
> Hi,
>
> As PR102767 shows, the commit r12-3482 exposed one ICE in function
> rs6000_builtin_vectorization_cost. We claims V1TI supports movmisalign
> on rs6000 (See define_expand "movmisalign"), so it return true in
>
On Thu, Oct 21, 2021 at 8:39 AM CHIGOT, CLEMENT wrote:
>
> Hi David,
>
> The problem is that cdtors is created by the linker only when the -bcdtors
> flag is provided. Thus, if we add "extern void (* _cdtors[]) (void);" to
> the "crtcxa.c", we can't use it without using the new constructor types.
Clement,
+ /* Use __C_runtime_pstartup to run ctors and register dtors.
+ This whole part should normally be in libgcc but as
+ AIX cdtors format is currently not the default, managed
+ that in collect2. */
Why are you emitting the special startup function call in collect2.c
instead of
on, Oct 18, 2021 at 11:09 AM H.J. Lu wrote:
>
> On Mon, Oct 18, 2021 at 8:04 AM David Edelsohn wrote:
> >
> > Hi, H.J.
> >
> > My colleague responded that GCC Go builds and works on AIX, but it
> > currently requires a special, custom version of GNU objcopy t
On Tue, Oct 12, 2021 at 9:50 PM Xionghu Luo wrote:
>
> Resend this patch. Previous discussion is:
>
> https://gcc.gnu.org/pipermail/gcc-patches/2021-June/572330.html
>
> vmrghb only accepts permute index {0, 16, 1, 17, 2, 18, 3, 19, 4, 20,
> 5, 21, 6, 22, 7, 23} no matter for BE or LE in ISA,
David Edelsohn wrote:
> >
> > On Sat, Oct 16, 2021 at 1:13 PM H.J. Lu wrote:
> > >
> > > On Sat, Oct 16, 2021 at 10:04 AM David Edelsohn wrote:
> > > >
> > > > On Sat, Oct 16, 2021 at 7:48 AM H.J. Lu wrote:
> > > > >
On Sat, Oct 16, 2021 at 3:59 PM H.J. Lu wrote:
>
> On Sat, Oct 16, 2021 at 12:53 PM David Edelsohn wrote:
> >
> > On Sat, Oct 16, 2021 at 1:13 PM H.J. Lu wrote:
> > >
> > > On Sat, Oct 16, 2021 at 10:04 AM David Edelsohn wrote:
> > > >
> &
On Sat, Oct 16, 2021 at 1:13 PM H.J. Lu wrote:
>
> On Sat, Oct 16, 2021 at 10:04 AM David Edelsohn wrote:
> >
> > On Sat, Oct 16, 2021 at 7:48 AM H.J. Lu wrote:
> > >
> > > On Fri, Oct 15, 2021 at 5:22 PM David Edelsohn wrote:
> > > >
> &
On Sat, Oct 16, 2021 at 7:48 AM H.J. Lu wrote:
>
> On Fri, Oct 15, 2021 at 5:22 PM David Edelsohn wrote:
> >
> > On Fri, Oct 15, 2021 at 8:06 PM H.J. Lu wrote:
> > >
> > > On Wed, Oct 13, 2021 at 6:42 AM H.J. Lu wrote:
> > > >
> &
On Fri, Oct 15, 2021 at 8:06 PM H.J. Lu wrote:
>
> On Wed, Oct 13, 2021 at 6:42 AM H.J. Lu wrote:
> >
> > On Wed, Oct 13, 2021 at 6:03 AM Richard Biener
> > wrote:
> > >
> > > On Wed, Oct 13, 2021 at 2:56 PM H.J. Lu wrote:
> > > >
> > > > On Wed, Oct 13, 2021 at 5:45 AM Richard Biener
> > > >
On Thu, Oct 14, 2021 at 2:17 AM HAO CHEN GUI wrote:
>
> Hi,
>
>The patch optimizes the code generation for vec_xl_sext builtin. Now all
> the sign extensions are done on VSX registers directly.
>
>Bootstrapped and tested on powerpc64le-linux with no regressions. Is this
> okay for
il, I'm wondering if we don't want to always keep both
> csects. If .data is kept, then .text is and if .text is kept, then .data is.
> Or always keeping .data would have too much side effects ?
>
> Thanks,
> Clément
>
>
> From: David Edelsohn
On Thu, Oct 14, 2021 at 9:00 AM Richard Sandiford
wrote:
>
> rs6000_density_test has an early exit test between a call
> to get_loop_body and the corresponding free. This would
> lead to a memory leak if the early exit is taken.
>
> Tested on powerpc64le-linux-gnu. It's obvious that moving the
The reference to __tls_get_addr is in the data section. And the code
just above creates a symbol in the text section referenced from the
data section to ensure the text section is retained. So this change
doesn't make sense. You're essentially saying that the data section
is not used, which
>> gcc/
>> * config/rs6000/rs6000-call.c (altivec_expand_lxvr_builtin):
>> Modify the expansion for sign extension. All extentions are done
>> within VSX resgisters.
>
> Two typos here: extentions => extensions, resgisters => registers.
This is okay with Bill's comments
> The patch punishes reload of alternative pair of "d, Z" for
> movsi_internal1. The reload occurs if 'Z' doesn't match and generates an
> additional insn. So the memory reload should be punished.
>
> Bootstrapped and tested on powerpc64le-linux with no regressions. Is this
> okay for
2021-08-25 Haochen Gui
gcc/
* config/rs6000/rs6000-call.c (rs6000_gimple_fold_builtin):
Modify the VSX_BUILTIN_XVMINDP, ALTIVEC_BUILTIN_VMINFP,
VSX_BUILTIN_XVMAXDP, ALTIVEC_BUILTIN_VMAXFP expansions.
Please write something more than "modify". The ChangeLog should be
more like
Hi, Xionghu
What's the status of the \M and \m testcase beautification requested
by Segher? Did you send an updated patch? Your messages ping the
version prior to Segher's additional comments.
It seems that the changes to the patterns are complete, but there are
remaining questions about the
On Fri, Sep 24, 2021 at 11:20 AM Bill Schmidt wrote:
>
> Hi!
>
> This fixes a bug reported in
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101985.
>
> The vec_cpsgn built-in function API differs in argument order from the
> copysign3 convention. Currently that pattern is incorrectly used to
>
This needs an additional adjustment. The encoding decoration needs to
be applied if the decl isn't an alias. That means both a null summary
*OR* the decl is not explicitly an alias.
I'm proposing the following:
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index
ibffi itself...
> This patch is specific to gcc because the multilib part is specific
> to gcc.
> I'll ask the community but the patch cannot be merged inside
> libffi.
>
> Thanks,
> Clément
> ____
> From: David Edelsohn
> Sent: Wednesday, Septem
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