The e500v2 (SPE) hardware is such that if the address of vector (double world
load / stores) are not double world aligned the instruction will trap.
So this alignment is not optional.
Edmar
On Fri, Jun 7, 2013 at 3:43 PM, Richard Henderson wrote:
> On 06/07/2013 12:25 PM, Jakub Jelinek wrote:
Alan,
The first hunk will match powerpc64 as well.
Edmar
On Thu, May 9, 2013 at 2:27 AM, Alan Modra wrote:
> Another tweak for little-endian powerpc. Committed revision 198734.
>
> * configure.ac (HAVE_AS_TLS): Enable tests for powerpcle and
> powerpc64le.
> * configure:
