On Thu, May 13, 2021 at 7:52 PM Richard Sandiford
wrote:
>
> Jakub Jelinek writes:
> > On Thu, May 13, 2021 at 12:32:26PM +0100, Richard Sandiford wrote:
> >> Jakub Jelinek writes:
> >> > On Thu, May 13, 2021 at 11:43:19AM +0200, Uros Bizjak wrote:
> >> >> > > Bootstrapped and regtested on
Hi:
When __builtin_ia32_vzeroupper is called explicitly, the corresponding
vzeroupper pattern does not carry any CLOBBERS or SETs before LRA,
which leads to incorrect optimization in pass_reload.
In order to solve this problem, this patch introduces a pre_reload
splitter which adds CLOBBERS to
Hi:
When arg0 is same as arg1 in __builtin_ia32_pcmpgtw,
gimple_build (, GT_EXPR, cmp_type, arg0, arg1) will simplify the
comparison to vector constant 0, no stmts is generated, which causes
ICE in gsi_insert_before (gsi, stmts, GSI_SAME_STMT). So don't insert
stmts when it's NULL.
There's a typo in the testcase, I've committed the patch as an obvious fix.
Fix typo in testcase.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx-pr94680.c: Fix typo in testcase.
diff --git a/gcc/testsuite/gcc.target/i386/avx-pr94680.c
On Wed, May 12, 2021 at 10:19 PM Jakub Jelinek wrote:
>
> On Sun, Apr 25, 2021 at 02:57:08PM +0800, Hongtao Liu via Gcc-patches wrote:
> > gcc/ChangeLog:
> >
> > PR target/94680
> > * config/i386/sse.md (ssedoublevecmode): Add attribute for
&g
On Wed, May 12, 2021 at 8:38 PM Uros Bizjak wrote:
>
> On Wed, May 12, 2021 at 1:42 PM Hongtao Liu wrote:
> >
> > On Wed, May 12, 2021 at 4:36 PM Uros Bizjak wrote:
> > >
> > > On Tue, Apr 27, 2021 at 1:05 PM Hongtao Liu via Gcc-patches
> > > wrot
On Wed, May 12, 2021 at 4:36 PM Uros Bizjak wrote:
>
> On Tue, Apr 27, 2021 at 1:05 PM Hongtao Liu via Gcc-patches
> wrote:
> >
> > Hi:
> > As described in the subject line, this patch is about to do the
> > below transformation.
> >
> >
ping.
On Sun, Apr 25, 2021 at 2:57 PM Hongtao Liu wrote:
>
> On Fri, Apr 23, 2021 at 5:13 PM Jakub Jelinek wrote:
> >
> > On Fri, Apr 23, 2021 at 12:53:58PM +0800, Hongtao Liu via Gcc-patches wrote:
> > > + if (!CONST_INT_P (er))
> > > + re
ping
On Tue, Apr 27, 2021 at 5:58 PM Hongtao Liu wrote:
>
> Hi:
> As described in the subject line, this patch is about to do the
> below transformation.
>
> - vpcmpeqd%ymm3, %ymm3, %ymm3
> - vpandn %ymm3, %ymm2, %ymm2
> - vpblendvb %y
ping
On Fri, Apr 30, 2021 at 12:42 PM Hongtao Liu wrote:
>
> Hi:
> This patch is to fix ice which was introduced by my
> r11-5696-g35c4c67e6c534ef3d6ba7a7752ab7e0fbc91755b.
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
> Ok for trunk and backport to GCC11?
&
ping
On Fri, Apr 30, 2021 at 12:49 PM Hongtao Liu wrote:
>
> Hi:
> For v{,p}expand* When mask is 0, -1, or has all all one bits in its
> lower part, it can be optimized to simple mov or mask mov.
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,} and
> x86_64-lin
Hi:
For v{,p}expand* When mask is 0, -1, or has all all one bits in its
lower part, it can be optimized to simple mov or mask mov.
Bootstrapped and regtested on x86_64-linux-gnu{-m32,} and
x86_64-linux-gnu{m32\ -march=cascadelake,-m64\ -march=cascadelake},
gcc/ChangeLog:
*
Hi:
This patch is to fix ice which was introduced by my
r11-5696-g35c4c67e6c534ef3d6ba7a7752ab7e0fbc91755b.
Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
Ok for trunk and backport to GCC11?
gcc/ChangeLog
PR target/100310
* config/i386/i386-expand.c
On Tue, Apr 27, 2021 at 9:28 AM Hongtao Liu wrote:
>
> On Mon, Apr 26, 2021 at 8:35 PM Uros Bizjak via Gcc-patches
> wrote:
> >
> > On Sat, Apr 24, 2021 at 3:43 PM Cui, Lili wrote:
> > >
> > > Hi Uros,
> > >
> > > Th
Hi:
As described in the subject line, this patch is about to do the
below transformation.
- vpcmpeqd%ymm3, %ymm3, %ymm3
- vpandn %ymm3, %ymm2, %ymm2
- vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+ vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
Bootstrapped and
On Mon, Apr 26, 2021 at 8:35 PM Uros Bizjak via Gcc-patches
wrote:
>
> On Sat, Apr 24, 2021 at 3:43 PM Cui, Lili wrote:
> >
> > Hi Uros,
> >
> > This patch is to synchronize Rocket Lake's processor_names and
> > processor_cost_table with processor_type.
> >
> > Bootstrap is ok, and no
On Fri, Apr 23, 2021 at 5:13 PM Jakub Jelinek wrote:
>
> On Fri, Apr 23, 2021 at 12:53:58PM +0800, Hongtao Liu via Gcc-patches wrote:
> > + if (!CONST_INT_P (er))
> > + return 0;
> > + ei = INTVAL (er);
> > + if (i < nelt2 && ei !
On Wed, Dec 2, 2020 at 9:57 AM Hongtao Liu wrote:
>
> On Wed, Dec 2, 2020 at 8:28 AM Jeff Law wrote:
> >
> >
> >
> > On 11/30/20 10:17 PM, Hongtao Liu via Gcc-patches wrote:
> > > Hi:
> > > There're many pairs of define_insn/define_expand that
On Fri, Apr 23, 2021 at 3:18 PM Uros Bizjak wrote:
>
> On Fri, Apr 23, 2021 at 9:15 AM Hongtao Liu wrote:
> >
> > On Fri, Apr 23, 2021 at 2:50 PM Uros Bizjak wrote:
> > >
> > > On Fri, Apr 23, 2021 at 8:36 AM Hongtao Liu wrote:
> > > >
On Fri, Apr 23, 2021 at 2:50 PM Uros Bizjak wrote:
>
> On Fri, Apr 23, 2021 at 8:36 AM Hongtao Liu wrote:
> >
> > Hi:
> > The patch is a follow-up to
> > https://gcc.gnu.org/pipermail/gcc-patches/2021-January/564320.html.
> > Bootstrapped and regtested
Hi:
The patch is a follow-up to
https://gcc.gnu.org/pipermail/gcc-patches/2021-January/564320.html.
Bootstrapped and regtested on x86-64_iinux-gnu{-m32,}.
Ok for trunk?
gcc/ChangeLog:
PR target/98911
* config/i386/i386-builtin.def (BDESC): Change the icode of
the
Hi:
If the second operand of __builtin_shuffle is const vector 0, and with
specific mask, it can be optimized to movq/vmovps.
.i.e.
foo128:
- vxorps %xmm1, %xmm1, %xmm1
- vmovlhps%xmm1, %xmm0, %xmm0
+ vmovq %xmm0, %xmm0
foo256:
- vxorps %xmm1, %xmm1, %xmm1
Hi:
Bootstrapped and regtested on x86-64_iinux-gnu{-m32,}.
Ok for trunk?
gcc/ChangeLog:
PR target/100093
* config/i386/i386-options.c (ix86_option_override_internal):
Clear MASK_AVX256_SPLIT_UNALIGNED_LOAD/STORE in x_target_flags
when
Hi:
This patch is about to add a pre-reload splitter to transform
vpcmpeqd with a zero operand to vptestnmd, which could save a vpxor
instruction.
.i.e
- vpxor %xmm1, %xmm1, %xmm1
- vpcmpd $0, %zmm1, %zmm0, %k0
+ vptestnmd %zmm0, %zmm0, %k0
vpmovm2d zmm0, k0
On Mon, Apr 12, 2021 at 6:20 PM Cui, Lili via Gcc-patches
wrote:
>
>
> Updated wwwdocs for Rocketlake [GCC11], thanks.
>
> [PATCH] Mention Rocketlake
> ---
> htdocs/gcc-11/changes.html | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/htdocs/gcc-11/changes.html
On Tue, Apr 13, 2021 at 6:38 PM Uros Bizjak wrote:
>
> On Tue, Apr 13, 2021 at 12:18 PM Hongtao Liu wrote:
> >
> > Hi:
> > As described in PR, we introduced tigerlake string in driver-i386.c
> > by r9-8652 w/o support -march/tune=tigerlake which causes an er
From-SVN: r274693
--
BR,
Hongtao
From 89a130f2e626d9e7d92ec8d51956a4ae0d10d277 Mon Sep 17 00:00:00 2001
From: Hongtao Liu
Date: Tue, 20 Aug 2019 07:06:03 +
Subject: [PATCH] backport TIGERLAKE part to GCC9.
2019-08-20 Lili Cui
gcc/
* common/config/i386/i386-common.c
(processor_n
On Mon, Apr 12, 2021 at 3:20 PM Uros Bizjak via Gcc-patches
wrote:
>
> On Mon, Apr 12, 2021 at 5:13 AM Cui, Lili wrote:
> >
> > Hi Uros,
> >
> > This patch is about to change Alder Lake ISA list to GCC add m_ALDERLAKE to
> > m_CORE_AVX2.
> > Alder Lake Intel Hybrid Technology is based on
On Thu, Feb 4, 2021 at 8:00 PM Jakub Jelinek wrote:
>
> On Thu, Feb 04, 2021 at 01:31:52PM +0800, Hongtao Liu via Gcc-patches wrote:
> * gcc.target/i386/avx512vl-pr92686-vpcmp-1.c: This test is
> used to guard code generation of integer mask comparison, but
>
On Thu, Feb 4, 2021 at 4:52 PM Richard Biener
wrote:
>
> On Thu, Feb 4, 2021 at 7:45 AM Uros Bizjak wrote:
> >
> > On Thu, Feb 4, 2021 at 5:28 AM Hongtao Liu wrote:
> >
> > > > > >GCC11 will be the system GCC 2 years from now, and for the
> &
Rebase and update patch:
Fix ICE: Don't generate integer mask comparison for 128/256-bits
vector when op_true/op_false are NULL or constm1_rtx/const0_rtx
[PR98537]
in ix86_expand_sse_cmp/ix86_expand_int_sse_cmp
gcc/ChangeLog:
PR target/98537
*
On Thu, Jan 28, 2021 at 9:18 PM H.J. Lu wrote:
>
> On Thu, Jan 28, 2021 at 1:21 AM Richard Biener via Gcc-patches
> wrote:
> >
> > On Thu, Jan 28, 2021 at 7:32 AM Hongtao Liu via Gcc-patches
> > wrote:
> > >
> > > Hi:
> >
Hi:
GCC11 will be the system GCC 2 years from now, and for the
processors then, they shouldn't even need to split a 256-bit vector
into 2 128-bits vectors.
.i.e. Test SPEC2017 with the below 2 options on Zen3/ICL show
option B is better than Option A.
Option A:
-march=x86-64 -mtune=generic
On Wed, Jan 27, 2021 at 6:38 PM Hongtao Liu wrote:
>
> On Wed, Jan 27, 2021 at 5:03 PM Jakub Jelinek wrote:
> >
> > On Wed, Jan 27, 2021 at 03:22:45PM +0800, Hongtao Liu wrote:
> > > Hi：
> > > As desribed in PR, also remove the relevant and useless expand
On Wed, Jan 27, 2021 at 5:03 PM Jakub Jelinek wrote:
>
> On Wed, Jan 27, 2021 at 03:22:45PM +0800, Hongtao Liu wrote:
> > Hi：
> > As desribed in PR, also remove the relevant and useless expanders
> > and builtins, the user can
> > directly use == and >, wit
Hi：
As desribed in PR, also remove the relevant and useless expanders
and builtins, the user can
directly use == and >, without calling the builtin function.
Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
gcc/ChangeLog:
PR target/98833
* config/i386/i386-builtin.def
On Thu, Jan 14, 2021 at 7:16 PM Hongtao Liu wrote:
>
> ping.
>
> On Thu, Jan 7, 2021 at 1:22 PM Hongtao Liu wrote:
> >
> > On Wed, Jan 6, 2021 at 10:39 PM Jakub Jelinek wrote:
> > >
> > > On Wed, Jan 06, 2021 at 02:49:13PM +0800, Hongtao L
> OK with those changes and the one that HJ asked for.
>
This is the patch I'm checking in, thanks for the review.
> Thanks,
> Richard
--
BR,
Hongtao
From b806e0cece62620e31a4a861208d37616059a212 Mon Sep 17 00:00:00 2001
From: liuhongt
Date: Mon, 18 Jan 2021 16:55:32 +0800
Subject: [PATCH]
On Wed, Jan 20, 2021 at 12:35 PM Hongtao Liu wrote:
>
> On Wed, Jan 20, 2021 at 12:10 AM Richard Sandiford
> wrote:
> >
> > Jakub Jelinek via Gcc-patches writes:
> > > On Tue, Jan 19, 2021 at 12:38:47PM +, Richard Sandiford via
> > > Gcc-patches
On Wed, Jan 20, 2021 at 12:10 AM Richard Sandiford
wrote:
>
> Jakub Jelinek via Gcc-patches writes:
> > On Tue, Jan 19, 2021 at 12:38:47PM +, Richard Sandiford via Gcc-patches
> > wrote:
> >> > actually only the lower 16bits are needed, the original insn is like
> >> >
> >> > .294.r.ira
>
On Mon, Jan 18, 2021 at 7:10 PM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> > On Mon, Jan 18, 2021 at 6:18 PM Richard Sandiford
> > wrote:
> >>
> >> Hongtao Liu via Gcc-patches writes:
> >> > Hi:
> >> > If SRC had been assig
On Mon, Jan 18, 2021 at 6:43 PM Hongtao Liu wrote:
>
> On Mon, Jan 18, 2021 at 6:18 PM Richard Sandiford
> wrote:
> >
> > Hongtao Liu via Gcc-patches writes:
> > > Hi:
> > > If SRC had been assigned a mode narrower than the copy, we can't link
> &
On Mon, Jan 18, 2021 at 6:18 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > Hi:
> > If SRC had been assigned a mode narrower than the copy, we can't link
> > DEST into the chain even they have same
> > hard_regno_nregs(i.e.
Hi:
If SRC had been assigned a mode narrower than the copy, we can't link
DEST into the chain even they have same
hard_regno_nregs(i.e. HImode/SImode in i386 backend).
i.e
kmovw %k0, %edi
vmovd %edi, %xmm2
vpshuflw$0, %xmm2, %xmm0
kmovw %k0, %r8d
ping.
On Thu, Jan 7, 2021 at 1:22 PM Hongtao Liu wrote:
>
> On Wed, Jan 6, 2021 at 10:39 PM Jakub Jelinek wrote:
> >
> > On Wed, Jan 06, 2021 at 02:49:13PM +0800, Hongtao Liu wrote:
> > > ix86_expand_fp_vec_cmp/ix86_expand_int_vec_cmp are used by vec_cmpmn
Hi:
d->flag is always 0 for builtins located in
BDESC_FIRST (comi,COMI,...)
...
BDESC_END (COMI, PCMPESTR)
So the condition can be deleted, so did BUILTIN_DESC_SWAP_OPERANDS.
Regtested and bootstrapped on x86_64-linux-gnu{-m32,}.
gcc/ChangeLog:
PR target/98612
*
On Thu, Jan 7, 2021 at 9:43 PM Uros Bizjak via Gcc-patches
wrote:
>
> 2021-01-07 Uroš Bizjak
>
> No functional changes.
>
> gcc/
> * config/i386/i386.md (insn): Merge from plusminus_insn, shift_insn,
> rotate_insn and optab code attributes.
> Update all uses to merged code
On Tue, Dec 29, 2020 at 3:01 PM sunil.k.pandey via Gcc-regression
wrote:
>
> On Linux/x86_64,
>
> 12ae2bc70846a2be8255eaa41322cd1a5a7b7350 is the first bad commit
> commit 12ae2bc70846a2be8255eaa41322cd1a5a7b7350
> Author: Hongyu Wang
> Date: Fri Dec 25 09:25:39 2020 +0800
>
> Fix standard
On Wed, Jan 6, 2021 at 10:39 PM Jakub Jelinek wrote:
>
> On Wed, Jan 06, 2021 at 02:49:13PM +0800, Hongtao Liu wrote:
> > ix86_expand_fp_vec_cmp/ix86_expand_int_vec_cmp are used by vec_cmpmn
> > for vector comparison to vector mask, but ix86_expand_sse_cmp(which is
>
Hi:
ix86_expand_fp_vec_cmp/ix86_expand_int_vec_cmp are used by vec_cmpmn
for vector comparison to vector mask, but ix86_expand_sse_cmp(which is
called in upper 2 functions.) may return integer mask whenever integer
mask is available, so convert integer mask back to vector mask if
needed.
> >>
> >> Note there's a data dependency between them. insn 7 feeds insn 9. When
> >> there's a data dependency, combiner patterns are usually the better
> >> choice than peepholes. I think you'd be looking to match something
> >> likethis (from the . combine dump):
> >>
Using combiner
On Tue, Jan 5, 2021 at 3:20 PM Uros Bizjak wrote:
>
> On Tue, Jan 5, 2021 at 8:04 AM Uros Bizjak wrote:
> > >
> > > +(define_split
> > > + [(set (match_operand:SI 0 "register_operand")
> > > +(zero_extend:SI
> > > + (not:HI
> > > +(subreg:HI
> > > +
On Mon, Jan 4, 2021 at 4:59 PM Hongtao Liu wrote:
>
> On Mon, Jan 4, 2021 at 4:49 PM Jakub Jelinek wrote:
> >
> > On Mon, Jan 04, 2021 at 01:56:44PM +0800, Hongtao Liu via Gcc-patches wrote:
> > > +(define_insn_and_split "*sse2_pmovskb_zexthisi&quo
On Mon, Jan 4, 2021 at 4:49 PM Jakub Jelinek wrote:
>
> On Mon, Jan 04, 2021 at 01:56:44PM +0800, Hongtao Liu via Gcc-patches wrote:
> > +(define_insn_and_split "*sse2_pmovskb_zexthisi"
> > + [(set (match_operand:SI 0 "register_operand")
> > +
On Mon, Jan 4, 2021 at 3:40 PM Uros Bizjak wrote:
>
> On Mon, Jan 4, 2021 at 6:54 AM Hongtao Liu wrote:
> >
> > Hi:
> > The following patch adds define_insn_and_split to optimize
> >
> >vpmovmskb %xmm0, %eax
> > -
Hi:
The following patch adds define_insn_and_split to optimize
vpmovmskb %xmm0, %eax
- movzwl %ax, %eax
notl%eax
Bootstrapped/regtested on x86_64-linux-gnu {,-m32}.
Ok for trunk?
gcc/ChangeLog
PR target/98461
* config/i386/sse.md
When i'm working on PR98348, i notice there's Typo in define_insn
"*one_cmpl2_1", There are 2 alternatives, so the index couldn't
be 2.
Bootstrap and regress test is ok on x86_64-unknown-linux.
gcc/ChangeLog
* config/i386/i386.md (*one_cmpl2_1): Fix typo, change
alternative
On Tue, Dec 15, 2020 at 7:11 PM Jakub Jelinek wrote:
>
> On Tue, Dec 15, 2020 at 06:10:57PM +0800, Hongtao Liu via Gcc-patches wrote:
> > --- a/gcc/config/i386/i386.c
> > +++ b/gcc/config/i386/i386.c
> > @@ -18187,21 +18187,67 @@ ix86_gimple_fold_builtin (gimple
Hi:
As indicated in PR98167, this patch is a follow-up to [1].
Bootstrapped and regtested on x86_64-linux-gnu.
Ok for trunk?
gcc/
PR target/98167
* config/i386/i386.c (ix86_gimple_fold_builtin): Handle
IX86_BUILTIN_SHUFPD512, IX86_BUILTIN_SHUFPS512,
On Thu, Dec 10, 2020 at 8:52 PM Prathamesh Kulkarni
wrote:
>
> On Wed, 9 Dec 2020 at 15:52, Hongtao Liu wrote:
> >
> > On Wed, Dec 9, 2020 at 5:22 PM Prathamesh Kulkarni via Gcc-patches
> > wrote:
> > >
> > > On Wed, 9 Dec 2020 at 00:29, sunil.k.pand
>
> > On Mon, 7 Dec 2020 at 17:37, Hongtao Liu wrote:
> > >
> > > On Mon, Dec 7, 2020 at 7:11 PM Prathamesh Kulkarni
> > > wrote:
> > > >
> > > > On Mon, 7 Dec 2020 at 16:15, Hongtao Liu wrote:
> > > > >
> > > &g
On Wed, Dec 9, 2020 at 5:22 PM Prathamesh Kulkarni via Gcc-patches
wrote:
>
> On Wed, 9 Dec 2020 at 00:29, sunil.k.pandey wrote:
> >
> > On Linux/x86_64,
> >
> > 3a6e3ad38a17a03ee0139b49a0946e7b9ded1eb1 is the first bad commit
> > commit 3a6e3ad38a17a03ee0139b49a0946e7b9ded1eb1
> > Author:
On Tue, Dec 8, 2020 at 6:23 PM Jakub Jelinek wrote:
>
> On Mon, Nov 30, 2020 at 06:16:06PM +0800, Hongtao Liu via Gcc-patches wrote:
> > Add no strict aliasing to function CALC, since there are
> >
> > "long long tmp = (*(long long *) [i]) ^ (*(long long *)
On Thu, Dec 3, 2020 at 2:22 AM Jakub Jelinek wrote:
>
> On Tue, Dec 01, 2020 at 12:49:03PM +0800, Hongtao Liu via Gcc-patches wrote:
> > +bool neq_p = INTVAL (operands[4]) >> 2;
> > +/* LE: 2, NLT: 5, NLE: 6, LT: 1 */
> > +rtx cmp_predicate = ne
On Thu, Dec 3, 2020 at 3:11 AM Jeff Law wrote:
>
>
>
> On 11/25/20 9:47 PM, Hongtao Liu wrote:
> > On Wed, Nov 25, 2020 at 7:37 PM Jakub Jelinek wrote:
> >> On Wed, Nov 25, 2020 at 07:32:44PM +0800, Hongtao Liu wrote:
> >>> Update patch:
> >>
On Wed, Dec 2, 2020 at 8:28 AM Jeff Law wrote:
>
>
>
> On 11/30/20 10:17 PM, Hongtao Liu via Gcc-patches wrote:
> > Hi:
> > There're many pairs of define_insn/define_expand that are very similar
> > to each other except mode iterator and condition. For these patte
Hi:
There're many pairs of define_insn/define_expand that are very similar
to each other except mode iterator and condition. For these patterns
VI12_AVX512VL are used under condition TARGET_AVX512BW, and
VI48_AVX512VL are used under condition TARGET_AVX512F.
This patch is about to introduce a new
On Mon, Nov 30, 2020 at 9:46 PM Jakub Jelinek wrote:
>
> On Mon, Nov 30, 2020 at 09:11:10PM +0800, Hongtao Liu wrote:
> > +;; PR96906 - optimize vpsubusw compared to 0 into vpcmpleuw or vpcmpnltuw.
> > +(define_split
> > + [(set (match_operand: 0 "register_o
Hi:
This patch is quite similar like what jakub did in
https://gcc.gnu.org/pipermail/gcc-patches/2020-November/560151.html
but for target avx512bw.
.i.e. for -mavx512bw -mavx512vl transform code from
vpsubusw%xmm1, %xmm0, %xmm0
vpxor %xmm1, %xmm1, %xmm1
vpcmpw
Add no strict aliasing to function CALC, since there are
"long long tmp = (*(long long *) [i]) ^ (*(long long *) [i]);"
in function CALC.
modified gcc/testsuite/gcc.target/i386/avx512dq-vandnpd-2.c
@@ -9,6 +9,7 @@
#include "avx512f-mask-type.h"
void
+__attribute__ ((optimize
On Thu, Nov 26, 2020 at 4:11 PM Uros Bizjak wrote:
>
> > Hi:
> > This patch is about to delete dead code in
> > ix86_expand_special_args_builtin.
> >
> > Bootstrap and regression test are ok.
> >
> > gcc/ChangeLog:
> > * config/i386/i386-expand.c
> >
Hi:
This patch is about to delete dead code in ix86_expand_special_args_builtin.
Bootstrap and regression test are ok.
gcc/ChangeLog:
* config/i386/i386-expand.c
(ix86_expand_special_args_builtin): Delete last_arg_constant.
From 948756dae8f67bf766714d9ecc064b4eea9952cd Mon
On Wed, Nov 25, 2020 at 7:37 PM Jakub Jelinek wrote:
>
> On Wed, Nov 25, 2020 at 07:32:44PM +0800, Hongtao Liu wrote:
> > Update patch:
> > 1. ix86_expand_special_args_builtin is used for expanding mask load
> > intrinsics, this function will always convert the co
Thanks for the review.
BTW, the patch is already installed because uros helped to review this
patch in another thread
https://gcc.gnu.org/pipermail/gcc-patches/2020-November/558682.html
On Thu, Nov 26, 2020 at 3:15 AM Jeff Law wrote:
>
>
>
> On 11/11/20 1:03 AM, Hongtao Liu via Gcc-p
On Tue, Nov 24, 2020 at 9:00 PM Jakub Jelinek wrote:
>
> On Tue, Nov 24, 2020 at 10:36:49AM +0800, Hongtao Liu via Gcc-patches wrote:
> > > > * gcc.target/i386/pr97642-2.c: New test.
> > > So in the BZ Jakub asked for the all-ones mask case to be specially
>
On Mon, Nov 23, 2020 at 11:54 PM Richard Biener wrote:
>
> On Mon, 23 Nov 2020, Tamar Christina wrote:
>
> > Hi All,
> >
> > This patch adds support for
> >
> > * Complex Addition with rotation of 90 and 270.
> >
> > Addition with rotation of the second argument around the Argand plane.
> >
Hi:
I'm learning about this patch, and I see one place that might be
slighted improved.
+ poly_int64 size = (top - bot);
+
+ /* Assert the edge of each variable is aligned to the HWASAN tag granule
+size. */
+ gcc_assert (multiple_p (top, HWASAN_TAG_GRANULE_SIZE));
+
On Tue, Nov 24, 2020 at 4:27 AM Jeff Law wrote:
>
>
>
> On 11/4/20 2:19 AM, Hongtao Liu via Gcc-patches wrote:
> > Hi:
> > When programmers explicitly use mask loaded intrinsics, don't
> > transform the instruction to vpblend{b,w,d,q} since If mem_addr points
&g
On Tue, Nov 17, 2020 at 8:05 AM Jeff Law wrote:
>
>
> On 9/2/20 3:34 AM, Hongtao Liu via Gcc-patches wrote:
> > Hi:
> > Add define_peephole2 to eliminate potential redundant conversion
> > from mask to vector.
> > Bootstrap is ok, regression test is ok
On Fri, Nov 13, 2020 at 3:32 AM Gerald Pfeifer wrote:
>
> Per our discussion on the list (plus a grammer improvement in a
> section above).
>
> One question: why are the ISA extension lists not alphabetically
> sorted? Wouldn't that be beneficial for users? Easier to find
> something and also
Got it.
On Fri, Nov 13, 2020 at 3:26 AM Gerald Pfeifer wrote:
>
> On Wed, 11 Nov 2020, Hongtao Liu via Gcc-patches wrote:
> > + New ISA extension support for Intel AVX-VNNI was added to GCC.
>
> More for the future (i.e., no need to change that now): I suggest
> to skip &
On Thu, Nov 12, 2020 at 5:15 PM Hongtao Liu wrote:
>
> On Thu, Nov 12, 2020 at 5:12 PM Hongtao Liu wrote:
> >
> > On Thu, Nov 12, 2020 at 4:21 PM Uros Bizjak wrote:
> > >
> > > On Thu, Nov 12, 2020 at 3:04 AM Hongtao Liu wrote:
> > >
> > >
On Thu, Nov 12, 2020 at 5:12 PM Hongtao Liu wrote:
>
> On Thu, Nov 12, 2020 at 4:21 PM Uros Bizjak wrote:
> >
> > On Thu, Nov 12, 2020 at 3:04 AM Hongtao Liu wrote:
> >
> > > > > gcc/ChangeLog:
> > > > >
> > > > > PR target/97
On Thu, Nov 12, 2020 at 4:21 PM Uros Bizjak wrote:
>
> On Thu, Nov 12, 2020 at 3:04 AM Hongtao Liu wrote:
>
> > > > gcc/ChangeLog:
> > > >
> > > > PR target/97194
> > > > * config/i386/i386-expand.c (ix86_expand_vector_se
On Wed, Nov 11, 2020 at 4:45 PM Uros Bizjak wrote:
>
> > gcc/ChangeLog:
> >
> > PR target/97194
> > * config/i386/i386-expand.c (ix86_expand_vector_set_var): New function.
> > * config/i386/i386-protos.h (ix86_expand_vector_set_var): New Decl.
> > * config/i386/predicates.md (vec_setm_operand):
[GCC-11] Mention Intel AVX-VNNI and add it to ALDERLAKE and SAPPIRERAPIDS,
also add HRESET to ALDERLAKE.
diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html
index d7a3a1f9..fc4c74f4 100644
--- a/htdocs/gcc-11/changes.html
+++ b/htdocs/gcc-11/changes.html
@@ -267,15 +267,20 @@ a
ping ^3
Rebase patch on latest trunk.
On Tue, Oct 27, 2020 at 3:51 PM Hongtao Liu wrote:
>
> ping^1
>
> On Tue, Oct 20, 2020 at 3:36 PM Richard Biener
> wrote:
> >
> > On Tue, Oct 20, 2020 at 4:35 AM Hongtao Liu wrote:
> > >
> > > On Mon, Oct 19
On Tue, Nov 10, 2020 at 4:17 PM Hongtao Liu wrote:
>
> On Tue, Nov 10, 2020 at 3:22 AM Jason Merrill via Gcc-patches
> wrote:
> >
> > This patch was also applied to the GCC 9 and 10 branches and breaks those
> > builds, because PTA_CLDEMOTE is not defined.
>
On Tue, Nov 10, 2020 at 3:22 AM Jason Merrill via Gcc-patches
wrote:
>
> This patch was also applied to the GCC 9 and 10 branches and breaks those
> builds, because PTA_CLDEMOTE is not defined.
>
Mine, let me fix it, sorry for that.
--
BR,
Hongtao
On Mon, Nov 9, 2020 at 8:26 PM Uros Bizjak wrote:
>
> On Mon, Nov 9, 2020 at 11:31 AM Hongtao Liu wrote:
> >
> > >
> > > + /* Support unified builtin. */
> > > + || (mask2 == OPTION_MASK_ISA2_AVXVNNI)
> > >
> > > I don't t
ON_MASK_ISA2_AVX2_UNSET;
> }
>return true;
>
Yes.
> No review for the sse.md and for testcases.
>
> Uros.
Update the patch based on latest trunk.
--
BR,
Hongtao
From 881868b8c9f5925c63a953454f45f5e0a3c8ea4f Mon Sep 17 00:00:00 2001
From: liuhongt
Date: Tue, 13 Oct
Hi:
When programmers explicitly use mask loaded intrinsics, don't
transform the instruction to vpblend{b,w,d,q} since If mem_addr points
to a memory region with less than whole vector size of accessible
memory, the mask would prevent reading the inaccessible bytes which
could avoid fault.
On Tue, Nov 3, 2020 at 9:51 PM Richard Sandiford
wrote:
>
> Vladimir Makarov via Gcc-patches writes:
> > On 2020-10-27 2:53 a.m., Hongtao Liu wrote:
> >> Hi:
> >>For inline asm, there could be an operand like (not (mem:)), it's
> >> not a val
rnal/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf
> >
> > Bootstrap ok, regression test on i386/x86 backend is ok.
> >
> > OK for master?
> >
> > 2020-10-13 Hongtao Liu
> > Hongyu Wang
> >
> > gcc/
>
On Fri, Oct 30, 2020 at 1:00 AM Richard Sandiford
wrote:
>
> I guess my main objection is that we have a special memory constraint
> that isn't in fact matching a MEM (at least not directly). That seems
> odd and feels like it's going to come back to bite us.
>
> From an RTL perspective, the MEM
On Tue, Oct 27, 2020 at 7:13 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > Hi:
> > For inline asm, there could be an operand like (not (mem:)), it's
> > not a valid operand for normal memory constraint.
> > Bootstrap is ok, regres
On Wed, Oct 28, 2020 at 8:24 PM Uros Bizjak wrote:
>
> On Wed, Oct 28, 2020 at 10:54 AM Hongyu Wang wrote:
> >
> > Hi Uros,
> >
> > Thanks for the example. We've update the patterns with new expanders
> > and predicates like vzeroall.
> > Now the generated insn for "encodekey128u32" is like
> >
On Thu, Oct 29, 2020 at 2:46 AM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> > On Tue, Oct 27, 2020 at 7:13 PM Richard Sandiford
> > wrote:
> >>
> >> Hongtao Liu via Gcc-patches writes:
> >> > Hi:
> >> > For i
On Tue, Oct 27, 2020 at 7:13 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > Hi:
> > For inline asm, there could be an operand like (not (mem:)), it's
> > not a valid operand for normal memory constraint.
> > Bootstrap is ok, regres
ping^1
On Tue, Oct 20, 2020 at 3:36 PM Richard Biener
wrote:
>
> On Tue, Oct 20, 2020 at 4:35 AM Hongtao Liu wrote:
> >
> > On Mon, Oct 19, 2020 at 5:55 PM Richard Biener
> > wrote:
> > >
> > > On Mon, Oct 19, 2020 at 11:37 AM Hongtao Liu wrote:
>
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