Re: [AArch64] Give some new costs for Cortex-A57 floating-point operations

On Fri, Jun 03, 2016 at 09:35:50AM +0100, James Greenhalgh wrote: > > Hi, > > This patch rebases the floating-point cost table for Cortex-A57 to be > relative to the cost of a floating-point move. This in response to this > feedback from Richard Sandiford [2] on Ramana's p

Re: [PATCH 1/2][AArch64] Implement AAPCS64 updates for alignment attribute

On Tue, Jun 07, 2016 at 12:07:03PM +0100, James Greenhalgh wrote: > On Fri, Jan 22, 2016 at 05:16:00PM +, Alan Lawrence wrote: > > > > On 21/01/16 17:23, Alan Lawrence wrote: > > > On 18/01/16 17:10, Eric Botcazou wrote: > > >> > > >> Could

Re: [v2][AArch64, 6/6] Reimplement vpadd intrinsics & extend rtl patterns to all modes

On Mon, Jun 06, 2016 at 02:40:55PM +0100, Jiong Wang wrote: > These intrinsics was implemented by inline assembly using "faddp" instruction. > There was a pattern "aarch64_addpv4sf" which supportsV4SF mode only while we > can > extend this pattern to support VDQF mode, then we can reimplement

Re: [v2][AArch64, 5/6] Reimplement fabd intrinsics & merge rtl patterns

On Mon, Jun 06, 2016 at 02:40:45PM +0100, Jiong Wang wrote: > These intrinsics were implemented before "fabd_3" introduces. > Meanwhile > the patterns "fabd_3" and "*fabd_scalar3" can be merged into a > single "fabd3" using VALLF. > > This patch migrate the implementation to builtins backed by

Re: [v2][AArch64, 4/6] Reimplement frsqrts intrinsics

On Mon, Jun 06, 2016 at 02:40:33PM +0100, Jiong Wang wrote: > Similar as [3/6], these intrinsics were implemented before the instruction > pattern "aarch64_rsqrts" added, that these intrinsics were implemented > through inline assembly. > > This mirgrate the implementation to builtin. OK.

Re: [v2][AArch64, 3/6] Reimplement frsqrte intrinsics

On Mon, Jun 06, 2016 at 02:40:22PM +0100, Jiong Wang wrote: > These intrinsics were implemented before the instruction pattern > "aarch64_rsqrte" added, that these intrinsics were implemented through > inline assembly. > > This mirgrate the implementation to builtin. OK. Thanks for the extra

Re: [v2][AArch64, 2/6] Reimplement vector fixed-point intrinsics

On Mon, Jun 06, 2016 at 02:39:38PM +0100, Jiong Wang wrote: > Based on top of [1/6], this patch reimplement vector intrinsics for > conversion between floating-point and fixed-point. OK. Thanks, James > > gcc/ > 2016-06-06 Jiong Wang > > *

Re: [v2][AArch64, 1/6] Reimplement scalar fixed-point intrinsics

On Mon, Jun 06, 2016 at 02:38:58PM +0100, Jiong Wang wrote: > On 27/05/16 17:52, Jiong Wang wrote: > > > > > >On 27/05/16 14:03, James Greenhalgh wrote: > >>On Tue, May 24, 2016 at 09:23:36AM +0100, Jiong Wang wrote: > >>> * config

Re: [PATCH 9/17][ARM] Add NEON FP16 arithmetic instructions.

On Thu, May 19, 2016 at 05:29:16PM +, Joseph Myers wrote: > On Thu, 19 May 2016, Jiong Wang wrote: > > > Then, > > > > * if we add scalar HF mode to standard patterns, vector HF modes operation > > will be > > turned into scalar HF operations instead of scalar SF operations. > > > >

Re: [PATCH 2/2][AArch64] Tests of AAPCS64 updates for alignment attribute

On Fri, Jan 15, 2016 at 02:17:43PM +, Alan Lawrence wrote: > Here I've added both tests using the abitest.h framework(which verifies values > are passed in the correct registers as specified by the AAPCS64), and separate > tests which verify that called functions read arguments from the same

Re: [PATCH 1/2][AArch64] Implement AAPCS64 updates for alignment attribute

On Fri, Jan 22, 2016 at 05:16:00PM +, Alan Lawrence wrote: > > On 21/01/16 17:23, Alan Lawrence wrote: > > On 18/01/16 17:10, Eric Botcazou wrote: > >> > >> Could you post the list of files that differ? How do they differ exactly? > > > > Hmmm. Well, I definitely had this failing to

Re: [PATCH][AArch64] Model CSEL instruction in Cortex-A57 scheduling model

On Tue, Jun 07, 2016 at 09:22:05AM +0100, Ramana Radhakrishnan wrote: > > > On 06/06/16 17:10, Kyrill Tkachov wrote: > > Hi all, > > > > This small patch adds handling of the CSEL-type instructions to the > > Cortex-A57 scheduling model. > > It is treated the same as simple ALU instructions. >

[Patch AArch64] Refactor and clean up some of the sched_fusion handling

Hi, I had a little trouble understanding the sched_fusion code, so I refactored it and added some comments. I think this is a bit easier to read, but I'm equally happy dropping the patch. Bootstrapped on aarch64-none-linux-gnu. OK? Thanks, James --- 2016-06-03 James Greenhalgh

Re: [Patch AArch64 2/2] Some more cleanup of ldp/stp generation

*ping* https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01192.html Thanks, James On Tue, May 17, 2016 at 10:22:31AM +0100, James Greenhalgh wrote: > > This is another refactoring patch to clean up more of the ldp/stp handling > code and avoid duplicating quite as much code. >

Re: [AArch64 1/2] Refactor aarch64_operands_ok_for_ldpstp, aarch64_operands_adjust_ok_for_ldpstp

*ping* https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01193.html Thanks, James On Tue, May 17, 2016 at 10:22:30AM +0100, James Greenhalgh wrote: > > Hi, > > These two functions are very similar and suffer from code duplication. > With a little bit of work we can reduce the strai

[AArch64] Give some new costs for Cortex-A57 floating-point operations

this fixes the issue Ramana was seeing, in a way consistent with what other back-ends do. This patch gives a small improvement to Spec2000FP on a Cortex-A57 platform. Bootstrapped on aarch64-none-linux-gnu with no issues. OK? Thanks, James --- 2016-06-03 James Greenhalgh <james.greenha...@arm.

[RFC: Patch 6/6] Remove second cost model from noce_try_store_flag_mask

James Greenhalgh <james.greenha...@arm.com> * ifcvt.c (noce_try_store_flag_mask): Delete redundant cost model. diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c index f71889e..6e9997e 100644 --- a/gcc/ifcvt.c +++ b/gcc/ifcvt.c @@ -1670,8 +1670,8 @@ noce_try_store_flag_mask (struct noce_i

[RFC: Patch 3/6] Remove if_info->branch_cost

Hi, This patch removes what is left of branch_cost uses, moving them to use the new hook and tagging each left over spot with a TODO to revisit them. All these uses are in rtx costs units, so we don't have more work to do at this point. OK? Thanks, James --- 2016-06-02 James Greenhalgh

[RFC: Patch 2/6] Factor out the comparisons against magic numbers in ifcvt

ed cost model should we want it. OK? Thanks, James --- 2016-06-02 James Greenhalgh <james.greenha...@arm.com> * ifcvt.c (noce_if_info): New field: rtx_edge_cost. (noce_estimate_conversion_profitable_p): New. (noce_try_store_flag_constants): Use it. (noce_t

[RFC: Patch 5/6] Improve the cost model for multiple-sets

Hi, This patch is a small rewrite to the cost model for bb_ok_for_noce_multiple_sets to use the new noce_cmove_estimate_cost function added in the previous patches. Thanks, James --- 2016-06-02 James Greenhalgh <james.greenha...@arm.com> * i

[RFC: Patch 0/6] Rewrite the noce-ifcvt cost models

some further polishing if we were to decide this was a useful direction. Thanks, James James Greenhalgh (6): [RFC: Patch 1/6] New target hook: rtx_branch_cost [RFC: Patch 2/6] Factor out the comparisons against magic numbers in ifcvt [RFC: Patch 3/6] Remove if_info->branch_cost

[RFC: Patch 4/6] Modify cost model for noce_cmove_arith

cost model should rely on the target giving back good information. A target that finds tests failing after this patch should consider either reducing the cost of a conditional move sequence, or increasing TARGET_RTX_BRANCH_COST. OK? Thanks, James --- gcc/ 2016-06-02 James Greenhalgh <

[RFC: Patch 1/6] New target hook: rtx_branch_cost

hook. To keep things consistent for targets which don't migrate, this new hook has a default value of BRANCH_COST * COSTS_N_INSNS (1). OK? Thanks, James --- 2016-06-02 James Greenhalgh <james.greenha...@arm.com> * target.def (rtx_branch_cost): New. * doc/tm.t

Re: [PATCH][wwwdocs][AArch64] Mention -mcpu=qdf24xx support for GCC 6

On Thu, Jun 02, 2016 at 03:54:43PM +0100, Kyrill Tkachov wrote: > Hi all, > > As discussed some time ago with Jim, here's the AArch64 note mentioning the > support for Qualcomm QDF24xx that was added in GCC 6. > > Ok to commit? OK. Thanks, James > Index: htdocs/gcc-6/changes.html >

Re: [PATCH][AArch64] Add missing fcsel in Cortex-A57 scheduler

On Thu, Jun 02, 2016 at 04:09:32PM +, Wilco Dijkstra wrote: > The Cortex-A57 scheduler is missing fcsel, so add it. > > OK for commit? OK. Thanks, James > > ChangeLog: > 2016-06-02 Wilco Dijkstra > > * config/arm/cortex-a57.md (cortex_a57_fp_cpys): Add fcsel. >

Re: [PATCH 2/3][AArch64] Emit square root using the Newton series

On Fri, May 27, 2016 at 05:57:26PM -0500, Evandro Menezes wrote: > 2016-04-04 Evandro Menezes > Wilco Dijkstra > > gcc/ > * config/aarch64/aarch64-protos.h > (aarch64_emit_approx_rsqrt): Replace with new function >

Re: [PATCH 1/3][AArch64] Add more choices for the reciprocal square root approximation

On Fri, May 27, 2016 at 05:57:23PM -0500, Evandro Menezes wrote: > From 86d7690632d03ec85fd69bfaef8e89c0542518ad Mon Sep 17 00:00:00 2001 > From: Evandro Menezes > Date: Thu, 3 Mar 2016 18:13:46 -0600 > Subject: [PATCH 1/3] [AArch64] Add more choices for the reciprocal

Re: [AArch64][3/4] Don't generate redundant checks when there is no composite arg

On Fri, May 06, 2016 at 04:00:40PM +0100, Jiong Wang wrote: > 2016-05-06 Jiong Wang > > gcc/ > * config/aarch64/aarch64.c (aarch64_gimplify_va_arg_expr): Avoid > duplicated check code. > > gcc/testsuite/ > * gcc.target/aarch64/va_arg_4.c: New testcase. I wonder

Re: [PATCH AArch64]Support missing vcond pattern by adding/using vec_cmp/vcond_mask patterns.

On Tue, May 17, 2016 at 09:02:22AM +, Bin Cheng wrote: > Hi, > Alan and Renlin noticed that some vcond patterns are not supported in > AArch64(or AArch32?) backend, and they both had some patches fixing this. > After investigation, I agree with them that vcond/vcondu in AArch64's backend >

Re: [PATCH] AARCH64: Remove spurious attribute __unused__ from NEON intrinsic

On Mon, Apr 25, 2016 at 05:47:57PM +0100, James Greenhalgh wrote: > On Mon, Apr 25, 2016 at 05:39:45PM +0200, Wladimir J. van der Laan wrote: > > > > Thanks for the info with regard to contributing, > > > > On Fri, Apr 22, 2016 at 09:40:11AM +0100, James Greenha

Re: [PATCH][AArch64] Use aarch64_fusion_enabled_p to check for insn fusion capabilities

On Fri, May 27, 2016 at 06:10:42PM -0500, Evandro Menezes wrote: > On 05/27/16 11:59, Kyrill Tkachov wrote: > >Hi all, > > > >This patch is a small cleanup that uses the newly introduced > >aarch64_fusion_enabled_p predicate > >to check for what fusion opportunities are enabled for the current >

Re: [PATCH][AArch64] Remove aarch64_simd_attr_length_move

On Fri, May 27, 2016 at 05:57:17PM +0100, Kyrill Tkachov wrote: > Hi all, > > I notice that we can do without aarch64_simd_attr_length_move. The move > alternatives for > the OI,CI,XImode modes that involve memory operands all use a single > load/store so are always > length 4, whereas the

Re: [PATCH][AArch64] Enable -frename-registers at -O2 and higher

On Fri, May 27, 2016 at 02:50:15PM +0100, Kyrill Tkachov wrote: > Hi all, > > As mentioned in https://gcc.gnu.org/ml/gcc-patches/2016-05/msg00297.html, > frename-registers registers can be beneficial for aarch64 and the patch at > https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01618.html resolves

Re: [PATCH 3/3][AArch64] Emit division using the Newton series

On Fri, May 27, 2016 at 05:57:30PM -0500, Evandro Menezes wrote: > On 05/25/16 11:16, James Greenhalgh wrote: > >On Wed, Apr 27, 2016 at 04:15:53PM -0500, Evandro Menezes wrote: > >>gcc/ > >> * config/aarch64/aarch64-protos.h > >> (tune_param

Re: [AArch64, 6/6] Reimplement vpadd intrinsics & extend rtl patterns to all modes

On Tue, May 24, 2016 at 09:24:03AM +0100, Jiong Wang wrote: > These intrinsics was implemented by inline assembly using "faddp" > instruction. > There was a pattern "aarch64_addpv4sf" which supportsV4SF mode only > while we can > extend this pattern to support VDQF mode, then we can reimplement

Re: [AArch64, 5/6] Reimplement fabd intrinsics & merge rtl patterns

On Tue, May 24, 2016 at 09:23:58AM +0100, Jiong Wang wrote: > These intrinsics were implemented before "fabd_3" introduces. > Meanwhile > the patterns "fabd_3" and "*fabd_scalar3" can be merged into a > single "fabd3" using VALLF. > > This patch migrate the implementation to builtins backed by

Re: [AArch64, 3/6] Reimplement frsqrte intrinsics

On Tue, May 24, 2016 at 09:23:48AM +0100, Jiong Wang wrote: > These intrinsics were implemented before the instruction pattern > "aarch64_rsqrte" added, that these intrinsics were implemented through > inline assembly. > > This mirgrate the implementation to builtin. > > gcc/ > 2016-05-23 Jiong

Re: [AArch64, 4/6] Reimplement frsqrts intrinsics

On Tue, May 24, 2016 at 09:23:53AM +0100, Jiong Wang wrote: > Similar as [3/6], these intrinsics were implemented before the instruction > pattern "aarch64_rsqrts" added, that these intrinsics were implemented > through inline assembly. > > This mirgrate the implementation to builtin. > > gcc/ >

Re: [AArch64, 1/6] Reimplement scalar fixed-point intrinsics

On Tue, May 24, 2016 at 09:23:36AM +0100, Jiong Wang wrote: > This patch reimplement scalar intrinsics for conversion between floating- > point and fixed-point. > > Previously, all such intrinsics are implemented through inline assembly. > This patch added RTL pattern for these operations that

Re: [PATCH, AArch64] atomics: prefetch the destination for write prior to ldxr/stxr loops

On Tue, Mar 15, 2016 at 03:31:30PM +, James Greenhalgh wrote: > On Mon, Mar 07, 2016 at 10:54:25PM -0800, Andrew Pinski wrote: > > On Mon, Mar 7, 2016 at 8:12 PM, Yangfei (Felix) <felix.y...@huawei.com> > > wrote: > > >> On Mon, Mar 7, 2016 at 7:27 PM, Yangf

Re: [PATCH][2/3][AArch64] Keep CTZ components together until after reload

On Thu, May 26, 2016 at 10:53:07AM +0100, Kyrill Tkachov wrote: > Hi all, > > In a similar rationale to patch 1/3 this patch changes the AArch64 backend to > keep the CTZ expression as a single RTX until after reload when it is split > into an RBIT and a CLZ instruction. This enables

Re: [PATCH][AArch64] Simplify ashl3 expander for SHORT modes

On Wed, Apr 27, 2016 at 03:10:47PM +0100, Kyrill Tkachov wrote: > Hi all, > > The ashl3 expander for QI and HI modes is needlessly obfuscated. > The 2nd operand predicate accepts nonmemory_operand but the expand code > FAILs if it's not a CONST_INT. We can just demand a const_int_operand in > the

Re: [PATCH][AArch64] Remove aarch64_cannot_change_mode_class

On Thu, May 19, 2016 at 12:23:32PM +0100, Wilco Dijkstra wrote: > Remove aarch64_cannot_change_mode_class as the underlying issue > (PR67609) has been resolved. This avoids a few unnecessary lane > widening operations like: > > faddp d18, v18.2d > mov d18, v18.d[0] > > Passes regress, OK

Re: [PATCH][AArch64] Delete obsolete CC_ZESWP and CC_SESWP CC modes

On Wed, Apr 27, 2016 at 03:12:10PM +0100, Kyrill Tkachov wrote: > Hi all, > > The CC_ZESWP and CC_SESWP are not used anywhere and seem to be a remmant of > some > old code that was removed. The various compare+extend patterns in aarch64.md > don't > use these modes. So it should be safe to

Re: [AArch64][2/4] PR63596, honor tree-stdarg analysis result to improve VAARG codegen

On Fri, May 06, 2016 at 04:00:28PM +0100, Jiong Wang wrote: > This patch fixes PR63596. > > There is no need to push/pop all arguments registers. We only need to > push and pop those registers used. These use info is calculated by a > dedicated vaarg optimization tree pass "tree-stdarg", the

Re: [AArch64][1/4] Enable tree-stdarg pass for AArch64 by defining counter fields

On Fri, May 06, 2016 at 04:00:13PM +0100, Jiong Wang wrote: > This patch initialize va_list_gpr_counter_field and > va_list_fpr_counter_field properly for AArch64 backend that tree-stdarg > pass will be enabled. > > The "required register" analysis is largely target independent, but the > user

Re: [PATCH][AArch64] Adjust SIMD integer preference

On Fri, Apr 22, 2016 at 03:35:42PM +, Wilco Dijkstra wrote: > SIMD operations like combine prefer to have their operands in FP registers, > so increase the cost of integer registers slightly to avoid unnecessary > int<->FP moves. This improves register allocation of scalar SIMD operations. I

Re: [PATCH][AArch64] Tie operand 1 to operand 0 in AESMC pattern when AES/AESMC fusion is enabled

On Fri, May 20, 2016 at 11:04:32AM +0100, Kyrill Tkachov wrote: > Hi all, > > The recent -frename-registers change exposed a deficiency in the way we fuse > AESE/AESMC instruction pairs in aarch64. > > Basically we want to enforce: > AESE Vn, _ > AESMC Vn, Vn > > to enable the fusion,

Re: [PATCH/AARCH64/ILP32] Fix unwinding (libgcc)

On Wed, Apr 27, 2016 at 02:13:21PM -0700, Andrew Pinski wrote: > Hi, > AARCH64 ILP32 is like x32 where UNITS_PER_WORD > sizeof(void*) so we > need to define REG_VALUE_IN_UNWIND_CONTEXT for ILP32. This fixes > unwinding through the signal handler. This is independent of the ABI > which Linux

Re: [PATCH][AArch64] Improve aarch64_case_values_threshold setting

On Mon, May 16, 2016 at 11:38:04AM +0100, Wilco Dijkstra wrote: > GCC expands switch statements in a very simplistic way and tries to use a > table > expansion even when it is a bad idea for performance or codesize. > GCC typically emits extremely sparse tables that contain mostly default >

Re: [AArch64, 2/4] Extend vector mutiply by element to all supported modes

On Wed, May 18, 2016 at 02:13:53PM +0100, Jiong Wang wrote: > Thanks for reporting this. > > Yes, reproduced. I should force those res* local variable into > memory so they can be in the same order as the expected result > which is kept in memory. > > The following patch fix this. > >

Re: [PATCH 3/3][AArch64] Emit division using the Newton series

On Wed, Apr 27, 2016 at 04:15:53PM -0500, Evandro Menezes wrote: >gcc/ > * config/aarch64/aarch64-protos.h > (tune_params): Add new member "approx_div_modes". > (aarch64_emit_approx_div): Declare new function. > * config/aarch64/aarch64.c >

Re: [PATCH 2/3][AArch64] Emit square root using the Newton series

On Wed, Apr 27, 2016 at 04:15:45PM -0500, Evandro Menezes wrote: >gcc/ > * config/aarch64/aarch64-protos.h > (aarch64_emit_approx_rsqrt): Replace with new function > "aarch64_emit_approx_sqrt". > (tune_params): New member "approx_sqrt_modes". > *

Re: [PATCH 1/3][AArch64] Add more choices for the reciprocal square root approximation

On Wed, Apr 27, 2016 at 04:13:33PM -0500, Evandro Menezes wrote: >gcc/ > * config/aarch64/aarch64-protos.h > (AARCH64_APPROX_MODE): New macro. > (AARCH64_APPROX_{NONE,SP,DP,DFORM,QFORM,SCALAR,VECTOR,ALL}): >Likewise. > (tune_params): New member

Re: [PATCH][wwwdocs] Improve arm and aarch64-related info in readings.html

On Thu, May 19, 2016 at 04:27:31PM +0100, Kyrill Tkachov wrote: > Hi all, > > I noticed that we have a readings.html page that has pointers to > documentation of various backends that GCC supports. The info on arm seems a > bit out of date and somewhat confusing, and there is no entry for

Re: [AArch64, 4/4] Reimplement vmvn* intrinscis, remove inline assembly

On Mon, May 16, 2016 at 10:09:42AM +0100, Jiong Wang wrote: > This patch remove inline assembly and reimplement all mvn/mvnq vector > integer intrinsics through the standard "one_cmpl2" pattern was > introduced later after the initial implementation of those intrinsics. > that's why inline

Re: [AArch64, 3/4] Reimplement multiply by element to get rid of inline assembly

On Mon, May 16, 2016 at 10:09:37AM +0100, Jiong Wang wrote: > This patch reimplement vector multiply by element on top of the existed > vmul_lane* intrinsics instead of inline assembly. > > There is no code generation change from this patch. > > OK for trunk? > > 2016-05-16 Jiong

Re: [AArch64, 2/4] Extend vector mutiply by element to all supported modes

On Mon, May 16, 2016 at 10:09:31AM +0100, Jiong Wang wrote: > AArch64 support vector multiply by element for V2DF, V2SF, V4SF, V2SI, > V4SI, V4HI, V8HI. > > All above are well supported by "*aarch64_mul3_elt" pattern and > "*aarch64_mul3_elt_" if there is lane size > change. > > Above patterns

Re: [AArch64, 1/4] Add the missing support of vfms_n_f32, vfmsq_n_f32, vfmsq_n_f64

On Mon, May 16, 2016 at 10:09:26AM +0100, Jiong Wang wrote: > The support of vfma_n_f64, vfms_n_f32, vfmsq_n_f32, vfmsq_n_f64 are > missing in current gcc arm_neon.h. > > Meanwhile, besides "(fma (vec_dup (vec_select)))", fma by element can > also comes from "(fma (vec_dup(scalar" where the

Re: [PATCH][AArch64] PR target/70809: Delete aarch64_vmls pattern

On Tue, May 17, 2016 at 11:37:57AM +0100, Kyrill Tkachov wrote: > Hi all, > > The aarch64_vmls pattern claims to perform a normal vector > floating-point multiply-subtract but in fact performs a fused > multiply-subtract. This is fine when -ffp-contract=fast, but it's not guarded > on anything so

Re: [Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequence

On Tue, May 17, 2016 at 11:32:36AM +0100, Marcus Shawcroft wrote: > On 17 May 2016 at 10:06, James Greenhalgh <james.greenha...@arm.com> wrote: > > > > Hi, > > > > This is just a simplification, it probably makes life easier for register > > allocation i

Re: [PATCH][AArch64][tests] Skip cpu-diagnostics tests when overriding -mcpu

On Mon, May 16, 2016 at 05:18:44PM +0100, Kyrill Tkachov wrote: > Hi all, > > The gcc.target/aarch64/cpu-diagnostics* tests specify invalid -mcpu options > and look for the expected error. > However, if the user overrides the -mcpu option when testing the tests start > FAILing because they

Re: [AARCH64] Remove static variable all_extensions from aarch64.c

On Tue, May 17, 2016 at 12:14:28PM +1000, Kugan Vivekanandarajah wrote: > Hi, > > static variable all_extensions in aarch64.c is not used and therefore > dead. I don’t see any reason why it should be there. Attached patch > removes this. > > > Bootstrapped on aarch64-linux-gnu. Regression

[AArch64 1/2] Refactor aarch64_operands_ok_for_ldpstp, aarch64_operands_adjust_ok_for_ldpstp

instead, at which point it becomes clear that these functions are very similar and can be pulled together. OK? Bootstrapped and tested for aarch64-none-linux-gnu with no issues. OK? Thanks, James --- 2016-05-17 James Greenhalgh <james.greenha...@arm.com> * config/aarch64/aar

[Patch AArch64 2/2] Some more cleanup of ldp/stp generation

, James --- 2016-05-17 James Greenhalgh <james.greenha...@arm.com> * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Refactor. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 434c154..01bbe81 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/

[Patch AArch64 0/2] Refactor ldp/stp code

this is subjective. I've bootstrapped the two patches on aarch64-none-linux-gnu with no issues. OK? Thanks, James --- [AArch64 1/2] Refactor aarch64_operands_ok_for_ldpstp, aarch64_operands_adjust_ok_for_ldpstp 2016-05-17 James Greenhalgh <james.greenha...@arm.com> * config/a

[Patch AArch64] Delete ASM_OUTPUT_DEF and fallback to default .set directive

fe to drop this. Bootstrapped on aarch64-none-linux-gnu. OK? Thanks, James [1]: https://gcc.gnu.org/ml/gcc-patches/2016-03/msg01691.html --- 2016-05-17 James Greenhalgh <james.greenha...@arm.com> * config/aarch64/aarch64-elf.h (ASM_OUTPUT_DEF): Delete. diff --git a/gcc/config/aarch64

[Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequence

, James --- 2016-05-17 James Greenhalgh <james.greenha...@arm.com> * config/aarch64/aarch64-simd.md (aarch64_reduc_plus_internal): Rename to... (reduc_plus_scal): ...This, and remove previous implementation. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/a

[Patch obvious] Fix indentation in c-typeck.c parser_build_unary_op

Hi, This patch is an obvious fix for some out of place indentation in parser_build_unary_op. I've checked that my new spacing didn't break the build on aarch64 or x86_64. Committed as obvious as revision 236313. Thanks, James --- gcc/c/ 2016-05-17 James Greenhalgh <james.gree

[Patch obvious AArch64] Wrap SHIFT_COUNT_TRUNCATED in brackets

Hi, This is probably not going to be an issue, but we should wrap the macro definition in () just in case someone does want to use it with a higher precedence operator. Applied as obvious as revision 236312. Thanks, James --- 2016-05-16 James Greenhalgh <james.greenha...@arm.

[AArch64 trivial] Don't define a macro when a variable will do

Hi, As title, this use of macros doesn't make much sense to me. We can just do this as a const unsigned int. Comitted as obvious as revision 236311. OK? Thanks, James --- 2016-05-17 James Greenhalgh <james.greenha...@arm.com> * config/aarch64/aar

Re: [PATCH][AArch64] Improve aarch64_case_values_threshold setting

On Mon, May 16, 2016 at 11:38:04AM +0100, Wilco Dijkstra wrote: > ping As this change will change code generation for all cores (except Exynos-M1), I'd like to hear from those with more detailed knowledge of ThunderX, X-Gene and qdf24xx before I take this patch. Let's give it another week or so

Re: [PATCH][AArch64] print_operand should not fallthrough from register operand into generic operand

On Wed, Apr 27, 2016 at 05:39:33PM +0100, Wilco Dijkstra wrote: > James Greenhalgh wrote: > > So the part of this patch removing the fallthrough to general operand > > is not OK for trunk. > > > > The other parts look reasonable to me, please resubmit just those. >

Re: [Patch ARM/AArch64 00/11][testsuite] AdvSIMD intrinsics update

On Wed, May 11, 2016 at 03:23:50PM +0200, Christophe Lyon wrote: > Hi, > > A few months ago, we decided it was time to remove neon-testgen.ml > and its generated tests. I did it, just to realize too late that > some intrinsics were not covered anymore, so I reverted the removal. > > This patch

Re: [Patch ARM/AArch64 10/11] Add missing tests for intrinsics operating on poly64 and poly128 types.

On Wed, May 11, 2016 at 03:24:00PM +0200, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (result): > Add poly64x1_t and poly64x2_t cases if supported. > *

Re: [Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type.

On Wed, May 11, 2016 at 03:24:01PM +0200, Christophe Lyon wrote: > 2016-05-04 Christophe Lyon > > * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add fp16 > tests. > * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise. >

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

On Wed, May 11, 2016 at 03:23:59PM +0200, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New. > * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New. > *

Re: [Patch ARM/AArch64 08/11] Add missing vstX_lane fp16 tests.

On Wed, May 11, 2016 at 03:23:58PM +0200, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Add fp16 tests. OK. Thanks, James

Re: [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests.

On Fri, May 13, 2016 at 04:41:33PM +0200, Christophe Lyon wrote: > On 13 May 2016 at 16:37, James Greenhalgh <james.greenha...@arm.com> wrote: > > On Wed, May 11, 2016 at 03:23:56PM +0200, Christophe Lyon wrote: > >> 2016-05-02 Christophe Lyon <

Re: [Patch ARM/AArch64 07/11] Add missing vget_lane fp16 tests.

On Wed, May 11, 2016 at 03:23:57PM +0200, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc.target/aarch64/advsimd-intrinsics/vget_lane.c: Add fp16 tests. OK. Thanks, James

Re: [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests.

On Wed, May 11, 2016 at 03:23:56PM +0200, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests > for vtst_p8 and vtstq_p8. And vtst_p16 and vtstq_p16 too please. vtst_s64 vtstq_s64 vtst_u64

Re: [Patch ARM/AArch64 05/11] Add missing vreinterpretq_p{8,16} tests.

On Wed, May 11, 2016 at 03:23:55PM +0200, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add > missing tests for vreinterpretq_p{8,16}. OK. Thanks, James

Re: [Patch ARM/AArch64 03/11] AdvSIMD tests: be more verbose.

On Wed, May 11, 2016 at 03:23:53PM +0200, Christophe Lyon wrote: > It is useful to have more detailed information in the logs when checking > validation results: instead of repeating the intrinsic name, we now print > its return type too. > > 2016-05-02 Christophe Lyon

Re: [Patch ARM/AArch64 04/11] Add forgotten vsliq_n_u64 test.

On Wed, May 11, 2016 at 03:23:54PM +0200, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: Add check for > vsliq_n_u64. > And vsliq_n_s64 ? OK with that change. Thanks, James > Change-Id:

Re: [testuite,AArch64] Make scan for 'br' more robust

On Wed, May 04, 2016 at 11:55:42AM +0200, Christophe Lyon wrote: > On 4 May 2016 at 10:43, Kyrill Tkachov wrote: > > > > Hi Christophe, > > > > > > On 02/05/16 12:50, Christophe Lyon wrote: > >> > >> Hi, > >> > >> I've noticed a "regression" of AArch64's noplt_3.c in

Re: [Patch ARM/AArch64 02/11] We can remove useless #ifdefs from these tests: vmul, vshl and vtst.

On Wed, May 11, 2016 at 03:23:52PM +0200, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc.target/aarch64/advsimd-intrinsics/vmul.c: Remove useless #ifdef. > * gcc.target/aarch64/advsimd-intrinsics/vshl.c: Likewise. > *

Re: [Patch ARM/AArch64 01/11] Fix typo in vreinterpret.c test comment.

On Wed, May 11, 2016 at 03:23:51PM +0200, Christophe Lyon wrote: > 2016-05-02 Christophe Lyon > > * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo in > comment. This one would have been OK to commit as obvious. OK for trunk. Thanks, James

Re: [AArch64] Remove an unused reload hook.

On Thu, Apr 28, 2016 at 03:11:59PM +0100, Matthew Wahab wrote: > Hello, > > Yvan Roux pointed out that the patch at > https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01713.html was never > committed. > > From the original submission: > > The LEGITIMIZE_RELOAD_ADDRESS macro is only needed for

Re: [PATCH][AArch64] print_operand should not fallthrough from register operand into generic operand

On Fri, Apr 22, 2016 at 02:24:49PM +, Wilco Dijkstra wrote: > Some patterns are using '%w2' for immediate operands, which means that a zero > immediate is actually emitted as 'wzr' or 'xzr'. This not only changes an > immediate operand into a register operand but may emit illegal instructions

Re: [PATCH][AArch64] Fix shift attributes

On Fri, Apr 22, 2016 at 02:11:52PM +, Wilco Dijkstra wrote: > This patch fixes the attributes of integer immediate shifts which were > incorrectly modelled as register controlled shifts. Also change EXTR > attribute to being a rotate. > > OK for trunk? OK. Thanks for the fix. Thanks, James

Re: [PATCH][AArch64] Improve aarch64_modes_tieable_p

On Fri, Apr 22, 2016 at 01:22:51PM +, Wilco Dijkstra wrote: > Improve modes_tieable by returning true in more cases: allow scalar access > within vectors without requiring an extra move. Removing these moves helps > the register allocator in deciding whether to use integer or FP registers on >

Re: [AArch64] Emit square root using the Newton series

On Tue, Apr 12, 2016 at 01:14:51PM -0500, Evandro Menezes wrote: > On 04/05/16 17:30, Evandro Menezes wrote: > >On 04/05/16 13:37, Wilco Dijkstra wrote: > >>I can't get any of these to work... Not only do I get a large > >>number of collisions and duplicated > >>code between these patches, when I

Re: [AArch64] Emit division using the Newton series

> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index b7086dd..21af809 100644 > --- a/gcc/config/aarch64/aarch64.c > +++ b/gcc/config/aarch64/aarch64.c > @@ -414,7 +414,8 @@ static const struct tune_params generic_tunings = >0, /* max_case_values. */ >0, /*

Re: [Patch AArch64] Set TARGET_OMIT_STRUCT_RETURN_REG to true.

On Tue, Apr 26, 2016 at 02:22:58PM +0100, Ramana Radhakrishnan wrote: > As $SUBJECT. The reason this caught my eye on aarch64 is because > the return value register (x0) is not identical to the register in which > the hidden parameter for AArch64 is set (x8). Thus setting this to true > seems to

Re: [PATCH] AARCH64: Remove spurious attribute __unused__ from NEON intrinsic

On Mon, Apr 25, 2016 at 05:39:45PM +0200, Wladimir J. van der Laan wrote: > > Thanks for the info with regard to contributing, > > On Fri, Apr 22, 2016 at 09:40:11AM +0100, James Greenhalgh wrote: > > This patch will need a ChangeLog entry [1], please draft one that I can &g

Re: [PATCH 2/2] (header usage fix) include c++ headers in system.h

On Fri, Apr 22, 2016 at 11:02:48AM +0100, Szabolcs Nagy wrote: > Some gcc source files include standard headers after > "system.h" but those headers may declare and use poisoned > symbols, they also cannot be included before "system.h" > because they might depend on macro definitions from there, >

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

On Thu, Apr 21, 2016 at 09:15:17AM +0100, Kyrill Tkachov wrote: > Hi all, > > Here's a proposed summary of the changes in the AArch64 backend for GCC 6. > If there's anything I've missed it's purely my oversight, feel free to add > entries or suggest improvements. For me, I'm mostly happy with

Re: [PATCH] AARCH64: Remove spurious attribute __unused__ from NEON intrinsic

On Fri, Apr 22, 2016 at 07:59:41AM +0200, Wladimir J. van der Laan wrote: > The lane parameter is not unused, so should not be marked as such. > > The others were removed in https://patchwork.ozlabs.org/patch/272912/, > but this one appears to have been missed. The patch looks good to me, and is

Re: [PATCH][AArch64] Work around PR target/64971

On Fri, Apr 15, 2016 at 03:12:58PM +0100, Kyrill Tkachov wrote: > > On 15/04/16 15:10, Kyrill Tkachov wrote: > >Hi all, > > > >This is a repost of Andrew's fix for PR target/64971 that was originally > >posted at: > >https://gcc.gnu.org/ml/gcc-patches/2015-02/msg00502.html > > > >The only change

Re: [PATCH][AArch64] Backport of PR 70044 fix to GCC 5

On Thu, Apr 14, 2016 at 02:24:48PM +0100, Kyrill Tkachov wrote: > Ping. > https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00142.html > > Thanks, > Kyrill > On 04/04/16 10:10, Kyrill Tkachov wrote: > >Hi all, > > > >I'd like to backport Nicks' patch for PR 70044 to the GCC 5 branch. > >The patch

<    3   4   5   6   7   8   9   10   11   12   >