Re: [Patch AArch64 3/3] Fix up for pr70133

erated with '-w' to skip the whitespace changes. OK? Thanks, James > --- > 2016-04-06 James Greenhalgh <james.greenha...@arm.com> > > PR target/70133 > > * config/aarch64/driver-aarch64.c > (aarch64_get_extension_string_for_isa_flags): New. > (arch_ex

Re: [Patch AArch64 1/3] Enable CRC by default for armv8.1-a

On Thu, Apr 07, 2016 at 05:23:59PM +0200, Christophe Lyon wrote: > On 6 April 2016 at 12:10, James Greenhalgh <james.greenha...@arm.com> wrote: > > > > Hi, > > > > This change reflects binutils support for CRC, where it is always enabled > > for armv8.1-

[Patch AArch64 3/3] Fix up for pr70133

the input data in pr70133. OK? Thanks, James --- 2016-04-06 James Greenhalgh <james.greenha...@arm.com> PR target/70133 * config/aarch64/driver-aarch64.c (aarch64_get_extension_string_for_isa_flags): New. (arch_extension):

[Patch AArch64 2/3] Rework the code to print extension strings (pr70133)

-none-linux-gnu and tested for the defaults, and with an explicit -march=native passed to dejagnu. OK? Thanks, James --- gcc/ 2016-04-06 James Greenhalgh <james.greenha...@arm.com> PR target/70133 * config/aarch64/aarch64-common.c (aarch64_option_extension): Keep

[Patch AArch64 0/3] Fix PR70133

AArch64 1/3] Enable CRC by default for armv8.1-a 2016-04-06 James Greenhalgh <james.greenha...@arm.com> * config/aarch64/aarch64.h (AARCH64_FL_FOR_ARCH8_1): Also add AARCH64_FL_CRC. [Patch AArch64 2/3] Rework the code to print extension strings (pr70133) gcc/ 2016-04-06

[Patch AArch64 1/3] Enable CRC by default for armv8.1-a

Hi, This change reflects binutils support for CRC, where it is always enabled for armv8.1-a. OK? Thanks, James --- 2016-04-06 James Greenhalgh <james.greenha...@arm.com> * config/aarch64/aarch64.h (AARCH64_FL_FOR_ARCH8_1): Also add AARCH64_FL_CRC. diff --git a/gcc/

Re: [AArch64] Add precision choices for the reciprocal square root approximation

On Fri, Apr 01, 2016 at 02:47:05PM +0100, Wilco Dijkstra wrote: > Evandro Menezes wrote: > > > > Ping^1 > > I haven't seen a newer version that incorporates my feedback. To recap what > I'd like to see is a more general way to select approximations based on mode. > I don't believe that looking at

Re: [PATCH, AArch64] Fix for PR67896 (C++ FE cannot distinguish __Poly{8,16,64,128}_t types)

On Mon, Jan 25, 2016 at 12:15:48PM +, James Greenhalgh wrote: > On Wed, Jan 20, 2016 at 09:27:41PM +0100, Roger Ferrer Ibáñez wrote: > > Hi James, > > > > > This patch looks technically correct to me, though there is a small > > > style issue to correct (in

Re: [Patch AArch64] Fix PR target/63874

On Thu, Mar 31, 2016 at 02:11:49PM +0100, Ramana Radhakrishnan wrote: > Hi, > > In this PR we have a situation where we aren't really detecting > weak references vs weak definitions. If one has a weak definition > that binds locally there's no reason not to put out PC relative >

[Patch ARM] Delete ASM_OUTPUT_DEF and fall back to default .set directive

and tested on an arm-none-linux-gnueabihf box with no issues. OK? Thanks, James --- 2016-03-31 James Greenhalgh <james.greenha...@arm.com> * config/arm/linux-elf.h (ASM_OUTPUT_DEF): Delete. --- [1]: https://gcc.gnu.org/ml/gcc-patches/2016-03/msg00018.html diff --git a/gcc/config

Re: [AArch64] Fix SIMD predicate

On Wed, Mar 30, 2016 at 11:18:27AM -0500, Evandro Menezes wrote: >Add scalar 0.0 to the aarch64_simd_reg_or_zero predicate. > >2016-03-30 Evandro Menezes > > * gcc/config/aarch64/predicates.md > (aarch64_simd_reg_or_zero predicate): Add the

Re: [AArch64] Emit square root using the Newton series

On Wed, Mar 16, 2016 at 02:45:37PM -0500, Evandro Menezes wrote: > On 03/08/16 16:08, Evandro Menezes wrote: > >On 02/16/16 14:56, Evandro Menezes wrote: > >>On 12/08/15 15:35, Evandro Menezes wrote: > >>>Emit square root using the Newton series > >>> > >>> 2015-12-03 Evandro Menezes

Re: [PATCH, aarch64] Fix 70048

On Wed, Mar 16, 2016 at 02:25:27PM -0700, Richard Henderson wrote: > PR target/70048 > * config/aarch64/aarch64.c (virt_or_elim_regno_p): New. > (aarch64_classify_address): Use it. > (aarch64_legitimize_address): Force all subexpressions of PLUS > into

Re: [PATCH] boehm-gc: add supprt for aarch64 ILP32

On Tue, Mar 15, 2016 at 03:46:00PM +0100, Andreas Schwab wrote: > * include/private/gcconfig.h [AARCH64] (ALIGNMENT, CPP_WORDSZ): > Define for __ILP32__. OK. Thanks, James > --- > boehm-gc/include/private/gcconfig.h | 9 +++-- > 1 file changed, 7 insertions(+), 2 deletions(-) >

Re: [PATCH] libffi: define FFI_SIZEOF_JAVA_RAW for aarch64 ILP32

On Tue, Mar 15, 2016 at 03:18:43PM +0100, Andreas Schwab wrote: > Like x32, aarch64 ILP32 needs to define FFI_SIZEOF_JAVA_RAW. This fixes > the java interpreter. Should this go through upstream libffi first? I can't remember the right order for these. Anyway, this is OK in whatever order is

Re: [PATCH, AArch64] atomics: prefetch the destination for write prior to ldxr/stxr loops

On Mon, Mar 07, 2016 at 10:54:25PM -0800, Andrew Pinski wrote: > On Mon, Mar 7, 2016 at 8:12 PM, Yangfei (Felix) wrote: > >> On Mon, Mar 7, 2016 at 7:27 PM, Yangfei (Felix) > >> wrote: > >> > Hi, > >> > > >> > As discussed in LKML: > >>

Re: [PATCH][AArch64] Fix gcc.target/aarch64/vect-reduc-or_1.c for -mcpu=cortex-a57

On Fri, Mar 11, 2016 at 03:19:54PM +, Kyrill Tkachov wrote: > Hi all, > > I've been seeing this test FAIL for a toolchain configured with > --with-cpu=cortex-a57 in the scan vectoriser dump check because the cost > model for -mtune=cortex-a57 decides not to vectorise. > > This patch disables

Re: [PATCH][AArch64] Replace insn to zero up DF register

On Thu, Mar 10, 2016 at 10:32:15AM -0600, Evandro Menezes wrote: > >I agree to postpone until GCC 7. > > > >[AArch64] Replace insn to zero up SIMD registers > > > >gcc/ > >* config/aarch64/aarch64.md > >(*movhf_aarch64): Add "movi %0, #0" to zero up

Re: [PATCH][AArch64] Fix thinko in handling of -momit-leaf-frame-pointer option

On Thu, Mar 10, 2016 at 03:42:38PM +, Kyrill Tkachov wrote: > Hi all, > > When extending the aarch64_handle_option function for GCC 6 I introduced a > thinko > when handling the -momit-leaf-frame-pointer option and had it set the variable > for -fomit-frame-pointer instead. This hasn't been

Re: RFA: PR 70044: Catch a second call to aarch64_override_options_after_change

On Mon, Mar 07, 2016 at 01:12:16PM +, Nick Clifton wrote: > Hi Kyrill, > > > This is missing a second hunk from the patch you attached in the PR that I > > think is necessary > > for this to work (setting to x_flag_omit_frame_pointer)... > > Doh! Silly me - there was a snafu restoring the

Re: [PATCH][AArch64] PR target/70002: Make aarch64_set_current_function play nice with pragma resetting

On Thu, Mar 03, 2016 at 11:38:11AM +, Kyrill Tkachov wrote: > Hi all, > > This patch fixes the ICE that was introduced by my earlier patch to > aarch64_set_current_function: > FAIL: gcc.dg/torture/pr52429.c -O2 -flto -fno-use-linker-plugin > -flto-partition=none (internal compiler error) >

Re: [AArch64] Disable pcrelative_literal_loads with fix-cortex-a53-843419

On Thu, Mar 10, 2016 at 01:37:50PM +0100, Christophe Lyon wrote: > On 10 March 2016 at 12:43, James Greenhalgh <james.greenha...@arm.com> wrote: > > On Tue, Jan 26, 2016 at 03:43:36PM +0100, Christophe Lyon wrote: > >> With the attachment > >> > >> &g

Re: [PATCH][AArch64] Replace insn to zero up DF register

On Wed, Mar 09, 2016 at 03:35:43PM -0600, Evandro Menezes wrote: > On 03/01/16 13:08, Evandro Menezes wrote: > >On 03/01/16 13:02, Wilco Dijkstra wrote: > >>Evandro Menezes wrote: > >>>The meaning of these attributes are not clear to me. Is there a > >>>reference somewhere about which insns are

Re: [AArch64] Disable pcrelative_literal_loads with fix-cortex-a53-843419

On Tue, Jan 26, 2016 at 03:43:36PM +0100, Christophe Lyon wrote: > With the attachment > > > On 26 January 2016 at 15:42, Christophe Lyon > wrote: > > Hi, > > > > This is a followup to PR63304. > > > > As discussed in bugzilla, this patch disables

Re: [AArch64] Fix dependency of gcc-plugin.h

On Tue, Mar 08, 2016 at 03:20:52PM +0100, Christophe Lyon wrote: > Hi, > > Our bug report https://bugs.linaro.org/show_bug.cgi?id=2123 > complains about aarch64's missing plugin dependency. > > IFAIT, the problem is present on trunk too, and the small attached > patch fixes it. > OK? This is

Re: [Patch testsuite] Change xfail conditions for bb-slp-34.c

On Wed, Mar 09, 2016 at 12:53:02PM +0100, Rainer Orth wrote: > Richard Biener <rguent...@suse.de> writes: > > > On Thu, 3 Mar 2016, James Greenhalgh wrote: > > > >> > >> Hi, > >> > >> ARM and AArch64 will still vectorize bb-slp-34.c

Re: [PATCH][AArch64][testsuite] PR target/70004: Remove check using undefined behaviour

On Fri, Mar 04, 2016 at 12:02:59PM +0100, Jakub Jelinek wrote: > On Fri, Mar 04, 2016 at 10:41:04AM +, Kyrill Tkachov wrote: > > Can do. I've moved the dodgy functions into their own separate compile test. > > The test passes. > > Ok? > > LGTM. OK from me too. James

[Patch testsuite] Change xfail conditions for bb-slp-34.c

-elf with no issues. OK? Thanks, James --- 2016-03-03 James Greenhalgh <james.greenha...@arm.com> * gcc.dg/vect/bb-slp-34.c: Don't XFAIL for ARM/AArch64. diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-34.c b/gcc/testsuite/gcc.dg/vect/bb-slp-34.c index 418f2b5..7b9511a 100644 ---

Re: [PATCH] Fix PR69951

On Tue, Mar 01, 2016 at 05:56:30PM +0100, Christophe Lyon wrote: > On 1 March 2016 at 10:51, James Greenhalgh <james.greenha...@arm.com> wrote: > > On Tue, Mar 01, 2016 at 10:21:27AM +0100, Richard Biener wrote: > >> On Mon, 29 Feb 2016, James Greenhalgh wrote: > >

Re: [PATCH 1/9] gensupport: Fix define_subst operand renumbering.

On Tue, Mar 01, 2016 at 01:35:18PM +0100, Andreas Krebbel wrote: > On 03/01/2016 01:15 PM, James Greenhalgh wrote: > > On Tue, Mar 01, 2016 at 10:29:28AM +0100, Andreas Krebbel wrote: > >> On 02/29/2016 02:36 PM, Bernd Schmidt wrote: > >>> On 02/29/2016 09:46 AM, An

Re: [PATCH 1/9] gensupport: Fix define_subst operand renumbering.

On Tue, Mar 01, 2016 at 10:29:28AM +0100, Andreas Krebbel wrote: > On 02/29/2016 02:36 PM, Bernd Schmidt wrote: > > On 02/29/2016 09:46 AM, Andreas Krebbel wrote: > >> Ok for mainline? > >> > >>* gensupport.c (process_substs_on_one_elem): Split loop to > >>complete

Re: [PATCH] Fix PR69951

On Tue, Mar 01, 2016 at 10:21:27AM +0100, Richard Biener wrote: > On Mon, 29 Feb 2016, James Greenhalgh wrote: > > > On Fri, Feb 26, 2016 at 09:32:53AM +0100, Richard Biener wrote: > > > > > > The following fixes PR69951, hopefully the last case of decl alias &g

Re: [PATCH] Fix PR69951

On Fri, Feb 26, 2016 at 09:32:53AM +0100, Richard Biener wrote: > > The following fixes PR69951, hopefully the last case of decl alias > issues with alias analysis. This time it's points-to and the DECL_UIDs > used in points-to sets not being canonicalized. > > The simplest (and cheapest) fix

Re: [PATCH 3/3] contrib/config-list.mk: Add aarch64-rtems and x86_64-rtems

On Thu, Feb 25, 2016 at 02:49:10PM -0600, Joel Sherrill wrote: > * contrib/config-list.mk: Add aarch64-rtems and x86_64-rtems The AArch64 part of this is OK. Thanks, James > --- > contrib/config-list.mk | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-)

Re: [PATCH 1/3] Add aarch64-*-rtems* target

On Thu, Feb 25, 2016 at 02:49:08PM -0600, Joel Sherrill wrote: > * gcc/config.gcc, libgcc/config.host: Add aarch64-*-rtems*. > * gcc/config/aarch64/rtems.h: New file. OK. Thanks, James > --- > gcc/config.gcc | 11 +-- > gcc/config/aarch64/rtems.h | 28

Re: [PATCH][AArch64] Set TREE_TARGET_GLOBALS in aarch64_set_current_function when new tree is the default node to recalculate optab availability

On Thu, Feb 25, 2016 at 11:04:21AM +, Kyrill Tkachov wrote: > Hi all, > > Seems like aarch64 is suffering from something similar to PR 69245 as well. > If a target pragma sets the target state to the same as the > target_option_default_node the node is just a pointer to >

Re: [PATCH][AArch64] PR target/69613: Return zero TARGET_SHIFT_TRUNCATION_MASK when SHIFT_COUNT_TRUNCATED is false

On Thu, Feb 25, 2016 at 09:25:45AM +, Kyrill Tkachov wrote: > Hi all, > > In this wrong-code PR we get bad code when synthesising a TImode right shift > by variable amount using DImode shifts during expand. > > The expand_double_word_shift function expands two paths: one where the > variable

Re: [PATCH][AArch64] Remove an unused reload hook.

On Thu, Feb 25, 2016 at 12:00:58PM +0100, Yvan Roux wrote: > Hi, > > On 26 January 2015 at 18:01, Matthew Wahab wrote: > > Hello, > > > > The LEGITIMIZE_RELOAD_ADDRESS macro is only needed for reload. Since the > > Aarch64 backend no longer supports reload, this macro is

Re: [AArch64] Emit square root using the Newton series

On Mon, Feb 22, 2016 at 06:50:44PM -0600, Evandro Menezes wrote: > In preparation for the patch adding the Newton series also for > square root, I'd like to propose this patch changing the name of the > existing tuning flag for the reciprocal square root. This is fine, other names like sw_rsqrt,

Re: [PATCH 1/2][AArch64] Implement AAPCS64 updates for alignment attribute

On Mon, Feb 22, 2016 at 03:07:09PM +, Alan Lawrence wrote: > On 22/01/16 17:16, Alan Lawrence wrote: > > > >On 21/01/16 17:23, Alan Lawrence wrote: > >>On 18/01/16 17:10, Eric Botcazou wrote: > >>> > >>>Could you post the list of files that differ? How do they differ exactly? > >> > >>Hmmm.

Re: [PATCH][AArch64][v2] Skip gcc.target/aarch64/assembler_arch_1.c if assembler does not support it

On Thu, Feb 18, 2016 at 11:31:02AM +0100, Christophe Lyon wrote: > On 17 February 2016 at 17:06, Kyrill Tkachov > wrote: > > Hi all, > > > > I've thought about this check a bit more and I think we can compactly > > auto-generate checks > > for any aarch64 architecture

Re: [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning

On Mon, Feb 15, 2016 at 11:24:53AM -0600, Evandro Menezes wrote: > On 02/15/16 04:50, James Greenhalgh wrote: > >On Mon, Feb 08, 2016 at 10:57:10AM +0000, James Greenhalgh wrote: > >>On Mon, Feb 01, 2016 at 02:00:01PM +, James Greenhalgh wrote: > >>>On Mon, Ja

Re: [PATCH][AArch64] Skip gcc.target/aarch64/assembler_arch_1.c if assembler does not support it

On Tue, Feb 16, 2016 at 09:27:00AM +, Kyrill Tkachov wrote: > Hi all, > > As Christophe reported at: > https://gcc.gnu.org/ml/gcc-patches/2016-02/msg00784.html > > The test gcc.target/aarch64/assembler_arch_1.c fails to assemble on older > assemblers that don't support the LSE architecture

Re: add check for aarch64 in check_effective_target_section_anchors()

On Thu, Feb 11, 2016 at 11:03:23PM +0530, Prathamesh Kulkarni wrote: > Hi, > aarch64 supports section anchors but it appears > check_effective_target_section_anchors() doesn't contain entry for it. > This patch adds for entry for aarch64. > OK for trunk ? OK. I presume you tested this, and the

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

On Thu, Jan 21, 2016 at 04:55:40PM -0600, Evandro Menezes wrote: > > Got it. > > Let me try this again: > >Add support for the FCCMP insn types > >2016-01-21 Evandro Menezes > >gcc/ > * config/aarch64/aarch64.md (fccmp): Change insn type. >

Re: [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning

On Mon, Feb 08, 2016 at 10:57:10AM +, James Greenhalgh wrote: > On Mon, Feb 01, 2016 at 02:00:01PM +0000, James Greenhalgh wrote: > > On Mon, Jan 25, 2016 at 11:20:46AM +0000, James Greenhalgh wrote: > > > On Mon, Jan 11, 2016 at 12:04:43PM +, James Greenhalgh wrote: &

Re: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS

On Mon, Feb 08, 2016 at 12:52:00PM +, James Greenhalgh wrote: > On Tue, Jan 26, 2016 at 04:04:47PM +0000, James Greenhalgh wrote: > > > > Hi, > > > > In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction > > available when compiling with

Re: [Patch AArch64] GCC 6 regression in vector performance. - Fix vector initialization to happen with lane load instructions.

On Mon, Feb 08, 2016 at 10:56:29AM +, James Greenhalgh wrote: > On Tue, Feb 02, 2016 at 10:29:29AM +0000, James Greenhalgh wrote: > > On Wed, Jan 20, 2016 at 03:22:11PM +0000, James Greenhalgh wrote: > > > > > > Hi, > > > > > > In a number of c

Re: [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt

On Mon, Feb 08, 2016 at 10:57:44AM +, James Greenhalgh wrote: > On Mon, Feb 01, 2016 at 01:59:34PM +0000, James Greenhalgh wrote: > > On Mon, Jan 25, 2016 at 11:21:25AM +0000, James Greenhalgh wrote: > > > On Mon, Jan 11, 2016 at 11:53:39AM +, James Greenhalgh wrote: &

Re: [PATCH] Fix PR69771, bogus CONST_INT during shift expansion

On Fri, Feb 12, 2016 at 05:34:21PM +0100, Jakub Jelinek wrote: > On Fri, Feb 12, 2016 at 03:20:07PM +0100, Bernd Schmidt wrote: > > >>- mode1 = GET_MODE (xop1) != VOIDmode ? GET_MODE (xop1) : mode; > > >>+ mode1 = GET_MODE (xop1) != VOIDmode ? GET_MODE (xop1) : mode1; > > >>if (xmode1 !=

Re: [PATCH][AArch64] Only update assembler .arch directive when necessary

On Thu, Feb 11, 2016 at 01:10:33PM +, Kyrill Tkachov wrote: > >>>Why not just keep the last string you printed, and use a string compare > >>>to decide whether to print or not? Sure we'll end up doing a bit more > >>>work, but the logic becomes simpler to follow and we don't need to pass >

Re: [PATCH][AArch64] Only update assembler .arch directive when necessary

On Wed, Feb 10, 2016 at 10:32:16AM +, Kyrill Tkachov wrote: > Hi James, > > On 10/02/16 10:11, James Greenhalgh wrote: > >On Thu, Feb 04, 2016 at 01:50:31PM +, Kyrill Tkachov wrote: > >>Hi all, > >> > >>As part of the target attribut

Re: [PATCH][AArch64] Only update assembler .arch directive when necessary

On Thu, Feb 04, 2016 at 01:50:31PM +, Kyrill Tkachov wrote: > Hi all, > > As part of the target attributes and pragmas support for GCC 6 I changed the > aarch64 port to emit a .arch assembly directive for each function that > describes the architectural features used by that function. This

Re: [Patch] Gate vect-mask-store-move-1.c correctly, and actually output the dump

On Mon, Feb 08, 2016 at 03:24:14PM +0100, Richard Biener wrote: > On Mon, Feb 8, 2016 at 2:40 PM, James Greenhalgh > <james.greenha...@arm.com> wrote: > > On Mon, Feb 08, 2016 at 04:29:31PM +0300, Yuri Rumyantsev wrote: > >> Hi James, > >> > >> Tha

Re: [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning

On Mon, Feb 01, 2016 at 02:00:01PM +, James Greenhalgh wrote: > On Mon, Jan 25, 2016 at 11:20:46AM +0000, James Greenhalgh wrote: > > On Mon, Jan 11, 2016 at 12:04:43PM +0000, James Greenhalgh wrote: > > > > > > Hi, > > > > > > I've see

Re: [Patch AArch64] GCC 6 regression in vector performance. - Fix vector initialization to happen with lane load instructions.

On Tue, Feb 02, 2016 at 10:29:29AM +, James Greenhalgh wrote: > On Wed, Jan 20, 2016 at 03:22:11PM +0000, James Greenhalgh wrote: > > > > Hi, > > > > In a number of cases where we try to create vectors we end up spilling to > > the > > stack and then

Re: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS

On Tue, Jan 26, 2016 at 04:04:47PM +, James Greenhalgh wrote: > > Hi, > > In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction > available when compiling with -march=armv8.1-a are only usable with > a register number in the range 0 to 15 for operand 3,

Re: [Patch] Gate vect-mask-store-move-1.c correctly, and actually output the dump

https://gcc.gnu.org/ml/gcc-testresults/2016-02/msg00824.html Thanks, James > > gcc/testsuite/ChangeLog: > > * gcc.dg/vect/vect-mask-store-move-1.c: Gate dump with x86 target. > > 2016-02-08 16:07 GMT+03:00 James Greenhalgh <james.greenha...@arm.com>: > > > > Hi,

[Patch] Gate vect-mask-store-move-1.c correctly, and actually output the dump

/native) and x86 with no issues. OK? Thanks, James --- 2016-02-08 James Greenhalgh <james.greenha...@arm.com> * gcc.dg/vect/vect-mask-store-move-1.c: Add dump option, and gate check on x86_64/i?86. diff --git a/gcc/testsuite/gcc.dg/vect/vect-mask-store-move-1.c b/gcc/tes

Re: [PATCH AArch64]Force register scaling out of mem ref and comment why

On Thu, Feb 04, 2016 at 10:11:53AM +, Bin Cheng wrote: > Hi, > There is a performance regression caused by my previous change to > aarch64_legitimize_address, in which I forced constant offset out of memory > ref if the address expr is in the form of "reg1 + reg2 << scale + const". > The

Re: [PATCH][AArch64] PR target/69161: Don't use special predicate for CCmode comparisons in expressions that require matching modes

On Fri, Jan 29, 2016 at 02:27:34PM +, Kyrill Tkachov wrote: > Hi all, > > In this PR we ICE during combine when trying to propagate a comparison into a > vec_duplicate, > that is we end up creating the rtx: > (vec_duplicate:V4SI (eq:CC_NZ (reg:CC_NZ 66 cc) > (const_int 0 [0]))) > >

Re: [PATCH] Fix jit crash on aarch64, mips

On Thu, Feb 04, 2016 at 10:31:27AM -0500, David Malcolm wrote: > The jit testsuite was showing numerous segfaults and fatal > errors for trunk on aarch64; typically on the 2nd iteration of each > test, with errors like: > test-volatile.c.exe: fatal error: pass ‘rnreg’ not found but is referenced

Re: [PATCH 4/4][AArch64] Cost CCMP instruction sequences to choose better expand order

On Thu, Jan 28, 2016 at 02:33:20PM +, James Greenhalgh wrote: > On Mon, Jan 25, 2016 at 08:09:39PM +, Wilco Dijkstra wrote: > > Andreas Schwab <sch...@linux-m68k.org> wrote: > > > > > FAIL: gcc.target/aarch64/ccmp_1.c scan-assembler-times \tcmp\tw[0-9]+, 0 4

Re: [aarch64] Improve TImode constant moves

On Sun, Jan 24, 2016 at 02:54:32AM -0800, Richard Henderson wrote: > This looks to be an incomplete transition of the aarch64 backend to > CONST_WIDE_INT. I haven't checked to see if it's a regression from > gcc5, but I suspect not, since there should have been similar checks > for CONST_DOUBLE.

Re: [Patch AArch64] GCC 6 regression in vector performance. - Fix vector initialization to happen with lane load instructions.

On Wed, Jan 20, 2016 at 03:22:11PM +, James Greenhalgh wrote: > > Hi, > > In a number of cases where we try to create vectors we end up spilling to the > stack and then filling. This is one example distilled from a couple of > micro-benchmrks where the issue sh

Re: [PATCH][AArch64] Add TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS

above is applied. Thanks, James > James Greenhalgh wrote: > > On Wed, Dec 16, 2015 at 01:05:21PM +, Wilco Dijkstra wrote: > > > James Greenhalgh wrote: > > > > On Tue, Dec 15, 2015 at 10:54:49AM +, Wilco Dijkstra wrote: > > > > > ping > > >

Re: [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt

On Mon, Jan 25, 2016 at 11:21:25AM +, James Greenhalgh wrote: > On Mon, Jan 11, 2016 at 11:53:39AM +0000, James Greenhalgh wrote: > > > > Hi, > > > > I'd like to switch the logic around in aarch64.c such that > > -mlow-precision-recip-sqrt causes us

Re: [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning

On Mon, Jan 25, 2016 at 11:20:46AM +, James Greenhalgh wrote: > On Mon, Jan 11, 2016 at 12:04:43PM +0000, James Greenhalgh wrote: > > > > Hi, > > > > I've seen a couple of large performance issues caused by expanding > > the high-precision reciprocal square

Re: [PATCH 4/4][AArch64] Cost CCMP instruction sequences to choose better expand order

On Mon, Jan 25, 2016 at 08:09:39PM +, Wilco Dijkstra wrote: > Andreas Schwab wrote: > > > FAIL: gcc.target/aarch64/ccmp_1.c scan-assembler-times \tcmp\tw[0-9]+, 0 4 > > FAIL: gcc.target/aarch64/ccmp_1.c scan-assembler adds\t > > FAIL: gcc.target/aarch64/ccmp_1.c

Re: [PATCH, aarch64] Fix pr69305 -- addti miscompilation

On Sun, Jan 24, 2016 at 03:19:35AM -0800, Richard Henderson wrote: > As Jakub notes in the PR, the representation for add_compare and > sub_compare were wrong. And several of the add_carryin patterns > were duplicates. > > This adds a CC_Cmode for which only the Carry bit is valid. > > The

Re: [PATCH][AArch64] Add vector permute cost

On Tue, Dec 15, 2015 at 11:35:45AM +, Wilco Dijkstra wrote: > > Add support for vector permute cost since various permutes can expand into a > complex > sequence of instructions. This fixes major performance regressions due to > recent changes > in the SLP vectorizer (which now vectorizes

[Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS

-- `sqrdmlsh v2.4h,v4.4h,v23.h[5]' This patch teaches GCC to avoid registers outside of this range when appropriate, in the same fashion as we do for other instructions with this limitation. Tested on an internal testsuite targeting Neon intrinsics. OK? Thanks, James --- 2016-01-25 James Greenhalgh

Re: [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning

On Mon, Jan 11, 2016 at 12:04:43PM +, James Greenhalgh wrote: > > Hi, > > I've seen a couple of large performance issues caused by expanding > the high-precision reciprocal square root for Cortex-A57, so I'd like > to turn it off by default. > > This is good for art

Re: [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt

On Mon, Jan 11, 2016 at 11:53:39AM +, James Greenhalgh wrote: > > Hi, > > I'd like to switch the logic around in aarch64.c such that > -mlow-precision-recip-sqrt causes us to always emit the low-precision > software expansion for reciprocal square root. I have two reasons t

Re: [AARCH64][ACLE][NEON] Implement vcvt*_s64_f64 and vcvt*_u64_f64 NEON intrinsics.

On Thu, Jan 21, 2016 at 12:32:07PM +, James Greenhalgh wrote: > On Wed, Jan 13, 2016 at 05:44:30PM +, Bilyan Borisov wrote: > > This patch implements all the vcvtR_s64_f64 and vcvtR_u64_f64 vector > > intrinsics, where R is ['',a,m,n,p]. Since these intrinsics ar

Re: [PATCH, AArch64] Fix for PR67896 (C++ FE cannot distinguish __Poly{8,16,64,128}_t types)

On Wed, Jan 20, 2016 at 09:27:41PM +0100, Roger Ferrer Ibáñez wrote: > Hi James, > > > This patch looks technically correct to me, though there is a small > > style issue to correct (in-line below), and your ChangeLogs don't fit > > our usual style. > > thank you very much for the useful

[Patch Obvious] gcc.dg/vect/bb-slp-pr68892.c requires vectorization of doubles

Hi, As title. This testcase fails on arm-none-linux-gnueabihf, because we don't have vectorization of doubles there. Committed as obvious as revision 232731. Thanks, James --- 2016-01-22 James Greenhalgh <james.greenha...@arm.com> * gcc.dg/vect/bb-slp-pr68892.c: Require vect_

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

On Thu, Jan 21, 2016 at 11:13:29AM +, Wilco Dijkstra wrote: > James Greenhalgh <james.greenha...@arm.com> wrote: > > If we don't have any targets which care about the fccmps/fccmpd split in > > the code base, do we really need it? Can we just follow the example of >

Re: [AARCH64][ACLE][NEON] Implement vcvt*_s64_f64 and vcvt*_u64_f64 NEON intrinsics.

On Wed, Jan 13, 2016 at 05:44:30PM +, Bilyan Borisov wrote: > This patch implements all the vcvtR_s64_f64 and vcvtR_u64_f64 vector > intrinsics, where R is ['',a,m,n,p]. Since these intrinsics are > identical in semantics to the corresponding scalar variants, they are > implemented in terms of

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote: > Hi, Wilco. > > On 01/06/2016 06:04 AM, Wilco Dijkstra wrote: > >>Here's what I had in mind when I inquired about distinguishing FCMP from > >>FCCMP. As you can see in the patch, Exynos is the only target that > >>cares about it,

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

On Thu, Jan 21, 2016 at 01:58:31PM -0600, Evandro Menezes wrote: > Hi, James. > > On 01/21/16 03:24, James Greenhalgh wrote: > >On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote: > >>On 01/06/2016 06:04 AM, Wilco Dijkstra wrote: > >>>>Here's w

[Patch AArch64] GCC 6 regression in vector performance. - Fix vector initialization to happen with lane load instructions.

of benchmarks to show no regressions on Cortex-A57 or Cortex-A53. The patch fixes some regressions caused by the more agressive vectorization in GCC6, so I'd like to propose it to go in even though we are in Stage 4. OK? Thanks, James --- gcc/ 2016-01-20 James Greenhalgh <james.greenha...@arm.

Re: [PATCH, AArch64] Fix for PR67896 (C++ FE cannot distinguish __Poly{8,16,64,128}_t types)

On Tue, Jan 19, 2016 at 06:28:18AM +0100, Roger Ferrer Ibáñez wrote: > Hi, > > aarch64-builtins.c defines several SIMD builtin types. Among these > SIMD types there are the polynomials __Poly{8,16,64,128}_t. These are > built by a call to build_distinct_type_copy >

Re: [PATCH][AArch64] Handle compare of zero_extract form of TST-immediate in rtx costs

On Mon, Jan 11, 2016 at 04:41:22PM +, Kyrill Tkachov wrote: > Hi all, > > The test gcc.target/aarch64/tst_3.c fails for an explicit -mcpu=cortex-a53 > because we don't handle the recent compare with zero_extract pattern properly > in rtx costs, so we end up recursing into its operands and end

Re: [PATCH][AArch64] Handle CSEL of zero_extended operands in rtx costs

On Mon, Jan 11, 2016 at 04:41:32PM +, Kyrill Tkachov wrote: > Hi all, > > This patch fixes the test gcc.target/aarch64/pr66776.c for -mcpu=cortex-a53. > Currently we don't handle the (if_then_else (cond) (zero_extend r1) > (zero_extend r2)) > form of CSEL, so we end up recursing into the

Re: [PATCH][AArch64] Properly reject invalid attribute strings

On Fri, Jan 15, 2016 at 01:39:54PM +, Kyrill Tkachov wrote: > Hi all, > > A bug in the target attribute parsing logic led to us silently accepting > attribute strings that did not appear in the attributes table i.e invalid > attributes. > > This patch fixes that oversight so we now error out

Re: [AArch64] Remove TODO (redundant type conversions) in arm_neon.h

On Mon, Jan 11, 2016 at 11:56:50AM +, Jiong Wang wrote: > There are quite a few redundant type conversions in arm_neon.h, all of > them are intrinsics taking argument of vector float type and return result > of vector unsigned integer type. > > The problem is currently we support UNOP and

Re: [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt

On Mon, Jan 11, 2016 at 04:57:56PM -0600, Evandro Menezes wrote: > On 01/11/2016 05:53 AM, James Greenhalgh wrote: > >I'd like to switch the logic around in aarch64.c such that > >-mlow-precision-recip-sqrt causes us to always emit the low-precision > >software expansion for r

Re: [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt

On Tue, Jan 12, 2016 at 05:53:21AM +, Kumar, Venkataramanan wrote: > Hi James, > > > -Original Message- > > From: James Greenhalgh [mailto:james.greenha...@arm.com] > > Sent: Monday, January 11, 2016 5:24 PM > > To: gcc-patches@gcc.gnu.org >

Re: [PATCH] Be less conservative in process_{output,input}_constraints (PR target/65689)

On Wed, Apr 08, 2015 at 11:00:59PM +0200, Jakub Jelinek wrote: > Hi! > > Right now, stmt.c on constraints not hardcoded in it, and not > define_{register,address,memory}_constraint just assumes the > constraint might allow both reg and mem. Unfortunately, on some > constraints which clearly

[Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt

precision sequences. I've also put this through bootstrap and test on aarch64-none-linux-gnu with no issues. OK? Thanks, James --- 2015-12-10 James Greenhalgh <james.greenha...@arm.com> * config/aarch64/aarch64.c (use_rsqrt_p): Always use software reciprocal sqrt for

[AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning

good (>10%) for some private microbenchmark kernels which stress the divide/sqrt/multiply units. It therefore seems to me to be the correct choice to make across a number of workloads. Bootstrapped and tested on aarch64-none-linux-gnu with no issues. OK? Thanks, James --- 2015-12-11 Ja

Re: Backport: [Patch AArch64] Reinstate CANNOT_CHANGE_MODE_CLASS to fix pr67609

On Fri, Dec 18, 2015 at 12:13:31PM +, James Greenhalgh wrote: > > On Mon, Dec 14, 2015 at 11:49:26AM +, Marcus Shawcroft wrote: > > On 14 December 2015 at 11:01, James Greenhalgh <james.greenha...@arm.com> > > wrote: > > > On Wed, Dec 09, 2015 at 01:13:2

Re: [PATCH][AArch64] PR rtl-optimization/68796: Add patterns for QImode and HImode comparison with zero

On Thu, Jan 07, 2016 at 03:39:42PM +, Kyrill Tkachov wrote: > Hi all, > > This is an aarch64-specific approach to fixing the issue I raised in the > thread at: > https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01779.html > > The guidance there was to define aarch64 patterns for comparing

[Patch testsuite] Skip gcc.dg/ifcvt-4.c for targets on which it may not work

trigger this for particular tuning targets. This patch skips the test on those targets. OK? Thanks, James --- 2015-12-17 James Greenhalgh <james.greenha...@arm.com> PR testsuite/68232 * gcc.dg/ifcvt-4.c: Skip for arm*-*-* and powerpc64le*-*-*. --2

Backport: [Patch AArch64] Reinstate CANNOT_CHANGE_MODE_CLASS to fix pr67609

On Mon, Dec 14, 2015 at 11:49:26AM +, Marcus Shawcroft wrote: > On 14 December 2015 at 11:01, James Greenhalgh <james.greenha...@arm.com> > wrote: > > On Wed, Dec 09, 2015 at 01:13:20PM +, Marcus Shawcroft wrote: > >> On 27 November 2015 at 13:01, Jame

[Patch ifcvt] Add a new parameter to limit if-conversion

James Greenhalgh <james.greenha...@arm.com> PR rtl-optimization/68920 * params.def (PARAM_MAX_RTL_IF_CONVERSION_INSNS): New. * ifcvt.c (noce_find_if_block): Limit by new param. * doc/invoke.texi (max-rtl-if-conversion-insns): Document it. gcc/testsuite/ 2015

Re: [Patch ifcvt] Add a new parameter to limit if-conversion

ession. I don't have a preference as to which direction we take this. I saw a similar performance boost for your testcase on my development box with my patch - so at least we now have two candidate patches to fix the performance regression. Thanks, James > > 2015-12-18 16:52 GMT+03:00 Jam

Re: [PATCH][AArch64][1/2] PR rtl-optimization/68796 Add compare-of-zero_extract pattern

On Thu, Dec 17, 2015 at 03:36:40PM +, Kyrill Tkachov wrote: > 2015-12-17 Kyrylo Tkachov > > PR rtl-optimization/68796 > * config/aarch64/aarch64.md (*and3nr_compare0_zextract): > New pattern. > * config/aarch64/aarch64.c (aarch64_select_cc_mode):

Re: [PATCH][AArch64] Properly cost zero_extend+ashift forms of ubfi[xz]

On Fri, Dec 04, 2015 at 09:30:45AM +, Kyrill Tkachov wrote: > Hi all, > > We don't handle properly the patterns for the [us]bfiz and [us]bfx > instructions when they > have an extend+ashift form. For example, the > *_ashl pattern. > This leads to rtx costs recuring into the extend and

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