This is a patch primarily from Shreya, though I think she cribbed some
code from Philipp that we had internally within Ventana and I made some
minor adjustments as well.
So the basic idea here is similar to her work on logical ops --
specifically when we can generate more efficient code at exp
926248780bb344327a15485
Author: Jeff Law
Date: Mon Aug 11 08:13:51 2025 -0600
Don't run tests requiring "B" on designs without "B"
So I resurrected our milkv pioneer over the weekend. While we had the
tell-tale signs of PCIE switch issues, it actually
On 8/10/25 3:24 PM, Andrew Pinski wrote:
On Fri, Feb 23, 2024 at 12:33 AM Jeff Law wrote:
On 2/23/24 01:05, Richard Biener wrote:
The following deprecates ia64*-*-* for GCC 14. Since we plan to
force LRA for GCC 15 and the target only has slim chances of getting
updated this notifies
On 7/27/25 2:50 PM, Aleksandar Rakic wrote:
From: Aleksandar Rakic
There are no platforms nor simulators for MSA and microMIPS R5 so
turning off this support for now.
gcc/ChangeLog:
* config/mips/mips.cc (mips_option_override): Error out for
-mmicromips -mmsa for MIPSr5 and
On 7/27/25 2:49 PM, Aleksandar Rakic wrote:
I tried to use just "TARGET_MICROMIPS" instead of "is_micromips", but
the compiler optimized "TARGET_MICROMIPS" away for some reason and
encoded it as "false".
That sounds like it's worth debugging; in general a TARGET_XXX macro
shouldn't have a con
On 7/27/25 11:00 AM, Aleksandar Rakic wrote:
Public
Hi,
I was going to apply this patch as it seems reasonable and independent
of everything else. But unfortunately it appears that you have munged
tabs into spaces.
While we could potentially use "-l" to ignore that problem and allow the
p
On 7/27/25 3:35 AM, Artemiy Volkov wrote:
From: Artemiy Volkov
Consider the following (RISC-V) instruction pair:
mul s6,a1,a2
add s6,a4,s6
Without this patch, while handling the second instruction, (a) the
existing chain for s6 will first be closed (upon the terminate_write
action for the
On 7/27/25 3:35 AM, Artemiy Volkov wrote:
From: Artemiy Volkov
Some of the instruction pairs recognized as fusible by a preceding
invocation of the dep_fusion pass require that both components of a pair
have the same hard register output for the fusion to work in hardware.
(An example of thi
On 8/6/25 8:29 AM, pan2...@intel.com wrote:
From: Pan Li
The previous cost value for vec_duplicate almost bases on the operators
like add/minus. The rtx_cost function try to match them case by case
and find if it has vec_duplicate, then update the cost values.
It is Ok when we initially ad
On 8/7/25 8:55 PM, Andrew Pinski wrote:
We increased the switch conversion array decl alignment
for better mergeability but it turns out that we increase
the alignment on targets which don't support mergeable sections
(e.g. NVPTX). Also after the fix for PR 121394, it becomes
obvious that we c
On 8/7/25 8:55 PM, Andrew Pinski wrote:
Now there are mergeable sections which have an entity size, we can place
decls (constants) that are smaller in size in these sections.
An example is an `long double` which has a size of 12 bytes on i686 and is
placed in the 16 bytes shareable section.
F
On 7/30/25 3:29 PM, Joseph Myers wrote:
On Tue, 15 Jul 2025, Ijaz, Abdul B wrote:
config/ChangeLog:
* lib-link.m4: Handle dash in the library name for
AC_LIB_LINKFLAGS_BODY.
OK.
THanks. I kept meaning to look at this older patch, but never found the
time.
I've pushed i
On 8/4/25 3:09 AM, Robin Dapp wrote:
Hi,
In PR121334 we are asked to expand a const_vector of size 4 with
poly_int elements. It has 2 elts per pattern so is neither a
const_vector_duplicate nor a const_vector_stepped.
We don't allow this kind of constant in legitimate_constant_p but expr
ap
On 8/8/25 3:31 AM, Richard Sandiford wrote:
In g:965564eafb721f813a3112f1bba8d8fae32b I'd added code
to try distributing non-widening subregs through logic ops,
in cases where that would eliminate a term of the logic op.
For "reasons", this indirectly caused combine to generate:
(set
On 7/28/25 2:40 AM, Anton Blanchard wrote:
The crypto type covers scalar (not vector) crypto instructions, and vclz
and vctz appear in two places.
gcc/ChangeLog:
* config/riscv/generic-vector-ooo.md (vec_crypto): Remove crypto,
vclz, vctz from insn reservation, rename to vec_
So just an FYI. My entire testing infrastructure system lost its mind
over the last week or so. Initially it was just failing to record
testresults, then is stopped running jobs.
No idea why Jenkins lost its mind -- it's running inside a docker
container and shouldn't have had anything ch
On 7/30/25 6:07 PM, KuanLin Chen wrote:
Please find:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release
These instructions are from "3.1.26. NDS.FFB" to "3.1.29. NDS.FLMISM"
in AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf.
Thanks, definitely helpful to see what those
On 7/31/25 2:35 AM, Kito Cheng wrote:
Previously, arch-canonicalize used hardcoded data to handle IMPLIED_EXT.
But this data often got out of sync with the actual C++ implementation.
Earlier, we introduced riscv-ext.def to keep track of all extension info
and generate docs. Now, arch-canonical
On 8/3/25 8:19 PM, Li, Pan2 wrote:
Thanks Jeff.
OK. Any change we could get run test for this in addition to the scanners?
I tried to add run test target this but seems happen to work here for mulhsu.
Here we only cares the result(high bits of mul) has values or not, looks like
mulhsu wi
On 7/30/25 11:22 PM, pan2...@intel.com wrote:
From: Pan Li
The previous code-gen of scalar unsigned SAT_MUL, aka usmul.
Leverage the mulhs by mistake, it should be mulhu for the
hight bit result of mul. Thus, this patch would like to make
it correct.
gcc/ChangeLog:
* config/riscv/
On 7/29/25 7:41 PM, KuanLin Chen wrote:
+
+;;
+;;
+;;
+;;String Extension
+;;
+;;
+;;
+
+(define_insn "riscv_nds_ffb"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (unspec:GPR [(match_operand:GPR 1 "reg_or_0_operand" "rJ")
+
On 7/28/25 3:38 AM, Konstantinos Eleftheriou wrote:
When having multiple stores with the same offset as the load, in the
case that we are eliminating the load, we were generating a mov instruction
for both of them, leading to the overwrite of the register containing the
loaded value.
This pat
On 7/29/25 7:41 AM, Richard Sandiford wrote:
This patch adds a new rule for distributing lowpart subregs through
ANDs, IORs, and XORs with a constant, in cases where one of the terms
then disappears. For example:
(lowart-subreg:QI (and:HI x 0x100))
simplifies to zero and
(lowart-subr
On 7/28/25 5:00 AM, Konstantinos Eleftheriou wrote:
While scanning the instructions and upon reaching an instruction that
doesn't satisfy the constraints that we have set, we were removing the
already detected stores, but we were continuing adding stores from that
point onward. This was causin
On 7/28/25 9:39 AM, Christoph Müllner wrote:
Function riscv_ext_is_subset () uses structured bindings to iterate over
all keys and values of an unordered map. However, this is only
available since C++17 and causes a warning like this:
warning: structured bindings only available with ‘-std=
On 7/28/25 3:23 AM, Robin Dapp wrote:
-;; Vector crypto, assumed to be a generic operation for now.
-(define_insn_reservation "vec_crypto" 4
+;; Vector population count
+(define_insn_reservation "vec_pop" 4
(and (eq_attr "tune" "generic_ooo,generic")
- (eq_attr "type" "crypto,vclz,vct
On 7/27/25 3:35 AM, Artemiy Volkov wrote:
Hi all,
This small patch series is intended to address a shortcoming of the
scheduler, which currently only identifies and preserves fusible
instruction pairs (according to the value of the
TARGET_SCHED_MACRO_FUSION_PAIR_P hook) that are already conse
On 11/7/24 10:36 AM, Robin Dapp wrote:
I think it'd be better if I abstain from this. I probably disagree too
much with the current structure and the way that the code is developing.
I won't object if anyone else approves it though.
It's not that I'm happy with the current state either and
On 7/22/25 4:19 AM, Konstantinos Eleftheriou wrote:
While scanning the instructions and upon reaching an instruction that
doesn't satisfy the constraints that we have set, we were removing the
already detected stores, but we were continuing adding stores from that
point onward. This was causin
On 7/23/25 5:41 AM, Aleksandar Rakic wrote:
Public
Hi,
Could you please let us know if you have any comments
on this patch?
Kind regards,
Aleksandar Rakic
From: Aleksandar Rakic
Sent: Monday, March 17, 2025 2:23 PM
To: gcc-patches@gcc.gnu.org
Cc: D
On 6/12/25 11:03 AM, Alfie Richards wrote:
Adds some aarch64 C fmv diagnostic tests.
This mostly tests C front end code, but has to be target specific at FMV
is requires specifying target extensions.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/mv-and-mvc-error1.c: New test.
On 6/12/25 11:03 AM, Alfie Richards wrote:
This patch removes the warning for target_version and target_clones in aarch64
as it is now spec compliant.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_process_target_version_attr):
Remove warning.
* config/aarch64/aa
On 6/12/25 11:03 AM, Alfie Richards wrote:
Add tests covering many FMV errors for Aarch64, including
redeclaration, and mixing target_clones and target_versions.
gcc/testsuite/ChangeLog:
* g++.target/aarch64/mv-and-mvc-error1.C: New test.
* g++.target/aarch64/mv-and-mvc-error
On 6/12/25 11:00 AM, Alfie Richards wrote:
This patch changes the semantics of target_version and target_clones attributes
to match the behavior described in the Arm C Language extension.
The changes to behavior are:
- The scope and signature of an FMV function set is now that of the default
On 6/12/25 10:53 AM, Alfie Richards wrote:
This patch is an overhaul of how FMV name mangling works. Previously
mangling logic was duplicated in several places across both target
specific and independent code. This patch changes this such that all
mangling is done in targetm.mangle_decl_assemb
On 7/24/25 1:53 AM, Andreas Schwab wrote:
From: Alexey Merzlyakov
Fixes incorrect SP-addresses used in CFA notes for the stack probes
unrelative to the frame's top. It applied to the RISC-V targets code
generation when the stack-clash protection is enabled.
PR target/120714
gcc/Chan
On 7/22/25 11:06 PM, pan2...@intel.com wrote:
From: Pan Li
The RVV fixed point insn VX combine should focus on the insn itself,
instead of any standard name like avg_floor, the vxrm should be
the value of insn as is.
The below test suites are passed for this patch series.
* The rv64gcv full
On 7/22/25 3:03 AM, Robin Dapp wrote:
Hi,
During the last weeks it became clear that our current broadcast
handling needs an overhaul in order to improve maintainability.
PR121073 showed that my intermediate fix wasn't enough and caused
regressions.
This patch now goes a first step towards u
On 7/20/25 6:54 PM, Sam James wrote:
This is vanilla zlib-1.3.1 imported over the existing zlib/ dir with:
* README adjusted to add the GCC note at the top;
* GCC's ChangeLog merged with the upstream one, as before;
* Deleted upstream Makefile as has been done before (we use an autoconf-
ge
On 7/22/25 3:04 AM, Robin Dapp wrote:
Hi,
This patch fixes the vf_vfmacc-run-1-f16.c test failures on rv32
by adding zvfh requirements as well as options to the test and
the target harness.
Regtested on rv64gcv_zvl512b and rv32gcv_zvl512b. Going to commit
as obvious if the CI agrees that it
So while debugging Austin's work to support the spacemit x60 in the BPI
we found that even though his pipeline description had mappings for all
the vector instructions, they were still getting matched by the
generic-vector-ooo DFA.
The core problem is that DFA never restricted itself to a tune
On 7/19/25 2:22 PM, Andrew Pinski wrote:
When we have an empty function, things can go wrong with
cfi_startproc/cfi_endproc and a few other things like exceptions. So if
the only thing the function does is a call to __builtin_unreachable,
let's replace that with a __builtin_trap instead if the
On 7/21/25 5:59 PM, Andrew Pinski wrote:
On Mon, Jul 21, 2025 at 4:46 PM Jeff Law wrote:
On 7/19/25 2:22 PM, Andrew Pinski wrote:
When we have an empty function, things can go wrong with
cfi_startproc/cfi_endproc and a few other things like exceptions. So if
the only thing the function
On 7/19/25 2:22 PM, Andrew Pinski wrote:
When we have an empty function, things can go wrong with
cfi_startproc/cfi_endproc and a few other things like exceptions. So if
the only thing the function does is a call to __builtin_unreachable,
let's replace that with a __builtin_trap instead if the
On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
This patch add support for XAndesvbfhcvt ISA extension.
This extension defines instructions to perform vector floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit
single-precision floating-point (SP) data in a vecto
On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
This extension defines instructions to perform scalar floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754
32-bit single-precision floating-point (SP) data in a scalar
floating point register.
gcc/ChangeLog:
* co
On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
This patch adds support for the XAndesperf ISA extension.
The 32-bit AndeStar V5 extension includes branch instructions,
load effective address instructions, and string processing
instructions for performance improvement.
New INSN patterns are added int
On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
This patch add basic support for the following XAndes ISA extensions:
XANDESPERF
XANDESBFHCVT
XANDESVBFHCVT
XANDESVSINTLOAD
XANDESVPACKFPH
XANDESVDOT
gcc/ChangeLog:
* config/riscv/riscv-ext.def: Include riscv-ext-andes.def.
* config/r
On 7/17/25 7:45 AM, Dusan Stojkovic wrote:
Hi Jeff,
So I'm not sure this transformation is correct.
Let's consider the case where a5 has the value 0x at the
"li" instruction.
a5 = 0xff00
li a4, -65536 // a4 = 0x
srai a5,a5,32 // a5 = 0xf
This is a trivial patch to add a few missing types to pipeline models
that are mostly complete.
In particular this adds the "ghost" to mips-p8700.md and the "sv_vc" and
"sf_vc_se" types to xiangshan.md.
There are definitely some bigger issues to solve in this space. But
this is a trivial fi
On 7/16/25 7:04 AM, Andreas Schwab wrote:
PR target/121121
* config/riscv/riscv.cc (riscv_allocate_and_probe_stack_space):
Use temp2 instead of temp1 for the CFA note.
---
gcc/config/riscv/riscv.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/g
On 7/16/25 8:38 AM, Paul-Antoine Arras wrote:
This pattern enables the combine pass (or late-combine, depending on the case)
to merge a float_extend'ed vec_duplicate into a (possibly negated) minus-mult
RTL instruction.
Before this patch, we have six instructions, e.g.:
vsetivli zero
On 7/17/25 2:24 AM, Stefan Schulze Frielinghaus wrote:
On Wed, Jul 09, 2025 at 03:48:43PM +0200, Stefan Schulze Frielinghaus wrote:
This is a follow-up to
https://gcc.gnu.org/pipermail/gcc-patches/2025-May/684181.html
I added the last missing pieces namely changelogs, and bootstrapped and
re
On 7/18/25 7:06 AM, Li, Pan2 wrote:
OK. Curious if you've seen this show up in practice and is using the
vaaddu and similar instructions actually profitable?
I remember avg will be presented in somewhere else but not for DImode.
I tried to add vaadd related vx combine and notice we don't ha
On 7/18/25 12:29 PM, Artemiy Volkov wrote:
On Fri, Jul 18, 2025 at 11:42:59AM -0600, Jeff Law wrote:
On 7/18/25 11:03 AM, Artemiy Volkov wrote:
On Wed, Jul 02, 2025 at 08:15:40PM -0600, Jeff Law wrote:
A number of folks have had their fingers in this code and it's going to take
On 7/19/25 3:37 AM, pan2...@intel.com wrote:
From: Pan Li
According to the semantics of the avg_floor and avg_ceil as below:
floor: op0 = (narrow) (((wide) op1 + (wide) op2) >> 1);
ceil: op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1);
Aka we have (const_int 1) as the op2 of the ashif
On 7/18/25 8:49 PM, pan2...@intel.com wrote:
From: Pan Li
The previous test case doesn't leverage the right test helper macro,
it should be DEF_AVG_0_WRAP instead of DEF_AVG_0. We prefer the
test function name is test_avg_floor_int64_t_int32_t_0 instead
of test_avg_floor_WT_NT_0 for DEF_AVG
On 7/18/25 11:03 AM, Artemiy Volkov wrote:
On Wed, Jul 02, 2025 at 08:15:40PM -0600, Jeff Law wrote:
A number of folks have had their fingers in this code and it's going to take
a few submissions to do everything we want to do.
This patch is primarily concerned with avoiding signaling
On 7/18/25 8:37 AM, Georg-Johann Lay wrote:
Ok to apply removal of backends no more present in v13?
Yes.
jeff
On 7/16/25 8:22 AM, pan2...@intel.com wrote:
From: Pan Li
Like the avg3_floor pattern, the avg3_ceil has the
similar issue that lack of the RVV DImode support.
Thus, this patch would like to support the DImode by
the standard name, with the iterator V_VLSI_D.
The below test suites are pass
On 7/16/25 9:20 AM, Stefan Schulze Frielinghaus wrote:
During jump bypassing also consider insns of the form
(insn 25 57 26 9 (parallel [
(set (reg:CCZ 33 %cc)
(compare:CCZ (reg:SI 60 [ _9 ])
(const_int 0 [0])))
(clobber (scratch
On 7/14/25 11:34 PM, Umesh Kalappa wrote:
Updated the test for rv32 accordingly and no regress found for runs like
"runtest --tool gcc
--target_board='riscv-sim/-march=rv32gc_zba_zbb_zbc_zbs/-mabi=ilp32d/-mcmodel=medlow'
riscv.exp" and
"runtest --tool gcc
--target_board='riscv-sim/-march=rv
On 7/10/25 8:44 AM, Dusan Stojkovic wrote:
This peephole pattern combines the following instructions:
bswap8:
rev8a5,a0
-> li a4,-65536
-> sraia5,a5,32
-> and a5,a5,a4
-> roriw a5,a5,16
and a0,a0,a4
or a
On 7/14/25 7:55 AM, Robin Dapp wrote:
Hi,
In PR120297 we fuse
vsetvl e8,mf2,...
vsetvl e64,m1,...
into
vsetvl e64,m4,...
Individually, that's ok but we also change the new vsetvl's demand to
"SEW only" even though the first original one demanded SEW >= 8 and
ratio = 16.
As we forget t
On 7/12/25 8:26 AM, pan2...@intel.com wrote:
From: Pan Li
Per previous discuss with Jeff, we don't do complicated
asm check like scalar saturation alu. It is somehow
not easy to maintain, as well as fragile. Thus, we
remove these function-body check, and introduce the
jmp label asm check i
On 7/12/25 2:58 AM, pan2...@intel.com wrote:
From: Pan Li
Add the run and asm testcase for rv32 SAT_MUL, widen mul from
uint8_t, uint16_t, uint32_t to uint64_t.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c: New test.
* gcc.target/riscv/sat/sat_
On 7/14/25 2:52 AM, Robin Dapp wrote:
This pattern enables the combine pass (or late-combine, depending on
the case)
to merge a float_extend'ed vec_duplicate into a plus-mult or minus-
mult RTL
instruction.
Before this patch, we have three instructions, e.g.:
fcvt.s.h fa5,fa5
vfmv
On 7/14/25 2:52 AM, Robin Dapp wrote:
This pattern enables the combine pass (or late-combine, depending on
the case)
to merge a float_extend'ed vec_duplicate into a plus-mult or minus-
mult RTL
instruction.
Before this patch, we have three instructions, e.g.:
fcvt.s.h fa5,fa5
vfmv
On 7/14/25 5:58 AM, Umesh Kalappa wrote:
Hi Jeff and Marco,
Please pass your comments on the below changes and do needful.
The changes fail pre-commit tsting:
https://patchwork.sourceware.org/project/gcc/patch/20250702071624.753431-1-ukalappa.m...@gmail.com/
On 7/10/25 8:37 AM, Jan Dubiec wrote:
On 10.07.2025 15:42, Jeff Law wrote:
[...]
Anyway, this has been repeatedly bootstrapped & regression tested on
aarch64, ppc64le and other targets. It's also been many dozens of
regression testing cycles on the various embedded targets.
Thi
On 7/9/25 11:53 PM, Sebastian Huber wrote:
There are targets, which only offer 32-bit atomic operations (for
example 32-bit RISC-V). For these targets, split the 64-bit atomic
bitwise-or operation into two parts.
For this test case
int a(int i);
int b(int i);
int f(int i)
{
if (i) {
On 2/22/25 8:10 AM, Jan Dubiec wrote:
This patch fixes SFtype to UDWtype (aka float to unsigned long long)
conversion on targets without DFmode like e.g. H8/300H. It solely relies
on SFtype->UWtype and UWtype->UDWtype conversions/casts. The existing code
in line 2218 (counter = a) assigns/cast
On 7/9/25 7:19 PM, Li, Pan2 wrote:
* gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c: Ditto.
Spot checked. Note this uses "RISC-V" so it's not going to be picked up
in the patchwork meeting.
Oops, should be a typo here.
It does seem to be causing some testing problems:
It seems the
On 7/3/25 3:50 PM, Palmer Dabbelt wrote:
This is really Jim's code, but it's been sitting around in Bugzilla for a while
so I've picked it up. All I really did here is add a target hook and mangle
some comments, but I think I understand enough about what's going on to try and
get things movin
On 7/1/25 10:13 PM, Andrew Pinski wrote:
With struct returns, we normally get a decl on the LHS of the call expression
that will be tail called and we can match things up there easy.
With TREE_ADDRESSABLE set on the type, things get more complex.
Instead we get:
```
*_6(D) = get_s (1); [ret
On 7/8/25 11:07 PM, pan2...@intel.com wrote:
From: Pan Li
The sat scalar run test should not require the v extension, thus
take rv32 || rv64 instead of riscv_v for the requirement.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
* The rv32gcv ful
On 7/8/25 9:17 AM, Paul-Antoine Arras wrote:
zvfh is not enabled at the testsuite level. It has to be enabled on a testcase
by testcase basis. This was correctly done for compile tests but not for run
tests. This patch fixes it.
Also, to ensure correct results with half-precision floats, MAX_R
On 7/9/25 2:35 AM, Ciyan Pan wrote:
From: panciyan
This patch adjust test data for unsigned vector SAT_SUB to vec_sat_data.h
Passed the rv64gcv regression test.
Signed-off-by: Ciyan Pan
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add
vec_sat_u_s
On 7/9/25 8:00 AM, Richard Sandiford wrote:
Makes me wonder if I should resurrect my aarch64_be RFS. I changed how
those systems worked in the system a few years back to make it work
better with container based testing rather than direct chroots. I never
converted aarch64_be to that setup
This is primarily Daniel's work... He's chasing things in QEMU & LLVM
right now so I'm doing a bit of clean-up and shepherding this patch forward.
--
Instruction fusion is a reasonably common way to improve the performance
of code on many architectures/designs. A few years ago we submitted
On 7/9/25 7:17 AM, Richard Biener wrote:
ISTR the backwards threader simply cancels paths that had blocks in
common with another jump thread (that happened to be materialized
first). But maybe it's less strict than that. It cancels things in too
many places and while it collects all opport
One thing I forgot to bring up in the patchwork meeting yesterday.
Philip or Craig asked if we should add the most basic fusions to the
generic tuning models for the two toolchains.
I'm generally in favor of making that kind of change. I don't think
anyone believes it'd be a major performanc
On 7/9/25 6:53 AM, Richard Biener wrote:
On Wed, Jul 9, 2025 at 2:16 PM Jeff Law wrote:
On 7/9/25 12:27 AM, Richard Biener wrote:
The following changes the percentage that determines how many
stmts are allowed for backwards jump threading from 50 to 54,
enabling the missed jump
On 7/9/25 12:27 AM, Richard Biener wrote:
The following changes the percentage that determines how many
stmts are allowed for backwards jump threading from 50 to 54,
enabling the missed jump threading observed in PR109893.
Bootstrapped and tested on x86_64-unknown-linux-gnu. It seems that
at
On 7/8/25 10:26 AM, Jan Dubiec wrote:
The patch changes order of inclusions, i.e. elfos.h is included before
target specific h8300/h8300.h, in a way similar to a few other targets.
Thanks to this change it is possible to override macros from elfos.h in
h8300/h8300.h, in particular .init/.fini
On 7/9/25 3:11 AM, Robin Dapp wrote:
Also, seems like the CI picked up the patch but didn't run it?
Yea, it's happened with a couple of mine recently, including one
yesterday. If it's not picked up when Paul-Antoine posts an update,
then I'll throw it into my system for some degree of pr
On 7/9/25 4:51 AM, Kito Cheng wrote:
OK if Pan say OK
Note the CI failure is unrelated to Ciyan Pan's work. Looks like
something went goofy in the libstdc++ space. I'm running it through my
tester right now.
jeff
AVL propagation currently assumes that it can propagate a constant AVL
into any vector insn and trips an assert if the insn fails to recognize
after such a propagation.
However, for xtheadvector that is not a correct assumption; xtheadvector
does not allow the vector length to be a constant
On 7/7/25 9:48 PM, Li, Pan2 wrote:
Is that correct? Don't you need to be testing that the platform has
vector in addition to being rv64?
It is riscv.exp test, so I think vector extension is not required here.
Oh, I see. We're not actually turning on RVV anywhere. OK for the trunk.
It lo
On 7/8/25 5:08 AM, Andreas Schwab wrote:
gcc:
PR target/120995
* config/riscv/sync.md (zacas_atomic_cas_value_strong):
Allow op3 to be zero.
gcc/testsuite:
PR target/120995
* gcc.target/riscv/amo/zabha-zacas-atomic-cas.c: New test.
Thanks. I didn't se
On 7/8/25 6:21 AM, Robin Dapp wrote:
Hi,
if a user passes a string that doesn't represent a variable we still try
to compute a hash for its type. Its tree does not represent a type but
just an exceptional, though. This patch just ignores it, leaving the
error to the checking code later.
Re
On 7/8/25 6:21 AM, Robin Dapp wrote:
Hi,
in emit_vlmax_insn_lra we use a vsetivli for an immediate AVL.
XTHeadVector does not support this, so guard appropriately.
Regtested on rv64gcv_zvl512b.
Regards
Robin
PR target/120461
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vlmax_
On 7/7/25 9:24 PM, pan2...@intel.com wrote:
/**/
/* Saturation Add (unsigned and signed)
*/
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
ommit 477abe67d34f7f8d1b0b12408e08769995b6ca9e
Author: Jeff Law
Date: Mon Jul 7 20:48:17 2025 -0600
[committed] Minor fix to gcc.dg/torture/pr120654.c
I don't recall which port complained, but pr120654.c was failing on one or
more
of the embedded targets due to the use of malloc/free. This change j
k-function-bodies atomic_add_fetch_int_seq_cst
Pushed to the trunk,
jeff
commit 7b1e8e0e85ec6f9d80ceb0d38355b2fcd4785f67
Author: Jeff Law
Date: Mon Jul 7 20:42:04 2025 -0600
[committed][RISC-V] Fix testsuite fallout from check-function-bodies change
Minor fallout from HJ's r
On 7/4/25 10:54 PM, Li, Pan2 wrote:
What you do want to watch out for is constants
Here I want the max value of unsigned scalar based on mode, it could be
UINT8_MAX,
UINT16_MAX, UINT32_MAX and UINT64_MAX.
Understood, but within the compiler HOST_WIDE_INT is how we tend to want
to work on
On 7/4/25 1:43 PM, Vineet Gupta wrote:
Hmm. I'm a little surprised that's needed. But there's new rules in
the era of LRA and define_constraint.
Yeah I was wondering why the fallback reg alternative is not already built-in.
Is that meant to catch bugs in the backends ?
I doubt it's meant
On 7/4/25 1:18 PM, Robin Dapp wrote:
This generally looks OK to me (including the tests).
+ HOST_WIDE_INT max = ((uint64_t)1 << bitsize) - 1;
Wouldn't a uint64_t type for max be clearer? I guess the worst that can
happen is compiling on a 32-bit host for a 64-bit target and get bitsize
On 7/4/25 10:21 AM, Richard Sandiford wrote:
ext-dce had:
if (SUBREG_P (dst) && SUBREG_BYTE (dst).is_constant ())
{
bit = subreg_lsb (dst).to_constant ();
if (bit >= HOST_BITS_PER_WIDE_INT)
bit = HOST_BITS_PER_WIDE_INT - 1;
On 7/3/25 5:19 PM, Vineet Gupta wrote:
Provide a fallback alternaive register contraint for LRA in the light of
the tightened "Q" constraint. Cures the following ICE ...
| gcc/testsuite/gcc.target/riscv/pr118241-b.cc:31:19: error: unable to generate
reloads for:
| 31 | void m() { a.l(); }
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