Committed to trunk
On Mon, Apr 24, 2023 at 11:09 AM juzhe.zh...@rivai.ai
wrote:
>
> I can push codes yet. Can you push them for me?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Jeff Law
> Date: 2023-04-22 04:42
> To: juzhe.zhong; gcc-patches
> CC: kito.cheng; palmer
> Subject: Re: [PATCH] RISC-V: Fix r
Committed to trunk
On Mon, Apr 24, 2023 at 11:06 AM juzhe.zh...@rivai.ai
wrote:
>
> Adding earlyclobber is to make dest operand do not overlap with source
> operand.
> For example:
> for gather load, vluxei.v v8,(a5),v8 is illegal according to RVV ISA.
> GCC is using same way as LLVM which is a
Committed, thanks!
On Tue, Apr 25, 2023 at 10:29 PM wrote:
> From: Pan Li
>
> In most architecture the precision_size of vbool*_t types are caculated
> like as the multiple of the type size. For example:
> precision_size = type_size * 8 (aka, bit count per bytes).
>
> Unfortunately, some archi
Plz write description for every item in changelog, otherwise the gcc
git hook will reject this patch.
remote: *** The following commit was rejected by your
hooks.commit-extra-checker script (status: 1)
remote: *** commit: 2777f46a58af65be380a2f44bf5cdf93e2d11886
remote: *** ChangeLog format failed
y for the implementation. Thus, it is
> OK if we think option 2 is a better way for this.
>
> Kito and Juzhe, any idea for making the decision? Thanks in advance!
>
> Pan
>
> -Original Message-
> From: Kito Cheng
> Sent: Tuesday, April 25, 2023 9:08 PM
> To
Hi ShiHua:
Thanks for your contribution to the zfbfmin extension :)
General comments:
- Add zfbfmin to riscv_ext_version_table
- Add test case to verify the -march is accepted.
- Add testcase to test argument passing.
- Add testcase for operations.
- Add testcase for compares.
> +(define_insn "*
tenance may be out of
> control if we will add many new define_insn_and_split for the shortcut.
> 2. The new added pattern may not friendly for the underlying
> auto-vectorization.
>
> Juzhe can help to correct me if any misleading.
>
> Pan
>
> -Original Message--
and merge it.
>
> Thanks,
> Philipp.
>
> On Tue, 25 Apr 2023 at 11:53, Kito Cheng wrote:
>
> > I am not sure if we should accept this on gcc trunk without binutils
> > support?
> >
> > On Sat, Apr 22, 2023 at 3:58 AM Jeff Law via Gcc-patches
> > wrot
I am not sure if we should accept this on gcc trunk without binutils support?
On Sat, Apr 22, 2023 at 3:58 AM Jeff Law via Gcc-patches
wrote:
>
>
>
> On 2/10/23 15:41, Philipp Tomsich wrote:
> > This adds the xventanacondops extension to the option parsing and as a
> > default for the ventana-vt1
Committed, thanks :)
On Sun, Apr 23, 2023 at 8:19 PM wrote:
>
> From: Juzhe-Zhong
>
> This patch is the V2
> patch:https://patchwork.sourceware.org/project/gcc/patch/20230328010124.235703-1-juzhe.zh...@rivai.ai/
>
> Address comments from Jeff. Add comments for all_avail_in_compatible_p and
> r
Pushed
On Sun, Apr 23, 2023 at 7:34 PM wrote:
>
> From: Juzhe-Zhong
>
> Address Jeff's comment:
> https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zh...@rivai.ai/
> Add a function comment.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (pass_vsetvl
Committed, thanks :)
On Sun, Apr 23, 2023 at 7:18 PM wrote:
>
> From: Juzhe-Zhong
>
> V2 patch for:
> https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zh...@rivai.ai/
> which has been reviewed.
>
> This patch address Jeff's comment, refine ChangeLog to give more
You need use git+ssh protocol, I use this way to manage that:
git remote add upstream-write git+ssh://@gcc.gnu.org/git/gcc.git
git push upstream-write master
On Sat, Apr 22, 2023 at 12:00 AM Vineet Gupta wrote:
>
>
> On 4/21/23 02:30, Richard Sandiford wrote:
> > No approval is needed when addi
--Original Message-
> From: Kito Cheng
> Sent: Friday, April 21, 2023 6:17 PM
> To: Li, Pan2
> Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng
> ; Wang, Yanzhang
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> I got a bunch
ng for the PATCH v2. Just FYI there will be some underlying
> investigation based on this PATCH like VMSEQ.
>
> Pan
>
> -Original Message-
> From: Li, Pan2
> Sent: Wednesday, April 19, 2023 7:27 PM
> To: 'Kito Cheng' ; 'juzhe.zh...@rivai.ai'
Thanks, committed to trunk.
On Fri, Apr 21, 2023 at 5:19 PM wrote:
>
> From: Juzhe-Zhong
>
> Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
>
> Consider the following testcase:
> void f (void * restrict in, void * restrict out, int l, int n, int m)
> {
> for (int i = 0; i < l;
Hi Robin:
OK, Feel free to commit that to trunk.
and don't forgot to mention this:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109582
On Fri, Apr 21, 2023 at 3:45 PM Robin Dapp via Gcc-patches
wrote:
>
> > ../../gcc/config/riscv/generic.md:28:1: unknown value `smin' for attribute
> > `type'
Committed with an extra testcase from PR109547
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616363.html
On Fri, Apr 7, 2023 at 9:34 AM wrote:
>
> From: Juzhe-Zhong
>
> This patch is to enhance optimization for auto-vectorization.
>
> Before this patch:
>
> Loop:
> vsetvl a5,a2...
> vset
From: Juzhe-Zhong
This patch is to enhance optimization for auto-vectorization.
Before this patch:
Loop:
vsetvl a5,a2...
vsetvl zero,a5...
vle
After this patch:
Loop:
vsetvl a5,a2
vle
gcc/ChangeLog:
PR target/109547
* config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn
Sorry, I didn't really commit this, it's send by accident since I give
wrong sha1
On Fri, Apr 21, 2023 at 2:47 PM Kito Cheng via Gcc-patches
wrote:
>
> ---
> gcc/common/config/riscv/riscv-common.cc | 118
> gcc/config/riscv/linux.h
---
gcc/common/config/riscv/riscv-common.cc | 118
gcc/config/riscv/linux.h| 13 ++-
2 files changed, 90 insertions(+), 41 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 309a52def75f..75b
Committed to trunk, thanks :)
On Tue, Apr 18, 2023 at 9:50 PM Jeff Law wrote:
>
>
>
> On 3/13/23 02:19, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > Co-authored-by: kito-cheng
> > Co-authored-by: kito-cheng
> >
> > Consider this
In newer ISA spec, F will implied zicsr, add that into -march option to
prevent different test result on different default -misa-spec version.
gcc/testsuite/
* gcc.target/riscv/arch-19.c: Add -misa-spec.
---
gcc/testsuite/gcc.target/riscv/arch-19.c | 4 ++--
1 file changed, 2 insertions(
GCC will complaint if target ABI isn't have corresponding multi-lib on
glibc toolchain, use stdint-gcc.h to suppress that.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/simplify_ior_optimization.c: Use stdint-gcc.h
rather than stdint.h
---
gcc/testsuite/gcc.target/riscv/simplify_io
Committed, thanks!
On Wed, Apr 19, 2023 at 6:42 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Testcase coming from Kito.
>
> Co-authored-by: kito-cheng
> Co-authored-by: kito-cheng
>
> PR 109535
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v
Hi Robin:
Share with you more context that I've discussed with Ju-Zhe, and look
for comments from you :)
There is 3 different auto vectorization flavor:
- VLA
- VLS fixed-vlmax (Name TBD)
- (Traditional) VLS
I think I don't need to explain too much on VLA.
So let we focus on second and third:
V
---
htdocs/gcc-13/changes.html | 34 +-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index f6941534..4515a6af 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -636,7
On Thu, Apr 20, 2023 at 5:07 PM juzhe.zh...@rivai.ai
wrote:
>
> >> With --param=riscv-autovec-preference=fixed-vlmax, however, the output is
> >> reasonable. BTW please use --param instead of -param in the description to
> >> avoid confusion.
> >>Now the patches don't explicitly note that they on
> LGTM, do we missed the timeline to merge code size reduction extensions
> support in gcc13?
Yeah, GCC 13 is branching out, so we need to wait for GCC 14, I also
really want to have this in GCC 13 too, and I am a little concerned
that it is still not officially ratified yet for merge that.
>
>
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h
> new file mode 100644
> index 000..be6b4c641cb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_
OK, thanks :)
On Thu, Apr 20, 2023 at 12:35 PM Jeff Law wrote:
>
> This is primarily Raphael's work. All I did was adjust it to apply to
> the trunk and add the new types to generic.md's scheduling model.
>
>
> The basic idea here is to make sure we have the ability to schedule the
> bitmanip in
On Thu, Apr 20, 2023 at 10:56 AM juzhe.zh...@rivai.ai
wrote:
>
> >> The comment above might not sync with your implementation?
> Address comment.
>
> >> Actually, you've allowed TARGET_MIN_VLEN < 128 && riscv_autovec_lmul <
> >> RVV_M2
> Not sure I am on the same page with you. I return word_mode
> +/* Return the vectorization machine mode for RVV according to LMUL. */
> +machine_mode
> +preferred_simd_mode (scalar_mode mode)
> +{
> + /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128
> + which is -march=rv64gcv. Since GCC loop vectorizer report ICE
> + when we enabl
Committed, thanks :)
On Wed, Apr 19, 2023 at 5:19 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch aligned the MODE_CLASS condition of the IOR to the AND. Then
> more MODE_CLASS besides SCALAR_INT can able to perform the optimization
> A | (~A) -> -1 similar to AND operator. For
Committed to trunk, thanks!
On Wed, Apr 19, 2023 at 8:34 PM wrote:
>
> From: Juzhe-Zhong
>
> RISC-V has provide different VLEN configuration by different ISA
> extension like `zve32x`, `zve64x` and `v`
> zve32x just guarantee the minimal VLEN is 32 bits,
> zve64x guarantee the minimal VLEN is 64
> On Wed, 19 Apr 2023 06:53:51 PDT (-0700), kito.ch...@sifive.com wrote:
> > ---
> > htdocs/gcc-13/changes.html | 31 ++-
> > 1 file changed, 30 insertions(+), 1 deletion(-)
> >
> > diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
> > index f6941534.
---
htdocs/gcc-13/changes.html | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index f6941534..5427f805 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -636,9 +63
Could you add more description? maybe like this:
RISC-V has provide different VLEN configuration by different ISA
extension like `zve32x`, `zve64x` and `v`
zve32x just guarantee the minimal VLEN is 32 bits,
zve64x guarantee the minimal VLEN is 64 bits,
and v guarantee the minimal VLEN is 128 bits
HI JuZhe:
Thanks for explaining!
Hi Pan:
I think that would be helpful if JuZhe's explaining that could be
written into the commit log.
> gcc/ChangeLog:
>
>* config/riscv/riscv-v.cc (emit_pred_op):
>* config/riscv/riscv-vector-builtins-bases.cc:
>* config/riscv/vector.
Hi Pan:
>rtx expand (function_expander &e) const override diff --git
> a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index
> 0ecca98f20c..6819363b9ff 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred
Write a primary version for that, did you mind giving it a try?
The basic idea is to select multilib only by ABI, so that we don't
need to bother with endless multilib reuse cases...
On Wed, Apr 19, 2023 at 9:38 AM Kito Cheng wrote:
>
> OK, thanks, I know what the problem is, I tri
OK, thanks, I know what the problem is, I tried rv64 but didn't try
rv32, I have another fix in my mind, and will post another fix soon.
On Wed, Apr 19, 2023 at 9:29 AM Palmer Dabbelt wrote:
>
> On Tue, 18 Apr 2023 18:26:18 PDT (-0700), Kito Cheng wrote:
> > And which -march -m
And which -march -mabi you used will got issue?
On Wed, Apr 19, 2023 at 8:51 AM Palmer Dabbelt wrote:
>
> On Tue, 18 Apr 2023 17:47:31 PDT (-0700), Kito Cheng wrote:
> > Do you mind shared gcc configure and the option you tried?
>
> Just riscv-gnu-toolchain with "--enbale-
> diff --git a/gcc/config/riscv/vector-iterators.md
> b/gcc/config/riscv/vector-iterators.md
> index 70ad85b661b..7fae87968d7 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -34,6 +34,8 @@
>UNSPEC_VMULHU
>UNSPEC_VMULHSU
>
> + UNSPEC_VA
> @@ -118,6 +120,41 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT
> minval,
> && IN_RANGE (INTVAL (elt), minval, maxval));
> }
>
> +/* Return the vlmul field for a specific machine mode. */
> +unsigned int
> +riscv_classify_vlmul_field (enum machine_mode mode)
This is not imp
> +/* Implement TARGET_ESTIMATED_POLY_VALUE.
> + Look into the tuning structure for an estimate.
> + KIND specifies the type of requested estimate: min, max or likely.
> + For cores with a known RVV width all three estimates are the same.
> + For generic RVV tuning we want to distinguish th
Could you please move the new function declarations and new code to
the patch where they are being used?
> +/* RVV vector register sizes. */
> +enum riscv_vector_bits_enum
> +{
> + RVV_SCALABLE,
> + RVV_NOT_IMPLEMENTED = RVV_SCALABLE,
> + RVV_64 = 64,
> + RVV_128 = 128,
> + RVV_256 = 256,
>
Do you mind shared gcc configure and the option you tried?
On Wed, Apr 19, 2023 at 4:01 AM Palmer Dabbelt wrote:
>
> On Tue, 18 Apr 2023 08:44:24 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> >> Yep, if I drop the non-canonicial strings via
> >>
> >> diff --git a/gcc/config/riscv/multilib-gen
Hi Richard, Jeff:
It's it possible to backport to GCC 13? highway is one of our
important users for RISC-V vector stuff, and it has built in some
distro, so we believe this bug fix is important to backport.
Thanks
Hi Ju-Zhe:
Thanks for update
On Wed, Apr 19, 2023 at 7:25 AM wrote:
>
> From: J
Hi Jeff, Ju-Zhe:
Let you know that I am running creduce with this testcase for reduce
the size of testcsae, it's really too huge...
On Wed, Apr 19, 2023 at 3:00 AM Jeff Law via Gcc-patches
wrote:
>
>
>
> On 4/17/23 20:03, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > gcc/ChangeLog:
4 + 4x SImode where x is 0~n, so it
will hold at least four DI
So GET_MODE_NUNITS for a single vector register with DI mode will
become 2 (VNx2DImode) if it is really possible, which is a more
precise way to model the vector extension for RISC-V .
On Tue, Apr 18, 2023 at 10:28 PM Kito Cheng
committed to trunk and gcc 13
On Tue, Apr 18, 2023 at 9:29 PM Jeff Law wrote:
>
>
>
> On 4/18/23 04:16, Kito Cheng via Gcc-patches wrote:
> > Document which version of RISC-V vector intrinsics has implemented in
> > GCC.
> >
> > gcc/ChangeLog:
> >
&g
> Yep, if I drop the non-canonicial strings via
>
> diff --git a/gcc/config/riscv/multilib-generator
> b/gcc/config/riscv/multilib-generator
> index 58b7198b243..a63a4d69c18 100755
> --- a/gcc/config/riscv/multilib-generator
> +++ b/gcc/config/riscv/multilib-generator
> @@ -174
Wait, VNx1DImode can be really evaluate to just one element if
-march=rv64g_zve64x,
I thinks this should be just fixed on backend by this patch:
https://patchwork.ozlabs.org/project/gcc/patch/20230414014518.15458-1-juzhe.zh...@rivai.ai/
On Tue, Apr 18, 2023 at 2:12 PM Richard Biener via Gcc-patc
I would prefer drop this patch from this patch series since I believe
https://patchwork.ozlabs.org/project/gcc/patch/20230414014518.15458-1-juzhe.zh...@rivai.ai/
is the right fix for this issue.
On Tue, Apr 18, 2023 at 2:40 AM Michael Collison wrote:
>
> From: Kevin Lee
>
> Kevin Lee
> gcc/Chan
Thanks, applied to trunk :)
On Tue, Apr 18, 2023 at 5:27 PM Jin Ma wrote:
>
> The current order of gcc and binutils parsing extensions is inconsistent.
>
> According to latest risc-v spec, the canonical order in which extension names
> must
> appear in the name string specified in Table 29.1 is
Document which version of RISC-V vector intrinsics has implemented in
GCC.
gcc/ChangeLog:
* doc/extend.texi (Target Builtins): Add RISC-V Vector
Intrinsics.
(RISC-V Vector Intrinsics): Document GCC implemented which
version of RISC-V vector intrinsics and its refer
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/scalar_move-2.c: Adjust include way
for riscv_vector.h
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: Add missing
-mabi.
---
gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-2.c | 2 +-
gcc/testsuite/gcc.tar
ent: Friday, April 14, 2023 2:47 PM
> To: Kito Cheng
> Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng
> ; Wang, Yanzhang
> Subject: RE: [PATCH v2] RISC-V: Add test cases for the RVV mask insn shortcut.
>
> You're very welcome!
>
> Looks vmorn(v,v) doesn't per
Wait, take second round review:
> * All extensions were being prefixed with an underscore, which leads to
> some odd combinations like "rv32gc_v", this just adds underscores to
> the multi-letter extensions.
> * The input base ISAs were being canonicalized, which resulted in some
> odd multi
OK, thanks for the patch :)
On Fri, Apr 14, 2023 at 11:27 AM Li, Pan2 via Gcc-patches
wrote:
>
> Thanks juzhe, update new version [PATCH v3] for even more checks.
>
> Pan
>
> From: juzhe.zh...@rivai.ai
> Sent: Friday, April 14, 2023 10:46 AM
> To: Li, Pan2 ; gcc-patches
> Cc: Kito.cheng ; Wang,
Thanks for catch this, I didn't enable multilib for linux toolchain
for a while,
I guess we should implement TARGET_COMPUTE_MULTILIB for linux targets
to simplify the damm multilib files, but I agree it's too late in the
release cycle, so let's fix that in this way for now.
So LGTM and OK for trun
Ok, thanks :)
Palmer Dabbelt 於 2023年4月13日 週四，23:12寫道：
> The RVV test harness currently sets the ISA according to the target
> tuple, but doesn't also set the ABI. This just sets the ABI to match
> the ISA, though we should really also be respecting the user's specific
> ISA to test.
>
> gcc/test
Thanks for the quick response! verified and pushed to trunk.
On Wed, Apr 12, 2023 at 9:56 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Fix supporting data type according to RVV ISA.
> For vint64m*_t, we should only allow them in zve64* instead of zve32*_zvl64b
> (>=64b).
> Ideally, we should make error
OK for trunk, but plz improve the coverage of the testcase, e.g.
vint16mf4_t has fixed too but not tested in testcase.
On Wed, Apr 12, 2023 at 7:09 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Fix supporting data type according to RVV ISA.
> For vint64m*_t, we should only allow them in zve64* instead of
> > The concept of fractional LMUL is the same as the concept of AArch64's
> > partial SVE vectors,
> > so they can only access the lowest part, like SVE's partial vector.
> >
> > We want to spill/restore the exact size of those modes (1/2, 1/4,
> > 1/8), so adding dedicated modes for those partial
Hi Richard:
> > In order to model LMUL in backend, we have to the combination of
> > scalar type and LMUL; possible LMUL is 1, 2, 4, 8, 1/2, 1/4, 1/8 - 8
> > different types of LMUL, and we'll have QI, HI, SI, DI, HF, SF and DF,
> > so basically we'll have 7 (LMUL type) * 7 (scalar type) here.
>
>
get/riscv/zero-scratch-regs-1.c: New test.
> > * gcc.target/riscv/zero-scratch-regs-2.c: New test.
> > * gcc.target/riscv/zero-scratch-regs-3.c: New test.
> >
> > Signed-off-by: Yanzhang Wang
> > Co-authored-by: Pan Li
> > Co-authore
Let me give more explanation why RISC-V vector need so many modes than AArch64.
The following will use "RVV" as an abbreviation for "RISC-V Vector"
instructions.
There are two key points here:
- RVV has a concept called LMUL - you can understand that as register
grouping, we can group up to 8 ad
> > Do you need to save/restore the vector configuration before and after
> > clearing the vector registers?If so, that seems to be missing. If
> > not, it seems like a comment explaining why would be useful.
>
> I'll add some comments in the code and want to explain here first.
> We need not
Generally LGTM, just one more comment :)
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..aad046240ee 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -724,4 +735,54 @@ gen_avl_for_scalar_move (rtx avl)
> }
> }
>
Is changes for riscv-vsetvl.cc necessary for autovec? or is it
additional optimization for the autovec use case? I would suggest
splitting that if it's later one.
And plz split out fixed-vlmax part into separated patch, that would be
easier to review.
On Thu, Apr 6, 2023 at 10:44 PM wrote:
>
> F
You included asm output by accidently :P
On Thu, Apr 6, 2023 at 10:45 PM wrote:
>
> From: Juzhe-Zhong
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/rvv.exp: Add testing for RVV
> auto-vectorization.
> * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase.
>
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..90c69b52bb4 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -43,6 +43,7 @@
> #include "optabs.h"
> #include "tm-constrs.h"
> #include "rtx-vector-builder.h"
> +#include
LGTM, thanks :)
On Thu, Apr 6, 2023 at 5:46 PM Jakub Jelinek via Gcc-patches
wrote:
>
> Hi!
>
> I've noticed
> make: Circular build/genrvv-type-indexer.o <- gtype-desc.h dependency dropped.
>
> The following patch fixes that. The RTL_BASE_H variable includes a lot of
> headers which the generato
ok, thanks!
On Tue, Apr 4, 2023 at 5:01 PM Jakub Jelinek via Gcc-patches
wrote:
>
> Hi!
>
> The following patch unbreaks riscv bootstrap, where it previously failed
> on -Werror=format-diag warning promoted to error.
>
> Ok for trunk?
>
> Or shall it say e.g.
> "%<-march=%s%>: % extension conflic
Commit as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=db4f7a9b47d148b5074ac15910124c746fb7a96f
with more commit log
On Wed, Mar 29, 2023 at 10:43 AM wrote:
>
> From: Juzhe-Zhong
>
> bug.C:144:2: error: unrecognizable insn:
> 144 | }
> | ^
> (insn 684 683 685 26 (set (reg:SI 513)
>
Committed as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=802ab7d0db5b5aa46edc8d82526d97258c599927
, thanks
On Wed, Mar 29, 2023 at 10:48 AM wrote:
>
> From: Juzhe-Zhong
>
> Co-authored-by: kito-cheng
> Co-authored-by: kito-cheng
>
> This path fix ICE of ternary int
gcc/ChangeLog:
PR target/109328
* config/riscv/t-riscv: Add missing dependencies.
Co-authored-by: Andrew Pinski
---
gcc/config/riscv/t-riscv | 43
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/gcc/config/riscv/t-riscv b/
x extension, so we just need to check f with zfinx extension
> as the base case.
>
> Co-Authored by: Kito Cheng
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
> * New check.
>
> gcc/testsuite/ChangeLog:
&g
Applied to trunk :)
於 2023年3月28日 週二，22:34寫道：
> LGTM。
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-03-28 22:26
> To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong;
> jeffreyalaw
> CC: Kito Cheng
> Subject: [PATCH
k one char when the pointer moving, So I still keep the
> implement
> by check the extenstison with target. Maybe we can add new check function in
> the new
> version :)
>
>
> > -原始邮件-
> > 发件人: "Kito Cheng"
> > 发送时间: 2023-03-27 16:15:00 (星期一
I would prefer those checking happened in
riscv_subset_list::parse@gcc/common/config/riscv/riscv-common.cc that
could be reused when we adding target attribute.
And I plan integrate the arch-canonicalize script to just reusing
whole arch string parser in GCC 14, so it would be great to have all
ch
RVV intrinsic has defined a macro to identity the version of RVV
intrinsic spec, we missed that before, thanksful we are catch this
before release.
gcc/ChangeLog:
PR target/109312
* config/riscv/riscv-c.cc (riscv_ext_version_value): New.
(riscv_cpu_cpp_builtins): Define __
OK for trunk, thanks :)
On Mon, Mar 27, 2023 at 7:04 PM Christoph Muellner <
christoph.muell...@vrull.eu> wrote:
> From: Christoph Müllner
>
> This patch adds missing mode specifiers for XTheadMemPair INSNs.
>
> gcc/ChangeLog:
> PR target/109296
> * config/riscv/thead.md: Add mis
HI Jiawei:
Thanks for the fix!
Two comments:
- Could you add testcase like
https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/riscv/arch-12.c
- And I would prefer those check happened in riscv_subset_list::parse
@gcc/common/config/riscv/riscv-common.cc
On Sun, Mar 26, 2023 at
Committed 2 weeks ago but apparently I didn't send mail to say that,
thanks Vineet.
On Thu, Mar 2, 2023 at 3:56 AM Philipp Tomsich wrote:
>
> On Wed, 1 Mar 2023 at 20:53, Vineet Gupta wrote:
> >
> > This showed up as dynamic icount regression in SPEC 531.deepsjeng with
> > upstream
> > gcc (vs.
committed, thanks for the reminder :)
On Mon, Mar 13, 2023 at 9:40 AM Li, Pan2 via Gcc-patches
wrote:
>
> Kindly reminder for this PR. Thank you all in advance.
>
> Pan
>
> -Original Message-
> From: Li, Pan2
> Sent: Wednesday, March 8, 2023 7:31 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juz
Nice catch, committed to the trunk!
On Tue, Mar 21, 2023 at 3:39 PM Songhe Zhu wrote:
>
> The arch 'rv32imac' will not be created when excuting
> './multilib-generator rv32imc-ilp32--a'
>
> The output is:
> MULTILIB_OPTIONS = march=rv32imc mabi=ilp32
> MULTILIB_DIRNAMES = rv32imc ilp32
> MULTILIB
committed as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=6f6eba35b9f06d35ff7bea81969fe905a5584bdc
On Fri, Mar 10, 2023 at 4:09 PM wrote:
>
> From: Ju-Zhe Zhong
>
> vfrsub_vf_m.cpp: In function 'int main()':
> vfrsub_vf_m.cpp:5:43: error: invalid argument to built-in function
>5 | vbool3
committed as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0e2715176df3787d1470d7b9bde26b1b5e16e1e2
On Mon, Mar 20, 2023 at 8:51 AM juzhe.zh...@rivai.ai
wrote:
>
> The last patch. Kito is still keep testing with pressure tests.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Jeff Law
> Date: 2023-03-20 0
committd as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a481eed8fd01837cdf011ea9a17853505080a888
with comment tweaks
On Mon, Mar 20, 2023 at 12:30 PM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (eliminate_insn): Fix bugs.
> (insert_vsetv
LGTM, but pending this to the GCC 14 queue.
On Wed, Mar 22, 2023 at 8:16 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Current expansion of vmsge will make RA produce redundant vmv1r.v.
>
> testcase:
> void f1 (void * in, void *out, int32_t x)
> {
> vbool32_t mask = *(vbool32_t*)in;
> asm volatil
Committed as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=cd0c433e5faba9a18f64881cd761a53a530aa798
with comment tweak.
On Wed, Mar 22, 2023 at 10:50 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (emit_vlmax_vsetvl): Define as global.
> (e
committed as
https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=116a8678840f9f52ec14639ff07e302a8c429f32
with few comment tweak.
On Wed, Mar 22, 2023 at 1:06 PM wrote:
>
> From: Ju-Zhe Zhong
>
> This patch fix PR109228
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109228
>
> gcc/ChangeLog:
>
>
Committed with git log tweak:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c413abed869e7e34a86855a015413418f3c6b595
On Mon, Mar 13, 2023 at 3:52 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Co-authored-by: kito-cheng
> Co-authored-by: kito-cheng
>
> This patch fixed a bunc
Committed with commit log tweak:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=02880e7803b19c357718abd2f0d567b4a761f318
On Wed, Mar 15, 2023 at 11:06 AM juzhe.zh...@rivai.ai
wrote:
>
> Yes, I have write access. However, I am new to commit patch to GCC trunk.
> I didn't figure out how to commit pa
...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > Co-authored-by: kito-cheng
> > Co-authored-by: kito-cheng
> >
> > Consider this case:
> > void f19 (void *base,void *base2,void *out,size_t vl, int n)
> > {
> > vuint64m8_t bindex = __riscv
Can you take a look at this?
>
>
> juzhe.zh...@rivai.ai
>
> From: Sam James
> Date: 2023-03-14 08:23
> To: gcc-patches
> CC: Kito Cheng; Palmer Dabbelt; Andrew Waterman; Jim Wilson; Ju-Zhe Zhong;
> Sam James
> Subject: [PATCH v4 2/2] gcc: Drop obsolet
RISC-V part is ok, and I assume you didn't have write access so I'm
gonna push that since the system.h change also got approved :)
On Tue, Mar 14, 2023 at 5:07 PM Richard Biener via Gcc-patches
wrote:
>
> On Tue, Mar 14, 2023 at 1:24 AM Sam James via Gcc-patches
> wrote:
> >
> > This fixes error
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