On 1 August 2014 16:09, Alan Lawrence alan.lawre...@arm.com wrote:
None of the variants of __builtin_aarch64_get_lane or
__builtin_aarch64_dup_lane are used in arm_neon.h (vdup_lane uses vget_lane
and vdup_n, vget_lane uses be_checked_get_lane to do an endianness swap,
vdup_n uses gcc vector
On 30 July 2014 11:10, James Greenhalgh james.greenha...@arm.com wrote:
2014-07-30 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Vary
the generated mask based on BYTES_BIG_ENDIAN.
On 30 July 2014 11:19, James Greenhalgh james.greenha...@arm.com wrote:
2014-07-28 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64-builtins.c
(aarch64_gimple_fold_builtin): Don't fold reduction operations for
BYTES_BIG_ENDIAN.
OK /Marcus
On 31 July 2014 17:12, James Greenhalgh james.greenha...@arm.com wrote:
---
gcc/
2014-07-31 James Greenhalgh james.greenha...@arm.com
* config/aarch64/arm_neon.h (vpadd_suf8,16,32,64): Move to
correct alphabetical position.
(vpaddd_f64): Rewrite using builtins.
On 22 July 2014 15:52, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_expand_epilogue): Don't subtract
outgoing area size when restore stack_pointer_rtx.
gcc/testsuite/
* gcc.target/aarch64/test_frame_12.c: Match optimized instruction
sequences.
OK and
On 22 July 2014 15:52, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.h (frame): New fields wb_candidate1 and
wb_candidate2.
* config/aarch64/aarch64.c (aarch64_layout_frame): Calcualte new added
fields.
OK and applied.
/Marcus
On 22 July 2014 15:52, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_save_callee_save_common): New
parameter skip_wb.
(aarch64_restore_callee_save_common): Likewise.
(aarch64_expand_prologue): Update call site.
(aarch64_expand_epilogue): Likewise.
On 24 July 2014 13:43, Jiong Wang jiong.w...@arm.com wrote:
Under new pro/epi code, we could also utilize our store write-back to
optimize
stack adjustment when there is no frame pointer.
* if there is candidate reg pair and adjustment amount is less than 512 then
we
could use aarch64's
On 24 July 2014 13:48, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_popwb_single_reg): New function.
(aarch64_expand_epilogue): Optimize epilogue when !frame_pointer_needed.
gcc/testsuite/
* gcc.target/aarch64/test_frame_1.c: Match optimized
On 22 July 2014 15:49, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): GNU-Stylize
code.
(aarch64_save_or_restore_callee_save_registers): Likewise.
(aarch64_expand_prologue): Likewise
OK and applied.
/Marcus
On 22 July 2014 15:49, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Change type to
HOST_WIDE_INT.
OK and applied.
/Marcus
On 22 July 2014 15:49, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c
(aarch64_save_or_restore_callee_save_registers): Rename
'offset' to 'start_offset'. Remove local variable 'start_offset'.
OK and applied.
/Marcus
On 22 July 2014 15:50, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Remove
base_rtx.
(aarch64_save_or_restore_callee_save_registers): Likewise.
OK and applied.
/Marcus
On 22 July 2014 15:51, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Use register
offset in
cfun-machine-frame.reg_offset.
(aarch64_save_or_restore_callee_save_registers): Likewise.
OK and applied.
/Marcus
On 22 July 2014 15:51, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Remove
increment.
(aarch64_save_or_restore_callee_save_registers): Likewise.
OK and applied.
/Marcus
On 22 July 2014 15:51, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Hoist
calculation
of register rtx.
(aarch64_save_or_restore_callee_save_registers): Likewise.
OK and applied.
/Marcus
On 22 July 2014 15:51, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_next_callee_save): New function.
(aarch64_save_or_restore_fprs): Use aarch64_next_callee_save.
(aarch64_save_or_restore_callee_save_registers): Likewise.
OK and applied.
/Marcus
On 22 July 2014 15:51, Jiong Wang jiong.w...@arm.com wrote:
* config/aarch64/aarch64.c (aarch64_gen_store_pair): New helper function.
(aarch64_gen_load_pair): Likewise.
(aarch64_save_or_restore_fprs): Use new helper functions.
(aarch64_save_or_restore_callee_save_registers): Likewise.
On 22 July 2014 15:51, Jiong Wang jiong.w...@arm.com wrote:
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Deleted.
(aarch64_save_callee_saves): New function to handle reg save
for both core and vectore regs.
OK and applied
/Marcus
On 22 July 2014 15:51, Jiong Wang jiong.w...@arm.com wrote:
* config/aarch64/aarch64.md: (aarch64_save_or_restore_callee_saves):
Rename to aarch64_save_callee_saves, remove restore code.
(aarch64_restore_callee_saves): New function.
OK and applied.
/Marcus
On 22 July 2014 15:51, Jiong Wang jiong.w...@arm.com wrote:
This patch simplify aarch64_expand_prologue using our new
helper functions. All ad-hoc code for saving FP/LR are removed.
*no functional change*
I think you mean no change in generated code rather than no functional change...
gcc/
On 22 July 2014 15:51, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_gen_loadwb_pair): New helper function.
(aarch64_popwb_pair_reg): Likewise.
(aarch64_expand_epilogue): Simplify code using new helper functions.
ChangeLog entry is missing the .md file
On 16 July 2014 10:49, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch implements the vbsl_f64 intrinsic and adds an execution test for
it.
Not much else to say about it.
Tested aarch64-none-elf.
Ok for trunk?
2014-07-16 Kyrylo Tkachov kyrylo.tkac...@arm.com
*
On 22 July 2014 12:23, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
I noticed that we use UNSPEC_CLS for the clrsb optab when we could be using
the RTL code for it. I don't see any reason not to use the RTL code and some
execution tests confirm that the cls instruction implements the
On 22 July 2014 12:23, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Following up on patch [1/2] Remove UNSPEC_CLS and use clrsb RTL code in
its' place this patch adds rtx costs handling of the CLZ, CLRSB RTL codes
as well as the UNSPEC_RBIT unspec.
The CLZ and CLRSB cases are
On 9 July 2014 15:37, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
These intrinsics are implemented as macros that map down to asms but the
types they accept are inconsistent with the ACLE spec. This patch fixes
them, although they should be reimplemented properly in C in the future.
On 20 June 2014 15:17, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Now that Alan fixed the float64x1_t machinery, this patch implements some
low-hanging intrinsics
in arm_neon.h.
Tested aarch64-none-elf and bootstrapped on aarch64-linux.
Ok for trunk?
Thanks,
Kyrill
On 10 July 2014 08:56, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 02/07/14 08:59, Christophe Lyon wrote:
Hi,
It seems some of the scan-assembler directives fail:
On 1 July 2014 11:05, Christophe Lyon christophe.l...@linaro.org wrote:
* documentation (README)
* dejanu driver (neon-intrinsics.exp)
* support macros (arm-neon-ref.h, compute-ref-data.h)
* Tests for 3 intrinsics: vaba, vld1, vshl
Hi, The terminology in armv8 is advsimd rather than neon.
On 8 July 2014 12:39, Jakub Jelinek ja...@redhat.com wrote:
On Tue, Jul 08, 2014 at 12:28:54PM +0100, Alan Lawrence wrote:
This corrects name-mangling of float64x1_t and makes it a distinct type from
float64_t, as per ACLE - the error mentioned in the Caveats section at
On 8 July 2014 13:31, Jakub Jelinek ja...@redhat.com wrote:
Many people are using different patch levels interchangeably and expect
them to be compatible. If X1 vectors are relatively rare, the better,
fewer people will be affected when switching from 4.9.x to 4.10.x.
But IMHO changing ABI
On 24 June 2014 09:45, James Greenhalgh james.greenha...@arm.com wrote:
2014-06-20 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64-simd.md (move_lo_quad_internal_mode): New.
(move_lo_quad_internal_be_mode): Likewise.
(move_lo_quad_mode): Convert
On 4 July 2014 14:58, Alan Lawrence alan.lawre...@arm.com wrote:
No regressions on aarch64-none-elf; new tests passing on aarch64-none-elf,
arm-none-eabi, x86_64-unknown-linux-gnu:
NA-PASS gcc.dg/vect/vect-singleton_1.c (test for warnings, line 20)
NA-PASS gcc.dg/vect/vect-singleton_1.c (test
On 2 July 2014 09:02, Tom de Vries tom_devr...@mentor.com wrote:
On 02-07-14 08:23, Marc Glisse wrote:
In the first example you gave, looking at the pattern (no match_dup,
setting the
full register), it seems that it may have wanted = instead of +.
[ move discussion from gcc ml to
On 4 June 2014 01:07, Jones, Joel joel.jo...@caviumnetworks.com wrote:
There is duplicate code for determining whether a load or store
instruction needs acquire or release semantics. This patch removes the
duplicated code and uses a modifying operator to output a/l instead. Since
the
On 23 June 2014 15:30, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch implements some absolute compare intrinsics in arm_neon.h.
Execution tests are added.
Tested aarch64-none-elf, aarch64_be-none-elf, bootstrapped on aarch64 linux
+/* { dg-do run } */
+/* { dg-options
adjusts the splits to use the output operand as the scratch
register.
Regressed aarch64-none-elf. Committed to trunk as r212137.
Back port to 4.9 coming shortly.
/Marcus
2014-06-30 Marcus Shawcroft marcus.shawcr...@arm.com
PR target/61633
* config/aarch64/aarch64.md
On 30 June 2014 10:41, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Here it is.
Now it applies cleanly to 4.9 and the tests are in gcc.target/aarch64
instead of gcc.target/aarch64/simd
Tested on aarch64-none-elf and aarch64_be-none-elf.
Ok to apply?
OK, thanks.
/Marcus
On 30 June 2014 09:03, Ramana Radhakrishnan ramana@googlemail.com wrote:
+ Move the tests to gcc.target/arm/ to gcc.target/aarch64 if the
AArch64 maintainers agree. For the extra AArch64 variants guard them
with #ifdef __aarch64__ #endif.
Given that the intrinsics in aarch64 are a
On 25 June 2014 10:21, Alan Lawrence alan.lawre...@arm.com wrote:
This one seems to have slipped under the radar. I've just rebased and run
the regression tests on aarch64_be-none-elf, with no issues; ping?
(patch applied straightforwardly, but rebased version below)
OK /Marcus
On 19 June 2014 14:12, James Greenhalgh james.greenha...@arm.com wrote:
This has been sitting waiting for comment for a while now. If we do need a
mechanism to describe individual costs for alternatives, it will need
applied to all the existing uses in aarch64.md/aarch64-simd.md. I think
On 20 June 2014 15:14, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Sure, but it depends on
https://gcc.gnu.org/ml/gcc-patches/2014-06/msg00779.html.
Is it ok to backport that one as well?
This can be backported as well.
/Marcus
On 16 June 2014 15:26, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
I noticed that a few saturating math intrinsics in arm_neon.h for aarch64
have the wrong types, i.e. not what's mandated by the ACLE spec.
This patch fixes that by adjusting the types of the builtin functions that
On 19 June 2014 13:27, Alan Lawrence alan.lawre...@arm.com wrote:
This updates the .md files to generate V1DFmode patterns instead of DFmode
for create and reinterpret, and the corresponding __builtins.
The various other float64x1_t intrinsics can then be rewritten, generally
I've tried to
On 19 June 2014 13:30, Alan Lawrence alan.lawre...@arm.com wrote:
Similarly, this makes int64x1_t a proper vector type, updating arm_neon.h
with many explicit vector construction/destruction operations (also
including some range checking using __builtin_aarch64_im_lane_boundsi).
Change the
On 19 June 2014 14:32, Yufeng Zhang yufeng.zh...@arm.com wrote:
Hi,
This patch updates a number of aapcs64 tests to make them big-endian
friendly. Changes are mainly:
* checking the W regs instead of X regs for integral arguments less than 8
bytes
* correcting the corresponding stack
On 1 June 2014 11:00, Tom de Vries tom_devr...@mentor.com wrote:
Richard,
This patch:
- adds the for TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS required
clobbers in CALL_INSN_FUNCTION_USAGE,
- sets TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS to true, which
enables
the
On 12 June 2014 18:04, Yufeng Zhang yufeng.zh...@arm.com wrote:
Hi,
The patch fixes a bug in the AArch64 backend in calculating the beginning
address of the unnamed incoming arguments on the stack, i.e. the initial
value of __va_list-__stack. aarch64_layout_arg incorrectly calculates the
On 10 June 2014 11:01, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This is an implementation of the ACLE intrinsics that can be used to access
the CRC32 instructions. We have them already implemented in aarch32.
You can find their definition and documentation at
On 10 June 2014 11:02, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This is the testsuite for the CRC32 ACLE intrinsics. They are done in much
the same way as the aarch32 tests in gcc.target/arm/acle/acle.exp except
that these are modified to run at -O2 optimisation level.
These
On 15 May 2014 17:12, Alan Lawrence alan.lawre...@arm.com wrote:
Oops, I missed:
gcc/ChangeLog:
2014-05-15 Alan Lawrence alan.lawre...@arm.com
* config/aarch64/aarch64-modes.def: Add V1DFmode.
* config/aarch64/aarch64.c (aarch64_vector_mode_supported_p):
Support
On 29 May 2014 17:47, Alan Lawrence alan.lawre...@arm.com wrote:
Patch retaining vfmaq_n_f64 attached, updated gcc/ChangeLog:
* config/aarch64/arm_neon.h (vmlaq_n_f64, vmlsq_n_f64, vrsrtsq_f64,
vcge_p8, vcgeq_p8, vcgez_p8, vcgez_u8, vcgez_u16, vcgez_u32,
vcgez_u64,
Looks like a copy n paste error originally.
Committed.
/Marcuscommit f6a9bafb21d26b2e7d767b392bea0f60c31701d5
Author: Marcus Shawcroft marcus.shawcr...@arm.com
Date: Fri Jun 6 14:26:50 2014 +0100
[AArch64] Fix REG_CFA_RESTORE mode.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index
Fixing various white space issues in the frame layout code. Committed.
/Marcusdiff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index e7f455b..3eb18e9 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1917,7 +1917,6 @@
On 10 June 2014 09:53, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
* config/aarch64/aarch64-simd.md (aarch64_sqdmulh_lanemode):
New expander.
(aarch64_sqrdmulh_lanemode): Likewise.
(aarch64_sqrdmulh_lanemode): Rename to...
(aarch64_sqrdmulh_lanemode_interna): ...this.
On 10 June 2014 15:03, Jiong Wang jiong.w...@arm.com wrote:
This patch add testcases for various aarch64 prologue/epilogue scenarios.
It will make sure our later frame code refine and improvement will not cause
any regression.
OK for trunk?
Thanks.
gcc/testsuite/
*
On 10 June 2014 15:29, Christophe Lyon christophe.l...@linaro.org wrote:
Hello,
This commit (211211) causes gcc.target/aarch64/vect-mull.c execution
test to FAIL for target aarch64_be-none-elf.
(tested using qemu)
Yep, that is exactly what Bin said in his original submission..
/Marcus
On
On 10 June 2014 16:37, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch corrects the insn types used for scheduling for some of our move
patterns.
GP-FP moves have type f_mcr
FP-GP moves have type f_mrc
GP-GP moves have type mov_reg
FP-FP moves have type fmov.
On 5 June 2014 09:29, Ramana Radhakrishnan ramana@googlemail.com wrote:
Thanks Richard for the comments. My primary intention here is to use
TARGET_SPILL_CLASS to make FP_REGS as spill registers.
Do you think
AArch64 can benefit from TARGET_SPILL_CLASS hook. I agree that just
increasing
I've committed to the attached to clarify the stack layout comment.
/Marcusdiff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 961e5c9..3348cf2 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2078,37 +2078,35 @@
I've just committed the attached to co-locate saved_varargs_size with
the other target specific frame related state...
/Marcus
2014-06-05 Marcus Shawcroft marcus.shawcr...@arm.com
* config/aarch64/aarch64.h (machine_function): Move
saved_varargs_size from here
the
handling of X29/X30.
Commmitted
/Marcus
2014-06-05 Marcus Shawcroft marcus.shawcr...@arm.com
* config/aarch64/aarch64.c (SLOT_NOT_REQUIRED, SLOT_REQUIRED): Define.
(aarch64_layout_frame): Use SLOT_NOT_REQUIRED and SLOT_REQUIRED.
(aarch64_register_saved_on_entry
This patch restructures the callee slave slot allocation code to handle
X29 and X30 consistently with the other core registers. The patch also
ensures that the offset recorded for X30 is accurate.
Committed.
/Marcus
2014-06-05 Marcus Shawcroft marcus.shawcr...@arm.com
Jiong
the STACK_BOUNDARY rounded locations of the frame_pointer, the
location of the hard_frame_pointer and the frame_size once and cache
them in the machine.frame structure.
Committed
/Marcus
2014-06-05 Marcus Shawcroft marcus.shawcr...@arm.com
* config/aarch64/aarch64.h (aarch64_frame): Add
On 27 May 2014 23:27, Kugan kugan.vivekanandara...@linaro.org wrote:
Due to the cost changes in IRA, now part of the arguments(v0.d[1]) for
multf3 ends up in stack. Reason for this us, in IRA, assign_hard_reg,
while iterating for the cost for assigning register to reg:TI 99,
allocates
On 3 June 2014 02:05, Andrew Pinski apin...@cavium.com wrote:
This factors out the IF_THEN_ELSE from aarch64_rtx_costs as that function was
getting too large.
OK? Build and tested for aarch64-elf with no regressions.
OK, Thanks /Marcus
On 3 June 2014 02:05, Andrew Pinski apin...@cavium.com wrote:
- if (GET_CODE (op0) == NE
- || GET_CODE (op0) == EQ)
+ if (cmpcode == NE
+ || cmpcode == EQ)
Those two can go back on one line ?
}
- else if (GET_CODE (op0) == LT
-
On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote:
Missing patch.
On Wed, May 28, 2014 at 3:02 PM, bin.cheng bin.ch...@arm.com wrote:
Hi,
I was surprised that GCC didn't support addressing modes like
[REG+OFF]/[REG_REG] for instructions ldr/str in vectorization scenarios.
The
On 3 June 2014 11:21, Alan Lawrence alan.lawre...@arm.com wrote:
Ok, this fixes it. We'll output an ext...#0, which is little more than a
MOV,
but that seems appropriate in the circumstance.
Regression tested check-gcc and check-g++ on aarch64-none-elf and
aarch64_be-none-elf.
Ok for
On 3 June 2014 12:19, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
* config/aarch64/aarch64.c (aarch64_evpc_ext): Allow+handle
location==0.
?
Allow and handle location == 0.
Otherwise OK
/Marcus
On 3 Jun 2014, at 18:08, Charles Baylis charles.bay...@linaro.org wrote:
On 3 June 2014 12:08, Marcus Shawcroft marcus.shawcr...@gmail.com wrote:
On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote:
So is it OK?
2014-05-28 Bin Cheng bin.ch...@arm.com
* config
On 28 May 2014 23:58, Andrew Pinski andrew.pin...@caviumnetworks.com wrote:
Hi,
The problem here is aarch64_rtx_costs for IF_THEN_ELSE does not
handle the case where the first operand is a non comparison. This
happens when the combine is combing a few RTLs and calling
set_src_cost to check
On 29 May 2014 13:44, Alan Lawrence alan.lawre...@arm.com wrote:
This adds three new sets of qualifiers to aarch64-builtins.c, and uses the
already-present-but-unused USHIFTIMM.
gcc/ChangeLog:
* gcc/config/aarch64/aarch64-builtins.c
(aarch64_types_binop_uus_qualifiers,
On 29 May 2014 13:47, Alan Lawrence alan.lawre...@arm.com wrote:
This adds another set of qualifiers to aarch64-builtins.c, and removes more
casts from arm_neon.h, for the suqadd, ushl, urshl, urshr_n, ushll_n, and
sshl intrinsics.
gcc/ChangeLog:
*
On 30 May 2014 09:14, Tom de Vries tom_devr...@mentor.com wrote:
Marcus,
when building for aarch64-linux-gnu with --enable-checking=yes,rtl, I run
into the following error:
OK, thanks Tom. /Marcus
On 26 February 2014 02:25, Andrew Pinski apin...@cavium.com wrote:
Hi,
This is the final patch which adds support for the dynamic linker and
multi-lib directories for ILP32. I did not change multi-arch support as
I did not know what it should be changed to and internally here at Cavium,
we
On 2 May 2014 13:27, Kugan kugan.vivekanandara...@linaro.org wrote:
+2014-05-02 Kugan Vivekanandarajah kug...@linaro.org
+
+ * config/aarch64/aarch64.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New
+ define.
+ * config/aarch64/aarch64-protos.h
On 22 May 2014 14:03, Jiong Wang jiong.w...@arm.com wrote:
gcc/testsuite
gcc.target/aarch64/tail-indirect-call_1.c: New test.
That should be tail_indirect_call_1.c as requested in the previous
review. Otherwise this is OK to commit.
/Marcus
On 20 May 2014 18:37, Carrot Wei car...@google.com wrote:
Hi James
Thank you for pointing this out. In the new patch I removed the
modification of vqdmulh_n_s32 and vqdmulhq_n_s32.
Passed dejagnu testing on aarch64 qemu again. OK for trunk, 4.9 and 4.8?
2014-05-20 Guozhi Wei
On 21 May 2014 09:28, Marcus Shawcroft marcus.shawcr...@gmail.com wrote:
On 20 May 2014 18:37, Carrot Wei car...@google.com wrote:
Hi James
Thank you for pointing this out. In the new patch I removed the
modification of vqdmulh_n_s32 and vqdmulhq_n_s32.
Passed dejagnu testing on aarch64
Hi,
On 18 March 2014 14:13, Jiong Wang jiong.w...@arm.com wrote:
* config/aarch64/predicates.md (aarch64_call_insn_operand): New
predicate.
* config/aarch64/constraints.md (Ucs, Usf): New constraints.
* config/aarch64/aarch64.md (*sibcall_insn, *sibcall_value_insn): Adjust
for
On 15 May 2014 01:10, Kugan kugan.vivekanandara...@linaro.org wrote:
Hi All,
AAarch64 back-end defines GENERAL_REGS and CORE_REGS with the same set
of register. Is there any reason why we need this?
Nope an artifact of the early evolution of AArch64. Long ago CORE_REGS
did not include SP.
On 15 May 2014 06:54, Kugan kugan.vivekanandara...@linaro.org wrote:
Hi All,
In AArch64 back-end, BASE_REG_CLASS is defined to be POINTER_REGS.
Shouldn’t this be GENERAL_REGS?
Hi Kugan,
Are you aware of any problem caused by BASE_REG_CLASS being POINTER_REGS?
GENERAL_REGS and POINTER_REGS
On 1 May 2014 17:57, Yufeng Zhang yufeng.zh...@arm.com wrote:
On AArch64, the singleton vector types int64x1_t, uint64x1_t and
float64x1_t exported by arm_neon.h are defined to be the same as their
base types. This results in incorrect application of parameter passing
rules to arguments of
On 8 May 2014 18:41, Ian Bolton ian.bol...@arm.com wrote:
gcc/testsuite
* gcc.target/aarch64/vdup_lane_2.c (force_simd): Emit an
actual instruction to move into the allocated register.
This macro is attempting to force a value to a particular class of
register, we don't need
On 1 April 2014 23:24, Richard Henderson r...@redhat.com wrote:
Comments? If approved, should this go in for 4.9, or wait for stage1?
Certainly it's self-contained...
Hi, I think this should go in, with the cache line increased to 128 as
discussed with Andrew.
/Marcus
On 30 April 2014 18:42, Ryan Mansfield rmansfi...@qnx.com wrote:
aarch64_function_profiler was removed in rev203028 but the prototype was
left behind. If OK, can someone apply? Thanks.
Regards,
Ryan Mansfield
2014-04-30 Ryan Mansfield rmansfi...@qnx.com
*
On 23 April 2014 21:22, Alan Lawrence alan.lawre...@arm.com wrote:
2014-03-27 Alan Lawrence alan.lawre...@arm.com
* config/aarch64/aarch64-builtins.c
(aarch64_types_binopv_qualifiers,
TYPES_BINOPV): New static data.
* config/aarch64/aarch64-simd-builtins.def
On 15 May 2014 16:52, Alan Lawrence alan.lawre...@arm.com wrote:
2014-05-15 Alan Lawrence alan.lawre...@arm.com
* config/aarch64/aarch64-simd.md
(aarch64_revREVERSE:rev-opmode):
New pattern.
* config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
This series is OK.
/Marcus
On 27 March 2014 17:33, James Greenhalgh james.greenha...@arm.com wrote:
Hi,
This patch series improves the costing model in the AArch64 backend to
match a number of new idioms.
This patch is a combination of a series I had been working on, with the
cost-model
On 16 May 2014 09:26, James Greenhalgh james.greenha...@arm.com wrote:
2014-05-15 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64.c (aarch64_rtx_mult_cost): Fix FNMUL case.
OK /Marcus
On 14 May 2014 22:30, Kyle McMartin kmcma...@redhat.com wrote:
The toolchain would like PT_GNU_STACK in our objects for all
architectures to make it explicit whether we are requesting an
executable stack or not.
2014-05-14 Kyle McMartin k...@redhat.com
*
On 6 May 2014 15:25, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2014-05-06 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config.gcc (aarch64*-*-*): Use ISA flags from aarch64-arches.def.
Do not define target_cpu_default2 to generic.
OK /Marcus
On 29 April 2014 03:37, Kugan kugan.vivekanandara...@linaro.org wrote:
On 28/04/14 21:01, Ramana Radhakrishnan wrote:
On 04/26/14 11:57, Kugan wrote:
Attached patch implements TARGET_ATOMIC_ASSIGN_EXPAND_FENV for AARCH64.
With this, atomic test-case gcc.dg/atomic/c11-atomic-exec-5.c now PASS.
On 2 May 2014 11:06, Marcus Shawcroft marcus.shawcr...@gmail.com wrote:
Kugan, I've not looked at the respin in detail yet, but it has just
occurred to me that the sequence used here to set FPCR is
insufficient. The architecture reference manual requires that any
write to FPCR must
Hi Kugan, Thanks for this, couple of comments inline:
On 26 April 2014 11:57, Kugan kugan.vivekanandara...@linaro.org wrote:
gcc/
+2014-04-27 Kugan Vivekanandarajah kug...@linaro.org
+
+ * config/aarch64/aarch64.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New
+ define.
+ *
On 22 April 2014 10:36, Zhenqiang Chen zhenqiang.c...@linaro.org wrote:
+float f1 (float a, float b, float c, float d)
+{
+ if (a 0.0)
+return c;
+ else
+return 2.0;
+}
+
+double f2 (double a, double b, double c, double d)
+{
+ if (a b)
+return c;
+ else
+
On 16 April 2014 09:12, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 15/04/14 18:45, Eric Christopher wrote:
Testcase weirdness?
for (i 0; i N; ++i)
{
arr[i] = i;
expect[i] = __builtin_bswap64 (i);
if (y) /* Avoid vectorisation. */
abort ();
}
i
On 28 March 2014 15:31, Alan Lawrence alan.lawre...@arm.com wrote:
This adds DejaGNU tests of the existing AArch64 vuzp_* intrinsics, both
checking
the assembler output and the runtime results. Test bodies are in separate
files
ready to reuse for ARM in the third patch.
Putting these in a
On 28 March 2014 15:36, Alan Lawrence alan.lawre...@arm.com wrote:
This patch replaces the temporary inline assembler for vtrn[q]_* in
arm_neon.h with equivalent calls to __builtin_shuffle. These are matched by
existing patterns in aarch64.c (aarch64_expand_vec_perm_const_1), outputting
the
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