RE: [PATCH, testsuite] MIPS: Upgrade to R2 for -mnan=2008 and -mabs=2008.

Toma Tabacu > The -mnan=2008 and -mabs=2008 options are not supported on pre-R2 targets. > This results in failures for tests which use these options, such as > nan-2008.c, > fabs-2008.c etc. > > This patch makes the testsuite upgrade to R2 if -mnan=2008 and -mabs=2008

RE: [PATCH, testsuite] MIPS: Skip msa-builtins-err.c if there is no assembly output.

Toma Tabacu writes: > The msa-builtins-err.c test is failing in the following configuration: > -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects > This is because the errors it is checking for are triggered by assembly > generation, which is prevented by

RE: [PATCH] MIPS MSA: Fix ICE when using out-of-range values to intrinsics

Robert Suchanek writes: > The revised patch attached below. > > Regards, > Robert > > gcc/ > * config/mips/mips.c (mips_expand_builtin_insn): Check input ranges >of literal integer arguments. > > gcc/testsuite/ > > *

RE: [PATCH] MIPS MSA: Fix ICE when using out-of-range values to intrinsics

Robert Suchanek writes: > The patch primarily fixes an ICE with out-of-range values to the > __builtin_msa_insve* intrinsics. > > The compiler segfaults in mips_legitimize_const_move () as it tries to > split symbol that has NULL_RTX value and gets here because the

RE: [PATCH,testsuite] MIPS: Downgrade from R6 to R5 to prevent redundant testing of branch-cost-1.c.

Moore, Catherine writes: > > gcc/testsuite/ChangeLog: > > > > 2016-11-15 Toma Tabacu > > > > * gcc.target/mips/branch-cost-1.c (dg-options): Use > > (HAS_MOVN) instead > > of isa>=4, in order to downgrade to R5. > > > > diff --git

RE: [PATCH] MIPS: If a test in the MIPS testsuite requires standard library support check the sysroot supports the required test options.

Toma Tabacu writes: > The version below has a more detailed comment about marking tests as > unsupported. > Matthew, does it look good to you ? > > Also, should we document our expectations for the rest of do_what's > format (elements 0 and 2) ? I don’t think it is

RE: [PATCH] MIPS: If a test in the MIPS testsuite requires standard library support check the sysroot supports the required test options.

Toma Tabacu writes: > Hi, > > The patch below is a rebased version of Andrew's patch plus a few more changes > to test options. > > I have tested Andrew's patch by passing -msoft-float to the testsuite without > having a soft-float library available, and saw that the >

RE: [PATCH,gcc/MIPS] Make loongson3a use fused madd.d

il.com] > Sent: 17 November 2016 03:01 > To: Matthew Fortune > Cc: gcc-patches@gcc.gnu.org; catherine_mo...@mentor.com > Subject: Re: [PATCH,gcc/MIPS] Make loongson3a use fused madd.d > > ping... > > On Thu, Nov 3, 2016 at 7:58 PM, Paul Hua <paul.hua...@gmail.com> wrote: >

RE: [PATCH 3/3] MIPS/GCC: Mark trailing labels with `.insn'

Maciej Rozycki <maciej.rozy...@imgtec.com> writes: > On Mon, 14 Nov 2016, Matthew Fortune wrote: > > > > This however requires the correct annotation of branch targets as > > > code, because the ISA mode is not relevant for data symbols and is > > > the

RE: [PATCH 4/4] MIPS16/GCC: Emit explicit JRC from`casesi_internal_mips16_' insn

Maciej Rozycki writes: > gcc/ > * config/mips/mips.md (casesi_internal_mips16_): > Explicitly switch between JR and JRC for the table jump. Adjust > instruction count. > --- > OK to apply? OK. Thanks, Matthew

RE: [PATCH 3/4] MIPS16/GCC: Improve `casesi_internal_mips16_'s instruction count estimate

Maciej Rozycki writes: > gcc/ > * config/mips/mips.md (casesi_internal_mips16_): Set > `insn_count' to 11 rather than 16. > --- > OK to apply? Good catch again. OK. Thanks, Matthew

RE: [PATCH 2/4] MIPS16/GCC: Correct `casesi_internal_mips16_'s RTL pattern

Maciej Rozycki writes: > gcc/ > * config/mips/mips.md (casesi_internal_mips16_): Use the > `ltu' rather than `leu' operation in the RTL pattern > --- > OK to apply? Good spot. OK to commit. Thanks, Matthew

RE: [PATCH 1/4] MIPS16/GCC: Fix DImode `casesi_internal_mips16_' assembly instructions

Maciej Rozycki writes: > gcc/ > config/mips/mips.md (casesi_internal_mips16_): Add missing >instruction prefixes throughout. Correct formatting. > > gcc/testsuite/ > * gcc.target/mips/code-readable-4.c (dg-final): Expect `dla' >

RE: [PATCH] microMIPS/GCC: Fix PIC call relaxation

Maciej Rozycki writes: > Fix `-mrelax-pic-calls' support for microMIPS code where the relocation > produced is supposed to be R_MICROMIPS_JALR rather than R_MIPS_JALR. > The lack of short delay support comes from a missed update to this code > for microMIPS support and

RE: [PATCH] MIPS/GCC: Mark text contents as code or data

Maciej Rozycki writes: > gcc/ > * config/mips/mips-protos.h (mips_set_text_contents_type): New > prototype. > * config/mips/mips.h (ASM_OUTPUT_BEFORE_CASE_LABEL): New macro. > (ASM_OUTPUT_CASE_END): Likewise. > * config/mips/mips.c

RE: [PATCH 3/3] MIPS/GCC: Mark trailing labels with `.insn'

Maciej Rozycki writes: > This however requires the correct annotation of branch targets as code, > because the ISA mode is not relevant for data symbols and is therefore > not recorded for them. I wonder if it would have been possible to add the ISA mode to data

RE: [PATCH 2/3] MIPS/GCC/test: Implement `-mcode-readable=yes' option test

Maciej Rozycki writes: > gcc/testsuite/ > * gcc.target/mips/mips.exp (mips_option_tests): Add > `-mcode-readable=yes' array element. > --- > OK to apply? OK, thanks. Matthew

RE: [PATCH 1/3] MIPS/GCC/test: Implement `-mmicromips' option test

Maciej Rozycki writes: > gcc/testsuite/ > * gcc.target/mips/mips.exp (mips_option_tests): Add > `-mmicromips' array element. OK, thanks. Matthew

RE: [PATCH 0/3] MIPS/GCC: Changes for `.insn' assembly annotation

Maciej Rozycki writes: > This small patch series addresses an issue uncovered by a recent > binutils master branch update, scheduled for the upcoming 2.28 release, > where we fail to annotate stray code labels -- generally produced for > code marked as unreachable --

RE: [MIPS] Enable descriptors for nested functions in Ada

Eric Botcazou writes: > Similarly to x86, PowerPC and SPARC, this enables the use of custom run- > time descriptors in Ada, thus eliminating the need for trampolines and > executable stack in presence of pointers to nested functions. > > Unfortunately I don't have access

RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need branch-likely instructions.

Toma Tabacu writes: > I've noticed that there is a typo in my surname in the ChangeLog entry > (in the name and in the email address). Apologies, corrected. Matthew

RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need branch-likely instructions.

Toma Tabacu <toma.tab...@imgtec.com> writes: > > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > > ow...@gcc.gnu.org] On Behalf Of Toma Tabacu > > Sent: 04 November 2016 15:25 > > To: Matthew Fortune; gcc-patches@gcc.gnu.org > > Cc: catherine_mo..

RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need branch-likely instructions.

Toma Tabacu writes: > The gcc.target/mips/wrap-delay.c test was failing on mips-img-* > toolchains > because it was using -mbranch-likely with an R6 target, and branch- > likely > instructions were removed in R6. > > This patch makes the testsuite downgrade to R5 if the

RE: [PATCH,gcc/MIPS] Make loongson3a use fused madd.d

Paul Hua writes: > Loongson3a has 4 operand fused madd instrcution. This patch set > loongson3a use fused madd.d. Hi Paul, Thanks for the fix. I was vaguely aware that this was wrong for loongson-3a but never confirmed it. I suspect this change is mechanical enough that

RE: Fix MIPS port WRT sprintf and fallthru warnings

Jeff Law writes: > The fallthrus in mips16_constant_cost are pretty obvious. One buffer > overflow in mips16_build_call_stub and one obvious fallthru comment > adjustment in mips16_build_call_stub. > > The usual stuff. Installing. Thanks Jeff. Matthew

RE: [RFC,PATCH,testsuite]

<matthew.fort...@imgtec.com> wrote: > Richard Biener <richard.guent...@gmail.com> writes: > > On Sun, Nov 23, 2014 at 10:15 AM, Matthew Fortune > > <matthew.fort...@imgtec.com> wrote: > > > I'd therefore like to apply the following. Any suggestions o

RE: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439

Richard Biener writes: > On Sat, Oct 1, 2016 at 3:35 AM, Doug Gilmore > wrote: > > My commit r240439 didn't handle the situation where setting --param > > prefetch-latency=0 can cause the prefetch address to be the same as > > the original

RE: [PATCH] MIPS/doc: Fix `d' constraint description

Maciej Rozycki writes: > Revert a part of the `d' constraint documentation update made with > commit 111868 ("Use define_constraint for MIPS"), > , > ,

RE: [PATCH] Fix PR tree-optimization/77654

Doug Gilmore writes: > > From: Richard Biener [rguent...@suse.de] > > Sent: Thursday, September 22, 2016 12:43 AM > > To: Doug Gilmore > > Cc: gcc-patches@gcc.gnu.org; rgue...@gcc.gnu.org > > Subject: RE: [PATCH] Fix PR tree-optimization/77654 > > > > On Wed, 21 Sep 2016,

RE: [PATCH] Disable -mbranch-likely for -Os when targetting generic architecture

Robert Suchanek writes: > Hi Catherine, > > Apologies for the (very) late reply. > It appears that I never replied to the last message. > > > > gcc/ > > > * config/mips/mips-cpus.def: Replace PTF_AVOID_BRANCHLIKELY with > > > PTF_AVOID_BRANCHLIKELY_ALWAYS for

RE: [PATCH 4/4] [MIPS] Add tests for MSA

Hi Robert, Sorry for the long delay. Just a couple of cleanup bits in here but otherwise OK. Unless you want me to read through again please go ahead and commit once you've addressed the comments. We could do more in mips.exp for inferring -mfp64 and -mhard-float but I'm not sure it is worth it

RE: [RFC,PATCH] Using equivalences to help eliminate_regs_in_insn

Vladimir N Makarov <vmaka...@redhat.com> writes: > On 09/06/2016 11:22 AM, Matthew Fortune wrote: > > There is an implementation that optimises a single set but not one for > > a REG_EQUAL. Do you have any recollection of this code and do you > > think there was a

[PATCH,committed] Infer architecture from ABI for mips-img* and mips-mti*

--- gcc/ChangeLog | 7 +++ gcc/config.gcc | 8 2 files changed, 15 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8527518..9b39906 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-09-14 Matthew Fortune <matthew.fort...@imgtec.

[PATCH] PR java/71917

Hi, Although libjava is currently on death row, here is a patch to (correctly) fix mips64el in the java interpreter. This restores sparc64 BE java support based on the report[1] that reverting my original patch fixes the bug (I have not rerun this on spark64 BE as we are back to the original code

[RFC,PATCH] Using equivalences to help eliminate_regs_in_insn

I've found a case of suboptimal code coming from LRA when we have a large frame and have the frame grow downwards with MIPS. A good testcase for this is the qsort benchmark from the automotive section of mibench[1]. Any frame access where the offset is not supported as an add-immediate should

RE: [PATCH] Delete GCJ

Andrew Haley writes: > As discussed. I think I should ask a Global reviewer to approve this > one. For obvious reasons I haven't included the diffs to the deleted > gcc/java and libjava directories. The whole tree, post GCJ-deletion, is > at

RE: [PATCH][mips] Add support for mips*r6-*-musl

Szabolcs Nagy writes: > Add the musl dynamic linker names for mips r6. > > It seems DRIVER_SELF_SPECS sets the default mips isa > (MIPS_DEFAULT_ISA_LEVEL_SPEC) on *-mti-linux* or *-mti-elf, but not on > gnu linux targets (see config/mips/mti-linux.h vs config/mips/gnu- >

RE: [PATCH][mips] Fix linux header use in libgcc

Szabolcs Nagy writes: > gcc should use libc headers, not kernel headers. > > libgcc/ > 2016-08-24 Szabolcs Nagy > > * config/mips/linux-unwind.h: Use sys/syscall.h. OK. Thanks for the fix. Matthew

[MIPS, committed] Skip gcc.dg/loop-8.c

MIPS creates more invariants than gcc.dg/loop-8.c expects. There is no way to represent what the original test was trying to verify given the additional invariants being moved out of the loop. Thanks, Matthew gcc/ PR rtl-optimization/9 * gcc.dg/loop-8.c: Skip for MIPS due to

[MIPS,committed] Use create_tmp_var_raw in mips_atomic_assign_expand_fenv

I have applied the MIPS specific fix for PR65345. It is a mechanical change. This fixes the MIPS failures in atomic/pr65345-4.c. gcc/ PR c/65345 * config/mips/mips.c (mips_atomic_assign_expand_fenv): Use create_tmp_var_raw instead of create_tmp_var. Thanks, Matthew

RE: [PATCH] Fix (parts of) PR68273

Richard Biener writes: > The following patch avoids overaligned types created from IPA parameter > replacement. It is said to help mipsel which still suffers from the > backend-looks-at-type-alignment-for-parameter-passing-ABI bug. > > Bootstrap and regtest pending on

RE: [PATCH] Fix FFI return type for proxy classes

Tom Tromey <t...@tromey.com> writes: > >>>>> "Matthew" == Matthew Fortune <matthew.fort...@imgtec.com> writes: > > Matthew> Tested on: x86_64-pc-linux-gnu (default and -m32), mips-linux-gnu > Matthew> mipsel-linux-gnuabi64 with no regressions

RE: [PATCH] Fix FFI return type for closures in the java interpreter

Tom Tromey <t...@tromey.com> writes: > >>>>> "Matthew" == Matthew Fortune <matthew.fort...@imgtec.com> writes: > > Matthew> Sorry for the long delay... > > No problem. > > >> This is ok. > >> Could you check? I th

[PATCH] Fix FFI return type for proxy classes

Hi, As mentioned in: https://gcc.gnu.org/ml/gcc-patches/2016-06/msg01827.html there is a bug in lang/reflect/natVMProxy.cc where the return types are not promoted to ffi_arg for integer types smaller than a word. This bug will not show up on little endian architectures as the issue gets fixed

RE: [PATCH] Fix FFI return type for closures in the java interpreter

Tom Tromey <t...@tromey.com> writes: > >>>>> "Matthew" == Matthew Fortune <matthew.fort...@imgtec.com> writes: > > Matthew> I'm not sure this will matter if the only arch is x86 as > Matthew> ffi_arg will be 32-bit anyway there. > > Ah

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

ent: 10 August 2015 13:15 > > To: catherine_mo...@mentor.com; Matthew Fortune > > Cc: gcc-patches@gcc.gnu.org > > Subject: [PATCH 3/4] Add support to run auto-vectorization tests for > > multiple > > effective targets > > > > Hi, > > > > Th

RE: [PATCH] Fix FFI return type for closures in the java interpreter

Tom Tromey <t...@tromey.com> writes: > >>>>> "Matthew" == Matthew Fortune <matthew.fort...@imgtec.com> writes: > Matthew> I've identified a latent bug in the java interpreter that affects > MIPS > Matthew> n32 and n64 ABIs both little and

[PATCH] Fix FFI return type for closures in the java interpreter

Hi, I've identified a latent bug in the java interpreter that affects MIPS n32 and n64 ABIs both little and big endian and, I presume, any 64-bit big endian target with int as 32-bit. A full description is in my original post: https://gcc.gnu.org/ml/java-patches/2016-q2/msg00020.html Patch

RE: [PATCH][MIPS] Add support for P6600

Hi Robert, A few comments inlined. I'd like to review again and/or let Catherine comment before commit. Thanks, Matthew > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c > index 06acd30..cbe1007 100644 > --- a/gcc/config/mips/mips.c > +++ b/gcc/config/mips/mips.c > @@ -18496,6

RE: [PATCH][MIPS] Remove "new" MIPS TLS access patterns

Robert Suchanek writes: > The below finishes the revert of r137670 that was already partially reverted > in r137734 as part of PR target/35802. > > It would appear that the revert was not completed because of a spill failure > at the time. As LRA can handle the 'v'

RE: [PATCH][MIPS] P5600 scheduler fix

Robert Suchanek writes: > gcc/ > * config/mips/p5600.md (p5600_fpu_fadd): Remove checking for > `fabs' and `fneg' type attributes. > (p5600_fpu_fabs): Add `fmove' to the comment. OK. Thanks, Matthew

RE: [PATCH][MIPS] Add -mgrow-frame-downwards option

by about 0.5% in average case for -Os, hence, it > > is good to turn the option on by default. > > > > Ok to apply? > > > > Regards, > > Robert > > > > gcc/ > > > > 2016-05-20 Matthew Fortune <matthew.fort...@imgtec.com> > > &

RE: [MIPS,committed] Update MIPS P5600 processor definition to avoid IMADD

Maciej Rozycki <maciej.rozy...@imgtec.com> writes: > On Wed, 4 May 2016, Matthew Fortune wrote: > > > diff --git a/gcc/config/mips/mips-cpus.def > > b/gcc/config/mips/mips-cpus.def index 17034f2..5df9807 100644 > > --- a/gcc/config/mips/mips-cpus.def > >

RE: [PATCH][MIPS] Enable LSA/DLSA for MSA

Robert Suchanek > The below enables LSA/DLSA instructions for -mmsa. > > Ok to commit? OK. There is a corresponding testsuite change needed for this as some code quality tests change if LSA is available. This is the HAS_LSA 'ghost' option in mips.exp. I'm happy to

RE: [PATCH][MIPS] Correct latency of loads in M5100

Robert Suchanek writes: > A small patch to correct the latency for M5100. > > Ok to commit? > * config/mips/m5100.md (m51_int_load): Update the latency to 2. OK. Matthew

RE: [MIPS r5900] libgcc floating point fixes

r work on r5900 vector support which will certainly need copyright assignment so this could be a good time to sort it out. Sorry for not checking this earlier so this could already be in progress. Let me know and I'll send the forms. Thanks, Matthew > > Thanks and regards, > -W Y >

RE: [PATCH 2/4] [MIPS] Add pipeline description for MSA

Robert Suchanek writes: > > gcc/ChangeLog: > > * config/mips/i6400.md (i6400_fpu_intadd, i6400_fpu_logic) > (i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float, i6400_fpu_store) > (i6400_fpu_long_pipe, i6400_fpu_logic_l, i6400_fpu_float_l) >

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

atch as it has had many major contributors now. I believe this includes at least the following for the implementation but fewer for the testsuite updates: Robert Suchanek Sameera Deshpande Matthew Fortune Graham Stott Chao-ying Fu Otherwise, OK to commit! Matthew > > > > mips_gen_co

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

rg] On Behalf Of Robert Suchanek > > Sent: 10 August 2015 13:15 > > To: catherine_mo...@mentor.com; Matthew Fortune > > Cc: gcc-patches@gcc.gnu.org > > Subject: [PATCH 3/4] Add support to run auto-vectorization tests for > > multiple effective targets > > &g

RE: [PATCH] MIPS: In mips_print_address_operand pass the mode argument to mips_classify_address

Andrew Bennett writes: > gcc/ > * config/mips/mips.c (mips_print_operand_address): Pass the mode > argument to > mips_classify_address. Changelog content should wrap at 74 chars. > I have tested the patch on the mips-mti-elf toolchain and there have > been

RE: [PATCH] MIPS: Ensure that lo_sums do not contain an unaligned symbol

Hi Andrew, Thanks for working on this it is a painful area. There's a bit more to do but this is cleaning up some sneaky bugs. Can you create a GCC bugzilla entry if you haven't already as we should record where these bugs exist and when they are fixed? See my comments but I think that you are

[MIPS,committed] Update MIPS P5600 processor definition to avoid IMADD

| 5 + gcc/config/mips/mips-cpus.def | 8 +++- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 623b269..ea32ba5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2016-06-04 Matthew Fortune <matthew.f

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Robert, Apologies for the long delay again. This patch is hard to get through. My comments are not all in source sequence but I've tried to keep them short. With a few minor things fixed and some trivial style issues done then this is ready to go. I've left a number of things to look at

RE: [Patch, MIPS] Patch for PR 68273 (user aligned variable arguments)

Steve Ellcey writes: > Here is a new patch for PR 68273. The original problem with gsoap has > been fixed by changing GCC to not create overly-aligned variables in > the SRA pass but the MIPS specific problem of how user-aligned variables > are passed to functions remains. >

RE: [MIPS r5900] libgcc floating point fixes

Woon yung Liu wries > Bump! Sorry, but could I please get an answer? I'm willing to update the > patch without > credit, if necessary. Hi WY, Apologies for exceptionally slow response. The patch you referenced is mostly OK but I would like to get the MIPS16 check changed to

RE: Remove -fshort-double (PR60410)

Jeff Law writes: > On 02/05/2016 12:31 PM, Bernd Schmidt wrote: > > This patch fixes PR60410 by removing -fshort-double. Nick earlier > > propsed a fix for the crash, but Richard B suggested removing the option > > entirely, and I'd agree with that. It's a pointless ABI-changing

RE: [Patch, MIPS] Patch for PR 68400, a mips16 bug

Richard Sandiford writes: > "Steve Ellcey " writes: > > Here is a patch for PR6400. The problem is that and_operands_ok was > > checking > > one operand to see if it was a memory_operand but MIPS16 addressing is more > > restrictive than what the

RE: [PATCH] Skip re-computing the mips frame info after reload completed

Bernd Edlinger <bernd.edlin...@hotmail.de> writes: > Matthew Fortune <matthew.fort...@imgtec.com> writes: > > Has the patch been tested beyond just building GCC? I can do a > > test run for you if you don't have things set up to do one yourself. > > I bui

RE: [PATCH] Skip re-computing the mips frame info after reload completed

Bernd Edlinger writes: > this patch skips the redundant re-computing of the frame info after reload > completed. > > I looked at all available targets initial_elimination_offset functions: > > All of them currently use either a trivial function of >

RE: [PATCH][MIPS] Migrate reduction optabs in mips-ps-3d.md

Alan Lawrence writes: > On 07/01/16 12:47, Alan Lawrence wrote: > > Here's an updated version, also covering the min/max patterns I missed > before. > > I've now managed to do some testing with a stage 1 compiler, by > > compiling all tests in gcc.dg/vect at -O2

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Robert, Thanks for the update and detailed comments. There are a couple of things which I think still need addressing based solely on your comments but generally the changes seem to have simplified things which is nice to see. I haven't read the patch again yet and given the changes it looks

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

Hi Robert, Do you have an updated version of this patch? It no longer applies cleanly. Thanks, Matthew > -Original Message- > From: Robert Suchanek > Sent: 05 January 2016 16:17 > To: catherine_mo...@mentor.com; Matthew Fortune > Cc: gcc-patches@gcc.gnu.org > Subje

RE: [PATHCH] Disable inline asm for in-tree mpfr (PR69134)

Bernd Edlinger writes: > an in-tree mpfr build enables inline asm code, which makes the mips-bootstrap > fail, > because at least mpfr 2.4.2 uses the "=h" constraint but in > config/mips/constraints.md > we find: "Formerly the @code{hi} register. This constraint is

RE: [PATCH] Fix pr69012 ICE on building libgfortran for mips

Bernd Edlinger writes: > Hi, > > On 30.12.2015 15:31, Richard Sandiford wrote: > > I think the problem is deeper than that though. The instructions that > > are triggering the ICE are only generated by the prologue, so this > > means that we're trying to lay out the

RE: [PATCH][MIPS] Reorder function types

Robert Suchanek writes: > gcc/ > * config/mips/mips-ftypes.def: Sort to lexicographical order. The patch is fine. I don't know what we can/should commit at this stage. Catherine: Any idea what is acceptable? I'd think this kind of small change to be OK and make

RE: [Patch, MIPS] Remove definition of TARGET_PROMOTE_PROTOTYPES

Steve Ellcey writes: > On Tue, 2015-11-10 at 15:57 -0800, Steve Ellcey wrote: > > 2015-11-10 Steve Ellcey > > > > * config/mips/mips.c (mips_promote_function_mode): New function. > > (TARGET_PROMOTE_FUNCTION_MODE): Define as above function.

RE: [PATCH] MIPS/GCC/doc: Reorder `-mcompact-branches='

Maciej Rozycki writes: > Move the `-mcompact-branches=' option out of the middle of a block of > floating-point options. The option is not related to FP in any way. > Place it immediately below other branch instruction selection options. > > gcc/ > *

RE: [RFA] Compact EH Patch

> This patch implements a more compact format for exception handling data. > Although I don't > have recent numbers for the amount of compression achieved, an earlier > measurement showed > a 30% reduction in the size of EH data for libstdc++. > > A design document detailing the new format is

RE: [PATCH, mips]: Use ROUND_UP and ROUND_DOWN macros

Uros Bizjak writes: > Fairly trivial patch that introduces no functional changes. > > * config/mips/mips.h (MIPS_STACK_ALIGN): Implement using > ROUND_UP macro. > * config/mips/mips.c (mips_setup_incoming_varargs): Use > ROUND_DOWN to calculate off. >

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Robert, Next batch of comments. This set covers the rest of mips-msa.md. >+++ b/gcc/config/mips/mips-msa.md >+(define_expand "vec_perm" >+ [(match_operand:MSA 0 "register_operand") >+ (match_operand:MSA 1 "register_operand") >+ (match_operand:MSA 2 "register_operand") >+

RE: [PATCH, MIPS] Frame header optimization for MIPS O32 ABI

Moore, Catherine writes: > The patch itself looks good, but the tests that you added need a little more > work. > > I tested with the mips-sde-elf-lite configuration and I'm seeing failures for > many > options. The main failure mode seems to be that the stack is

RE: [PATCH] Fix undefined behaviour in mips port

Jeff Law writes: > Another instance of left shifting a negative value. Fixed in an obvious > way. Verified all the mips configurations in config-list.mk build now > using a trunk compiler. > > Installed on the trunk, Thanks Jeff. Matthew

RE: [PATCH 2/4] [MIPS] Add pipeline description for MSA

> gcc/ChangeLog: > > * config/mips/i6400.md (i6400_fpu_intadd, i6400_fpu_logic) > (i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float, > i6400_fpu_store) > (i6400_fpu_long_pipe, i6400_fpu_logic_l, i6400_fpu_float_l) > (i6400_fpu_mult): New cpu units. >

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Robert, Next batch of comments for this patch. I've covered mips-msa.md up to the copy patterns and one supporting function from mips.c. >+++ b/gcc/config/mips/mips-msa.md >+;; The attribute gives half modes for vector modes. >+(define_mode_attr VHMODE >+ [(V8HI "V16QI") >+ (V4SI "V8HI")

RE: [PATCH] [MIPS] Fix wrong instruction in the delay slot

Robert Suchanek > IMO, the fix is to recognize the empty basic block that has a code_label > followed by a barrier (ignoring notes and debug_insns), forbid going > beyond the barrier if the empty block is found in > skip_consecutive_labels () and

RE: [PATCH, MIPS] Frame header optimization for MIPS O32 ABI

Steve Ellcey writes: > Here is an update of my MIPS frame header optimization patch. This is > actually only one part of the patch but I would like to get this approved > and checked in before proceeding with the second half. > > The O32 ABI on MIPS requires that

RE: [PATCH, MIPS] Compact branch support for MIPS32R6/MIPS64R6

Moore, Catherine <catherine_mo...@mentor.com> writes: > Hi Matthew: > > > -Original Message- > > From: Matthew Fortune [mailto:matthew.fort...@imgtec.com] > > Sent: Monday, August 17, 2015 6:47 PM > > To: Moore, Catherine; 'gcc-patches@gcc.gnu.org' (

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Robert, I'm taking small steps at this review. I did the first few files as below. mips-msa.md is next so don't expect the it quickly. I might do that in pieces too. No need to post an updated patch until I'm all the way through but I'd appreciate an explicit ok/done to each point or

RE: [PATCH] MIPS: If a test in the MIPS testsuite requires standard library support check the sysroot supports the required test options.

Moore, Catherine catherine_mo...@mentor.com writes: The recent changes to the MIPS GCC Linux sysroot (https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01014.html) have meant that the include directory is now not global and is provided only for each multi-lib configuration. This means that

RE: [PATCH] Disable -mbranch-likely for -Os when targetting generic architecture

Richard Sandiford rdsandif...@googlemail.com writes: Robert Suchanek robert.sucha...@imgtec.com writes: The patch below disables generation of the branch likely instructions for -Os but only for generic architecture. The branch likely may result in some code size reduction but the cost

RE: [Patch, MIPS] MIPS specific optimization for o32 ABI

Steve Ellcey steve.ell...@imgtec.com writes: On Thu, 2015-08-13 at 02:14 -0700, Matthew Fortune wrote: Hi Steve, Overall, I don't think these optimizations are ready to include. In principle the idea looks good but it is done at the wrong point in the compiler in my opinion

[MIPS,PATCH,committed] Fix mips.exp logic when disabling features removed in R6

When switching up from an older ISA to MIPSR6 some features need to be disabled. The support for this added in rev r225813 missed the fact that both the $isa and $isa_rev variables are referenced in this code so both must get redefined to their (potentially) new values. Without this patch a number

RE: [Patch, MIPS] MIPS specific optimization for o32 ABI

Hi Steve, Overall, I don't think these optimizations are ready to include. In principle the idea looks good but it is done at the wrong point in the compiler in my opinion. The biggest concern I have is that the analysis should be possible at (or prior to) the point where the prologue/epilogue

RE: [PATCH, MIPS] Enable load/store bonding for I6400

gcc/ * config/mips/mips.h (ENABLE_LD_ST_PAIRS): Enable load/store pairs for I6400. Sorry, I missed this one. OK to commit. Thanks, Matthew

RE: [PATCH][MIPS] Fix register renaming in the interrupt handlers

I'd like to give Catherine chance to review this, I notice a couple of formatting nits in the test case: Robert Suchanek robert.sucha...@imgtec.com writes: a/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c b/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c new file mode 100644

RE: [PATCH, MIPS] Remove W32 and W64 pseudo-processors

Robert Suchanek robert.sucha...@imgtec.com writes: gcc/ * config/mips/mips.c (mips_rtx_cost_data): Remove costs for W32 and W64 pseudo-processors. * config/mips/mips.md (processor): Remove w32 and w64. OK, thanks. Matthew

[PATCH, MIPS] Compact branch support for MIPS32R6/MIPS64R6

A full range of 'compact' branch instructions were introduced to MIPS as part of Release 6. The compact term is used to identify the fact that these do not have a delay slot. http://imgtec.com/mips/architectures/mips64/ The one subtlety of compact branches is that while they do not have a delay

RE: [PATCH] MIPS: Prevent the p5600-bonding.c test from being run for the n32 and 64 ABIs

Andrew Bennett andrew.benn...@imgtec.com writes: diff --git a/gcc/testsuite/gcc.target/mips/p5600-bonding.c b/gcc/testsuite/gcc.target/mips/p5600-bonding.c index 0890ffa..20c26ca 100644 --- a/gcc/testsuite/gcc.target/mips/p5600-bonding.c +++ b/gcc/testsuite/gcc.target/mips/p5600-bonding.c @@

RE: [PATCH, MIPS] I6400 scheduling

Robert Suchanek robert.sucha...@imgtec.com writes: 2015-07-16 Prachi Godbole prachi.godb...@imgtec.com gcc/ * config/mips/i6400.md: New file. * config/mips/mips-cpus.def (mips32r6): Change to PROCESSOR_I6400. (mips64r6): Likewise. (i6400): Define. *

RE: [PATCH, MIPS] Scheduling for M51xx core family

Robert Suchanek robert.sucha...@imgtec.com writes. 2015-07-16 Prachi Godbole prachi.godb...@imgtec.com gcc/ * config/mips/m5100.md: New file. * config/mips/mips-cpus.def (m5100, m5101): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c

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