RFA: RL78: Minor prologue and epilogue enhancements

? Cheers Nick 2015-01-26 Nick Clifton * config/rl78/rl78.c (rl78_expand_prologue): In G10 mode push the BC, DE and HL registers directly, not via AX. When decrementing the stack pointer by a large amount, transfer SP into AX and perform the subtraction there

RFA: RL78: Scan inside PARALLELs when looking for dead code

generated for the RL78 are the SImode shift patterns and these always consist of a SET as the first element and a CLOBBER as the second element. So I decided to keep things simple and create the patch below. OK to apply ? Cheers Nick 2015-01-20 Nick Clifton * config/rl78

Commit: MSP430: Fix addsi splitter (PR 64160)

Hi Guys. I am applying the patch below to fix PR 64160 for the MSP430. Cheers Nick gcc/ChangeLog 2014-12-24 Nick Clifton PR target/64160 * config/msp430/msp430.md (addsi splitter): Do not split when the destination partially overlaps the source. Index: config

Commit: 4.9 branch: Backport RX 'R' operator fix

Hi Guys, I am backporting an RX-specific patch from the mainline to the 4.9 branch as it fixes an ICE running the gcc test gcc.c-torture/compile/pr39423-2.c. Cheers Nick gcc/ChangeLog 2014-12-24 Nick Clifton Backport from mainline: 2014-03-25 Nick Clifton

Commit: 4.9 branch: Backport RX alignment fix

Hi Guys, I am backporting an RX-specific patch from the mainline to the 4.9 branch as this fixes an internal error in the assembler (!) when running the gcc test gcc.c-torture/compile/pr53748.c. Cheers Nick gcc/ChangeLog 2014-12-24 Nick Clifton Backport from mainline

Commit: Rl78: Save ES register in interrupt handlers

Nick gcc/ChangeLog 2014-11-21 Nick Clifton * config/rl78/rl78-real.md (movqi_from_es): New pattern. * config/rl78/rl78.c (struct machine_function): Add uses_es field. (rl78_expand_prologue): Save the ES register in interrupt handlers that use it

RL78: Add support for assembler G10 multiply/divide functions to libgcc

Hi Guys, I am applying the patch below to add support for G10 versions of the RL78 assembler multiply and divide functions to the libgcc library. Cheers Nick libgcc/ChangeLog 2014-11-13 Nick Clifton * config/rl78/divmodhi.S: Add support for the G10 architecture. Use

Commit: MSP430: Improve -mhwmult= opton and fix prologues and epilogues for naked functions

generation in that code in function.c expects some RTL to be returned, even if the function is naked. Cheers Nick gcc/ChangeLog 2014-09-29 Nick Clifton * config/msp430/msp430.c (msp430_expand_prologue): Return a CLOBBER rtx for naked functions. (msp430_expand_epilogue

Commit: SH: Fix typo in atomic fetch sequence

Hi Alex, Hi Kaz, Hi Oleg, I am applying the patch below as an obvious fix for a typo in the instruction sequence of the atomic_fetch_nand_soft_imask pattern. I hope that this is OK with you. Cheers Nick gcc/ChangeLog 2014-09-25 Nick Clifton PR target/62218 * config

Commit: RL78: Fix poping of registers in G10 mode

A to the correct register) because the popped values were never used. Cheers Nick gcc/ChangeLog 2014-09-19 Nick Clifton * config/rl78/rl78.c (rl78_expand_epilogue): Generate a USE of the pop'ed registers so that DCE does not eliminate them. Index: gcc/config/r

Commit:

Hi Guys, I am applying the patch below as an obvious fix. It adds a missing @gol to the end of one of the option list lines and it removes a superfluous second "functions" from the description of the -mhotpatch option. Cheers Nick gcc/ChangeLog 2014-09-09 Ni

Commit: RX:

where a register was pushed onto the stack was off by 4 bytes. Cheers Nick gcc/ChangeLog 2014-07-24 Nick Clifton * config/rx/rx.md (stack_push): Adjust RTL to account for the fact that operations are taking place in parallel. * config/rx.h (FRAME_POINTER_CFA_OFFSET

Commit: FRV: Remove redundant assert

Hi Guys, I am checking in the patch below to remove a redundant assert, now that DECL_SECTION_NAME returns a string rather than a tree. Cheers Nick gcc/ChangeLog 2014-06-26 Nick Clifton * config/frv/frv.c (frv_in_small_data_p): Remove redundant assert. Index: config/frv/frv.c

Commit: Testsuite: Fix typo in proc check_effective_target_trapping

Hi Guys, I am applying the patch below as an obvious fix for a typo in the check_effective_target_trapping proc in the testsuite's target-supports.exp file. Cheers Nick gcc/testsuite/ChangeLog 2014-06-26 Nick Clifton * lib/target-supports.exp (check_effective_target_tra

Commit: RX: Fix typo in description of RX vector attribute

Hi Guys, I am checking in the patch below to fix a small typo in the description of the RX vector function attribute. Cheers Nick gcc/ChangeLog 2014-06-26 Nick Clifton * doc/extend.texi (Function Attributes): Fix typo in description of RX vector attribute. Index: doc

Commit: MSP430: Add NOP after DINT in hardware multiply patterns

it has to be a NOP. The change is going in to the mainline sources and the 4.9 branch. Cheers Nick gcc/ChangeLog 2014-06-17 Nick Clifton * config/msp430/msp430.md (mulhisi3): Add a NOP after the DINT. (umulhi3, mulsidi3, umulsidi3): Likewise. Index: gcc/config/msp430

Commit: RX: Correctly honour user specified alignment of jumps, loops and labels

Hi Guys, I am applying the patch below to fix a small problem with the RX port - it was using non-log based alignment values for jumps, loops and labels when user specified alignment was enabled. Cheers Nick gcc/ChangeLog 2014-06-13 Nick Clifton * config/rx/rx.h (JUMP_ALIGN

Commit: MSP430: Built libgcc with hardware multiply disabled

even when it was not clear that it would be supported by the target MCU. The fix is just to disable the use of hardware multiplies inside libgcc. Cheers Nick libgcc/ChangeLog 2014-05-22 Nick Clifton * config/msp430/t-msp430 (HOST_LIBGCC2_CFLAGS): Add -mhwmult=none

Commit: MSP430: Add spaces after options inserted by ASM_SPEC

unintelligible options. Cheers Nick gcc/ChangeLog 2014-05-22 Nick Clifton * config/msp430/msp430.h (ASM_SPEC): Add spaces after inserted options. Index: gcc/config/msp430/msp430.h === --- gcc/config/msp430/msp430.h

Commit: MSP430: Fix some gcc testsuite failures

zero_extendpsisi2 pattern was confusing gcc about the number of hard registers needed to hold an SImode value. The second fixes a problem with expanding va_arg when pointers are not a multiple of the word size. Cheers Nick gcc/ChangeLog 2014-05-20 Nick Clifton * config/msp430

Commit: MSP430: Fix gcc.c-torture/execute/20050826-2.c

r7))) it became confused and thought that only r7 was being set, not r7 and r8. Changing the output constraint to "+r" prevents this from happening. Cheers Nick ChangeLog 2014-05-20 Nick Clifton * config/msp430/msp430.md (zero_extendpsisi2): Use + constraint on

RFA: Fix calculation of size of builtin setjmp buffer

for an rl78-elf toolchain. OK to apply ? Cheers Nick 2014-05-06 Nick Clifton * except.c (init_eh): Fix computation of builtin setjmp buffer size. Index: gcc/except.c === --- gcc/except.c(revision

Commit: MSP430: Fix bugs in MSP430 backend

interrupt handlers when in fact it is interrupt safe. * The umulsidi3 pattern used the wrong address for the second operand. Tested with an msp430-elf toolchain with no regressions. Cheers Nick gcc/ChangeLog 2014-04-29 Nick Clifton * config/msp430/msp430.md (umulsidi

Commit: Fix building ARC, M32C and M32R backends

.c:3178:88: error: invalid conversion from 'int' to 'machine_mode' [-fpermissive] It happens because all of these backends use an integer to hold a machine mode value instead of an enum. The simple fix is to use the enum instead. Cheers Nick gcc/ChangeLog 2014-04-29 Ni

Commit: MSP430: Enhance -mhwmult option

options so that the last one specified takes precedence. Cheers Nick gcc/ChangeLog 2014-04-23 Nick Clifton * config/msp430/msp430.c (msp430_handle_option): Move function to msp430-common.c (msp430_option_override): Simplify mcu and mcpu option handling

RFA: x86 backend: Add default-manifest to Cygwin/MinGW links

project which will have to become a new dependency for the Cygwin and MinGW projects. Cheers Nick gcc/ChangeLog 2014-04-23 Nick Clifton * config/i386/cygwin.h (ENDFILE_SPEC): Include default-manifest.o if it can be found in the search path. * config/i386

RFA: RL78: Fix handling of (SUBREG (SYMBOL_REF))

? Cheers Nick gcc/ChangeLog 2014-04-01 Nick Clifton * config/rl78/rl78-expand.md (movqi): Handle (SUBREG (SYMBOL_REF)) properly. Index: gcc/config/rl78/rl78-expand.md === --- gcc/config/rl78/rl78-expand.md

Commit: MSP430: Add hardware multiply routines to libgcc

Hi Guys, I am applying the patch below to add libgcc functions to support hardware multiplies on the MSP430. Cheers Nick libgcc/ChangeLog 2014-03-06 Nick Clifton * config/msp430/t-msp430 (LIB2ADD): Add lib2hw_mul.S * config/msp430/lib2hw_mul.S: New: Hardware multiply

Commit: Xstormy16: Add modes to post_inc and pre_dec patterns

Hi Guys, I am applying the patch below to add modes to the POST_INC and PRE_DEC patterns in the XStormy16 backend. The lack of the modes was leading to some build problems. Cheers Nick gcc/ChangeLog 2014-02-21 Nick Clifton * config/stormy16/stormy16.md (pushdqi1): Add mode

Re: RFA: Fix some gcc tests for 16-bit targets

Hi Richard, Instead of modifying testcases I'd be less nervous if you'd make them require 32bit. Otherwise you should reproduce the original issues with the modified testcases. OK, I can do that. How about this patch. OK to apply ? Cheers Nick gcc/testsuite/ChangeLog 2014-0

Re: RFA: RL78: Add missing instruction patterns

patterns, so the revised patch below removes them, Cheers Nick gcc/ChangeLog 2014-02-18 Nick Clifton * config/rl78/rl78-real.md (cbranchsi4_real_signed): Add anti-cacnonical alternatives. (negandhi3_real): New pattern. * config/rl78/rl78-virt.md (neg

RFA: Fix some gcc tests for 16-bit targets

. OK to apply ? Cheers Nick gcc/testsuite/ChangeLog 2014-02-17 Nick Clifton * gcc.dg/c-torture/execute/pr43220.c: Use a long integer to count the iterations. * gcc.c-torture/execute/pr58570.c: Use a long integer to hold a 29-bit bitfield. * gcc.c

RFA: RL78: Add missing instruction patterns

/bf.c gcc.dg/20050922-1.c OK to apply ? Cheers Nick gcc/ChangeLog 2014-02-14 Nick Clifton * config/rl78/rl78-expand.md (xorhi3): New pattern. * config/rl78/rl78-virt.md (andhi3_virt): New pattern. (nandhi3_virt): New pattern. (xorhi3_virt): New pattern

Re: [PATCH] Fix ARM dwarf2cfi ICE and unwind info issues (PR target/59575)

Hi Jakub, 2014-01-30 Jakub Jelinek PR target/59575 * config/arm/arm.c (emit_multi_reg_push): Add dwarf_regs_mask argument, don't record in REG_FRAME_RELATED_EXPR registers not set in that bitmask. (arm_expand_prologue): Adjust all callers. (arm

Re: RFA: MN10300: Include saved registers in stack usage

Hi Jeff, According to our coding conventions, the ability to build with something other than gcc is still desirable. You could argue that you're unlikely to be bootstrapping on a mn103 with something other than GCC and if you're building a cross, you could start by first building gcc native. H

RFA: MN10300: Include saved registers in stack usage

there is one thing that I am not sure about - is it OK to use __builtin_popcount() or should I be calling some other function ? Tested with no regression on an mn10300-elf toolchain. OK to apply ? Cheers Nick gcc/ChangeLog 2014-02-05 Nick Clifton * config/mn10300/mn10300.c

Re: RFA: MN10300: Fix building libstdc++-v3

registers to match some classes even in MN10300. So how about the patch below ? This also allows the libstdc++-v3 library to be built. Cheers Nick gcc/ChangeLog 2014-02-04 Nick Clifton * config/mn10300/mn10300.c (mn10300_hard_regno_mode_ok): Do not accept extended registers

RFA: MN10300: Fix building libstdc++-v3

ENDED_REGS class however is the mn10300_register_move_cost() function which tells it that it only costs 2 to move via those registers. Hence the patch below. With the patch applied the libstdc++-v3 library now builds. OK to apply ? gcc/ChangeLog 2014-02-03 Nick Clifton * conf

Re: RFA: MN10300: Fix typo store_movm pattern

Hi Jeff, Agreed, the naming seems awfully confusing right now. Feel free to go forward with fixing that :-) Done - thanks! Cheers Nick

RFA: MN10300: Fix typo store_movm pattern

-> mn10300_store_multiple_operation_p mn10300_store_multiple_operation_p -> mn10300_store_multiple_regs Cheers Nick gcc/ChangeLog 2014-01-29 Nick Clifton * config/mn10300/mn10300.md (store_movm): Fix typo. Index: gcc/config/mn10300/mn10

RFA: RL78: Fix UMUL and $FP size

gcc/ChangeLog 2014-01-29 Nick Clifton DJ Delorie * config/rl78/rl78.c (register_sizes): Make the "upper half" of %fp 2 to keep registers after it properly word-aligned. (rl78_alloc_physical_registers_umul): Handle the case where both inpu

Commit: MSP430: Linker script renaming

command line option so that it will accept a wider range of names for the ISA to use. Cheers Nick gcc/ChangeLog 2014-01-23 Nick Clifton * config/msp430/msp430.h (ASM_SPEC): Pass the -mcpu as -mcpu. (LIB_SPEC): Drop useof memory.ld and peripherals.ld scripts in

Re: Commit: MSP430: Add -mcpu= option

Hi Gerald, "command-line option", I think, and I suggest to use ... around the actual options. OK - I have made those changes and committed the result. Cheers Nick

Re: Commit: MSP430: Add -mcpu= option

Hi Gerald, Mind adding an entry to the release notes? Happy to help if you have any questions. Is the following acceptable ? I even remembered to run it through the validator... Cheers Nick Index: htdocs/gcc-4.9/changes.html

Commit: MSP430: Add -mcpu= option

Hi Guys, I am committing the attached patch to add a -mcpu= command line option to the MSP430 backend. This allows the selection of the ISA to be used, and it operates independently of the -mmcu= command line option. gcc/ChangeLog 2014-01-17 Nick Clifton * config/msp430/msp430

RFA: Fix assembler data directives emitted for variable length structures

-13 Nick Clifton PR middle-end/28865 * varasm.c (output_constant): Return the number of bytes actually emitted. (output_constructor_array_range): Update the field size with the number of bytes emitted by output_constant

Re: RFA: Use precision in get_mode_bounds()

Hi Volker, apparently you added the wrong PR number to the patch. You probably meant PR 59613. Would you mind fixing that in the ChangeLog? Doh! Sorry - fixed. Cheers Nick

Commit: MSP430: Add %A, %B, %C and %D as selectors for 16-bit parts of a 64-bit operand.

Hi Guys, I am applying the patch below to the MSP430 backend to enable the use of %A, %B, %C and %D in asm statements as selectors of 16-bit parts of a 64-bit value. This is at the request of TI, for compatibility with their compiler. Cheers Nick gcc/ChangeLog 2013-12-30 Nick

RFA: Use precision in get_mode_bounds()

patch was created by Peter Bigot for a different PR: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52856 gcc/ChangeLog 2013-12-30 Nick Clifton PR target/59631 * stor-layout.c (get_mode_bounds): Use GET_MODE_PRECISION instead of GET_MODE_BITSIZE. Ind

RFA: Fix test pr32912-2.c for 16-bit targets

place, not three. There were no regressions when tested with a i686-pc-linux-gnu or a x86_64-pc-linux-gnu toolchain, and the test was fixed for a rl78-elf toolchain. OK to apply ? Cheers Nick gcc/testsuite/ChangeLog 2013-12-18 Nick Clifton * gcc.dg/pr32912-2.c: Fix for 16

Commit: MSP430: Add wakeup function attribute

interrupt handler exits. Cheers Nick gcc/ChangeLog 2013-12-13 Nick Clifton * config/msp430/msp430.c (is_wakeup_func): New function. Returns true if the current function has the wakeup attribute. (msp430_start_function): Note if the function has the wakeup

Commit: MSP430: Add wakeup function attribute

/ChangeLog 2013-12-13 Nick Clifton * config/msp430/msp430.c (is_wakeup_func): New function. Returns true if the current function has the wakeup attribute. (msp430_start_function): Note if the function has the wakeup attribute. (msp430_attribute_table): Add

Commit: MSP430: Make -mmcu option define C preprocessor symbol and linker scripts

. Cheers Nick gcc/ChangeLog 2013-11-06 Nick Clifton * config/msp430/msp430.h (TARGET_CPU_CPP_BUILTINS): Define the name returned by msp430_mcu_name. (LIB_SPEC): If a -T option has not been specified then set a default, mcu-specific, linker script

RFA: Remove some assumptions from gcc.dg tests

-gnu toolchain with no regressions and several improvements. OK to apply ? Cheers Nick gcc/testsuite/ChangeLog 2013-10-24 Nick Clifton * c-c++-common/pr57793.c: Add expected error messages for targets with small integers. * gcc.dg/c99-stdint-1.c: Only run on 32-bit

Commit: testsuite/gcc.dg/20020312-2.c: Update for RL78 and MSP430

Hi Guys, I am applying the patch below as an obvious update to the 20020312-2.c test for the RL78 and MSP430 targets. Neither of them use a specific regiser for PIC support, but the test needs to be explicitly told that. Cheers Nick gcc/testsuite/ChangeLog 2013-10-24 Nick Clifton

RFA: Change behaviour of %* in spec strings

toolchain. OK to apply ? Cheers Nick gcc/ChangeLog 2013-10-17 Nick Clifton * gcc.c (do_spec_1): Do not insert a space after a %* substitution unless it is the last part of a spec substring. * doc/invoke.texi (Spec Files): Document space insertion behaviour of

Re: RFA: GCC Testsuite: Annotate compile tests that need at least 32-bit pointers/integers

Hi Mike, It may be reasonable to special case ptr32plus to say no on your platform, from check_effective_target_tls_native, we see code like: you could do something like: proc check_effective_target_ptr32plus { } { # msp430 never really has 32 or more bits in a pointer. if { [ista

RFA: GCC Testsuite: Annotate compile tests that need at least 32-bit pointers/integers

regressions on msp430-elf, rl78-elf and xstormy16-elf targets. OK to apply ? Cheers Nick gcc/testsuite/ChangeLog 2013-09-30 Nick Clifton * gcc.c-torture/compile/20010327-1.c: Only run the test for int32plus targets. * gcc.c-torture/compile/990617-1.c: Likewise.

Re: Commit: MSP430: Pass -md on to assembler

Hi Mike, I must say though, it seems wrong to have to provide a sign-extend pointer pattern when pointers (on the MSP430) are unsigned. Agreed. If we instead ask, is it sane for gcc to ever want to signed extend in this case, the answer appears to be no. Why does it, ptr_mode is SImode, an

Commit: MSP430: Code gen improvements

PSI to SI conversion pattern for when signed pointer values need to be stored in an SI pair of registers. Cheers Nick gcc/ChangeLog 2013-09-26 Nick Clifton * config/msp430/msp430.c (msp430_expand_epilogue): Fix compile time warning message. (msp430_print_operand_raw

Commit: MSP430: Pass -md on to assembler

the function in the assembler output. This is mainly for debugging purposes. Cheers Nick gcc/ChangeLog 2013-09-18 Nick Clifton * config/msp430/msp430.h (ASM_SPEC): Pass -md on to the assembler. (ASM_DECLARE_FUNCTION_NAME): Define. Index: gcc/config/msp430/msp430.h

Re: RFA: Testsuite: Add exceptions for MSP430

Hi Mike, Ok, I assume that the changes to hppa and return 0 are intentional and good… - || [istarget hppa64-hp-hpux11.23] } { - return 0; +|| [istarget hppa64-hp-hpux11.23] } { + return 0; Sorry - yes - they are just whitespace adjustments so that the entries line

Commit: MSP430: Add support for interrupt handlers

functions (which disable interrupts whilst they execute) and reentrant functions (which disable interrupts but always reenable them upon exit). Tested with no regressions on an msp430-elf toolchain. Cheers Nick gcc/ChangeLog 2013-09-17 Nick Clifton * config/msp430/msp430-protos.h

RFA: Testsuite: Add exceptions for MSP430

). OK to apply ? Cheers Nick gcc/testsuite/ChangeLog 2013-09-16 Nick Clifton * lib/target-supports.exp (check_effective_target_trampolines): Add MSP430 to the list of targets that do not support trampolines. (check_profiling_available): Add MSP430 to the list of

Re: [PING 3] [Patch RX] Add assembler option "-mcu" for generating assembler

Hi Sandeep, gas/config: 2013-07-18 Sandeep Kumar Singh * rx.h: Add option -mcpu for target variants RX100 and RX200. Approved - please apply. Cheers Nick

Re: RFA: AVR: Support building AVR Linux targets

was not sure whether it was better to accept avr-*-elf or avr-*-elf*. I went for the latter in case there were AVR ELF variants, but I defer to your superior knowledge. OK to apply ? Cheers Nick gcc/ChangeLog 2013-08-27 Nick Clifton * config.gcc (AVR): Restrict allowed targets to

Re: RFA: AVR: Support building AVR Linux targets

Hi Joseph, Your patch itself makes sense on general principles, but the concept of an AVR Linux target doesn't - this is an 8-bit processor Really, the bug you've found is that there's an avr-*-* case that is too general, matching nonsensical targets such as AVR Linux rather than just avr-*-

Re: RFA: Fix declaration of default value of TARGET_NARROW_VOLATILE_BITFIELD

commit an update patch? Thanks. I have gone ahead and checked in this patch: Cheers Nick gcc/ChangeLog 2013-08-20 Nick Clifton * target.def (narrow_volatile_bitfield): Note that the default value is false, not !TARGET_STRICT_ALIGN. * doc/tm.texi: Regenerate. Index

Commit: M32R: Fix config problem building m32r-linux toolchains

-08-12 Nick Clifton * config.gcc (m32r-linux): Allow for tmake_file not being empty. Index: gcc/config.gcc === --- gcc/config.gcc (revision 201658) +++ gcc/config.gcc (working copy) @@ -1705,8 +1705,7

RFA: AVR: Support building AVR Linux targets

Nick gcc/ChangeLog 2013-08-12 Nick Clifton * config.gcc (avr-*-*): Allow for tmake_file not being empty. Index: gcc/config.gcc === --- gcc/config.gcc (revision 201658) +++ gcc/config.gcc (working copy) @@ -1001

Re: msp430 port

Hi DJ, Hi Richard, +;; The next two patterns are here to support a "feature" of how GCC implements +;; varargs. When a function uses varargs and the *second* to last named +;; argument is split between argument registers and the stack, gcc expects the +;; callee to allocate space on the stack t

Re: [PING 2] [PATCH RX] Added target specific macros for RX100, RX200, and RX600

Hi Sandeep, >>> The patch is fine, please apply. Thanks for the review. I do not have write approvals to gcc-svn. Could you please commit this for me? Done. Cheers Nick

Re: [PING 2] [PATCH RX] Added target specific macros for RX100, RX200, and RX600

Hi Sandeep, Below patch added target specific macros for RX100, RX200, and RX600 http://gcc.gnu.org/ml/gcc-patches/2013-05/msg00050.html Please review the patch and let me know if there should be any modifications in it? Sorry - I missed your original posting. The patch is fine, please appl

RFA: RL78: Add support for naked function attribute.

Hi DJ, OK, I am abandoning my RL78 interrupt prologue patch for now. There are just too many complications to make it work. Instead here is a much simpler patch to add support for a naked function attribute. OK to apply ? Cheers Nick gcc/ChangeLog 2013-05-16 Nick Clifton

Re: RFA: Allow simplification of SUBREGs involving the frame pointer during LRA

Hi Jeff, I would like to apply the patch below to allow simplify_subreg_regno() to treat the frame pointer register in the same way as the stack pointer register when the LRA pass is running. Ew. Before accepting this, I'd like to see more of the rationale behind the change. *s

Re: new port: msp430-elf, revision 2

Hi Steven, > Should new ports be allowed in if they rely so heavily on reload? As it happens I am currently working on enabling LRA for the MSP430 target. Although I have run into a roadblock with a possibly unacceptable patch to simplify_subreg_regno: http://gcc.gnu.org/ml/gcc-patches/20

Re: RFA: RL78: Improve interrupt function generation

Hi DJ, * Uses register bank 3 instead of register bank 0 inside the handler. I wonder if nested interrupts will cause problems, since the second interrupt will occur with RB3 already selected. Yes - in fact this appears to be a general problem with RL78 interrupt handlers. Ther

RFA: Allow simplification of SUBREGs involving the frame pointer during LRA

still not working for these targets, but this patch lets more of libgcc be built than before). No regressions noted on an i686-pc-linux-gnu toolchain built with this patch applied. OK to apply ? Cheers Nick gcc/ChangeLog 2013-05-03 Nick Clifton * rtlanal.c

RFA: RL78: Improve interrupt function generation

K to apply ? Cheers Nick gcc/ChangeLog 2013-05-01 Nick Clifton * config/rl78/rl78.c (need_to_save): Make into a boolean function. Do not save register bank 0 registers in interrupt handlers. (rl78_attribute_table): Add "naked". (rl78_is_naked

RFA: Fix declaration of default value of TARGET_NARROW_VOLATILE_BITFIELD

rects this, and also fixes a small typo in the description of TARGET_CANONICALIZE_COMPARISON. Ok to apply ? Cheers Nick gcc/ChangeLog 2013-04-24 Nick Clifton * doc/tm.texi.in (TARGET_NARROW_VOLATILE_BITFIELD): Change the default to false. (TARGET_CANONICALIZE_

RFA: Fix use of extra_objs when configuring tilepro-linux and tilegx-linux

ux in config.gcc override the definition of extra_objs, rather than extending it, thus loosing the inclusion of linux_android.o into libbackend.a. I fixed the problem with the patch below and was able to build both toolchains. OK to apply ? Cheers Nick gcc/ChangeLog 2013-04-21 Nick Cl

Commit: V850: Use FPU-3.0 multiply-add instructions on E3V5 architectures

Hi Guys, I am checking in the patch below to make gcc generate the FPU-3.0 multiply-add instructions when targeting the E3V5 V850 architecture. Cheers Nick gcc/ChangeLog 2013-04-03 Nick Clifton * config/v850/v850e3v5.md (fmasf4): Use fmaf.s on E3V5 architectures

RFA: RL78: Improve prologues for interrupt handlers

Hi DJ, I am submitting a patch on behalf of Renesas and KPIT. They found a way to improve the prologues for interrupt handlers so that only the registers that actually need to be saved are pushed onto the stack. The patch has been tested with no regressions in the gcc testsuite for an

Commit: XStormy16: Remove spurious backslash

Hi Guys, I am applying this small patch to remove a spurious backslash escape at the end of a line in stormy16.c. Cheers Nick gcc/ChangeLog 2013-03-18 Nick Clifton * config/stormy16/stormy16.c (xstormy16_expand_prologue): Remove spurious backslash. Index: gcc/config

Commit: MN10300: Add missing comment line

Hi Guys I am applying this patch as obvious. It adds a line missing from the comment describing the mn10300_get_live_callee_saved_regs function. Cheers Nick gcc/ChangeLog 2013-03-18 Nick Clifton * config/mn10300/mn10300.c (mn10300_get_live_callee_saved_regs): Add

Re: closing PR's (was Re: [PATCH ARM iWMMXt 0/5] Improve iWMMXt support)

Hi Hans-Peter, Sorry if I misinterpret, but it seems a reminder is in order: magic powers are attached to whome...@gcc.gnu.org accounts in bugzilla, so when people use them instead of their whome...@employer.example.com, they are able to close PR's they haven't created. Ah - thank you, I did no

Commit: V850: Add support for the E3V5 architecture variant

ers Nick gcc/ChangeLog 2013-01-31 Hiroyuki Ono Nick Clifton * config/v850/constraints.md (Q): Define as a memory constraint. * config/v850/predicates.md (label_ref_operand): New predicate. (e3v5_shift_operand): New predicate. (ior_operator)

Re: [PATCH ARM iWMMXt 0/5] Improve iWMMXt support

Hi Matt, Could this patch, or perhaps the much smaller one I attached to bug 35294 be committed to the 4.7 branch? Yes. Done. Also, could you close its duplicates, bugs 36798 and 36966? Sorry no. I do not actually own these PRs, so I cannot close them. :-( Cheers Nick

RFA: RL78: Allow SP to be used as a base register

/ChangeLog 2013-01-28 Nick Clifton * config/rl78/rl78.c (rl78_regno_mode_code_ok_for_base_p): Allow SP_REG. Index: gcc/config/rl78/rl78.c === --- gcc/config/rl78/rl78.c (revision 195461) +++ gcc/config/rl78/rl78

Re: [testsuite] replace gcc.target/arm/ftest-*.c with compile-only tests

Hi Janis, > 2013-01-16 Janis Johnson > >* gcc.target/arm/ftest-support.h: Replace for compile-only tests. >* gcc.target/arm/ftest-support-arm.h: Delete. >* gcc.target/arm/ftest-support-thumb.h: Delete. >* gcc.target/arm/ftest-armv4-arm.c: Replace with compile-only test. >*

Re: PING: gcc.target/arm: skip 5 tests for flag conflicts

Hi Janis, Now I get it. This version is more selective about which multilibs are skipped. I tested it by using multilib test flags for all valid values for -march, with and without -mthumb as appropriate for the arch. The ones that are now skipped are the ones that used to fail with complaint

Re: [testsuite] replace gcc.target/arm/ftest-*.c with compile-only tests

Hi Janis, > The gcc.target/arm/ftest-*.c tests check various macros that are set for > ARM targets by setting flags based on preprocessor directives that check > those macros. The tests are skipped if the current test platform > doesn't support executing programs for the architecture for which fl

Re: [testsuite] fix ARM test gcc.target/arm/neon-vld1_dupQ.c

Hi Janis, > 2013-01-14 Janis Johnson > > * gcc.target/arm/neon-vld1_dupQ.c: Use types that match function > prototypes. Approved - please apply. Cheers Nick

Re: [testsuite] add option to LTO flags for c-torture/execute/builtins tests

Hi Janis, > 2013-01-15 Janis Johnson > > PR testsuite/55994 > * gcc.c-torture/execute/builtins/builtins.exp: Add > -Wl,--allow-multiple-definition for eabi and elf targets. Approved - please apply. Cheers Nick

Re: [testsuite] remove ARM big-endian from some vect effective targets

Hi Janis, > 2013-01-15 Janis Johnson > > PR testsuite/54622 > > * lib/target-supports.exp (check_effective_target_vect_perm_byte, > check_effective_target_vect_perm_short, > check_effective_target_vect_widen_mult_qi_to_hi_pattern, > check_effective_target_vect64)

Re: PING: gcc.target/arm: skip 5 tests for flag conflicts

Hi Janis, > Back in September I submitted a patch to fix five ARM tests in > . > You responded in < http://gcc.gnu.org/ml/gcc-patches/2012-10/msg00972.html> > and I answered your questions in a reply. I believe that Richard's main point wa

Re: v850 ld error

Hi Joel, Well Doh! The gcc-abi and 8byte multilib variants appeared to have been added around 2012-11-20 by Nick Clifton. I think he missed changing the ASM_SPEC in gcc/config/v850/rtems.h when he added it. v850-rtems-gcc wasn't passing in the expected cpu specification flags. Nick.. how

Commit: V850: Fix floating point comparisons, branches and conditional stores

ranch patterns. Tested with no regressions on a v850e2v3-elf toolchain. Cheers Nick gcc/ChangeLog 2013-01-09 Nguyen Duy Dat Nick Clifton * config/v850/v850.md (cbranchsf4): New pattern. (cstoresf4): New pattern. (cbranchdf4): New pattern. (csto

Commit: V850: Only compile callt support functions when CALLT is enabled

relocation error for these functions due to the way that they are implemented. Tested with no regressions on a v850-elf toolchain. Cheers Nick libgcc/ChangeLog 2013-01-04 Nick Clifton * config/v850/lib1funcs.S: Only provide CALLT support functions if the CALLT

RFA: RL78: Correct values of the MDBL and MDBH registers

gcc/ChangeLog 2013-01-03 Nick Clifton * config/rl78/rl78.md (mulsi3_g13): Correct values for MDBL and MDBH registers. Index: gcc/config/rl78/rl78.md === --- gcc/config/rl78/rl78.md (revision 194833) +++ gcc/confi

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