On 9/13/23 3:48 PM, Segher Boessenkool wrote:
- "TARGET_POWER10 && TARGET_POWERPC64"
+ "TARGET_POWER10 && TARGET_POWERPC64 && !RS6000_DISABLE_SCALAR_MODULO"
"vmoduq %0,%1,%2"
Did we ever test if this insn in fact is slower as well? I don't mean
either way, orthogonality is good, but
Ping.
On 6/30/23 2:26 PM, Pat Haugen via Gcc-patches wrote:
Updated from prior version to address latest review comment (simplify
umod3).
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues
Ping.
On 6/30/23 2:26 PM, Pat Haugen via Gcc-patches wrote:
Updated from prior version to address latest review comment (simplify
umod3).
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues
On 6/30/23 2:26 PM, Pat Haugen via Gcc-patches wrote:
Updated from prior version to address latest review comment (simplify
umod3).
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues
Ping.
On 6/30/23 2:26 PM, Pat Haugen via Gcc-patches wrote:
Updated from prior version to address latest review comment (simplify
umod3).
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues
since the equivalent div/mul/sub sequence does not suffer
the same problem.
Bootstrapped and regression tested on powerpc64/powerpc64le.
Ok for master and backports after burn in?
-Pat
2023-06-30 Pat Haugen
gcc/
* config/rs6000/rs6000.cc (rs6000_rtx_costs): Check if disabling
scalar
On 6/27/23 1:52 PM, Pat Haugen via Gcc-patches wrote:
Updated from prior version to address review comments (update
rs6000_rtx_cost,
update scan strings of mod-1.c/mod-2.c)l.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can
values. This patch disables
their generation since the equivalent div/mul/sub sequence does not suffer
the same problem.
Bootstrapped and regression tested on powerpc64/powerpc64le.
Ok for master and backports after burn in?
-Pat
2023-06-27 Pat Haugen
gcc/
* config/rs6000/rs6000.cc
Ping ^3
On 4/18/23 7:22 AM, Pat Haugen via Gcc-patches wrote:
Updated from prior patch to also disable for int128.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input
Ping.
On 4/18/23 7:22 AM, Pat Haugen via Gcc-patches wrote:
Updated from prior patch to also disable for int128.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input values
Ping.
On 4/18/23 7:22 AM, Pat Haugen via Gcc-patches wrote:
Updated from prior patch to also disable for int128.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input values
/mul/sub sequence does not suffer
the same problem.
Bootstrapped and regression tested on powerpc64/powerpc64le.
Ok for master and backports after burn in?
-Pat
2023-04-18 Pat Haugen
gcc/
* config/rs6000/rs6000.h (RS6000_DISABLE_SCALAR_MODULO): New.
* config/rs6000/rs6000.md
.
Bootstrapped and regression tested on powerpc64le (Power10).
Ok for master and backports after burn in?
-Pat
2023-04-07 Pat Haugen
gcc/
* config/rs6000/rs6000.h (RS6000_DISABLE_SCALAR_MODULO): New.
* config/rs6000/rs6000.md (mod3, *mod3): Use it.
(define_expand umod3
for a possible future peephole combining
div/mod. But this can lead to cases of a needless copy being inserted. Fixed
with the following patch.
Bootstrapped and regression tested on powerpc64le.
Ok for master?
-Pat
2023-03-21 Pat Haugen
gcc/
* config/rs6000/rs6000.md (*mod3, umod3
On 2/27/23 2:53 PM, Segher Boessenkool wrote:
Hi!
On Mon, Feb 27, 2023 at 02:12:23PM -0600, Pat Haugen wrote:
On 2/27/23 11:08 AM, Segher Boessenkool wrote:
On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
The define_insns for the modulo operation currently force the target
On 2/27/23 11:08 AM, Segher Boessenkool wrote:
Hi!
On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
The define_insns for the modulo operation currently force the target
register
to a distinct reg in preparation for a possible future peephole combining
div/mod. But this can lead
with the following patch.
Bootstrapped and regression tested on powerpc64le.
Ok for master?
-Pat
2023-02-27 Pat Haugen
gcc/
* config/rs6000/rs6000.md (*mod3, umod3): Add
non-earlyclobber alternative.
gcc/testsuite/
* gcc.target/powerpc/mod-no_copy.c: New.
diff --git a/gcc
On 1/4/23 3:20 AM, Kewen.Lin via Gcc-patches wrote:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 88c865b6b4b..6fa084c0807 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4378,9 +4378,15 @@ rs6000_option_override_internal (bool
Ping.
On 4/26/22 3:06 PM, Pat Haugen via Gcc-patches wrote:
Fix register count when not splitting Complex IEEE 128-bit args.
For ABI_V4, we do not split complex args. This created a problem because
even though an arg would be passed in two VSX regs, we were only
advancing the
function arg
.
Bootstrapped and regression tested on powerpc64(32/64) and powerpc64le.
Ok for master?
-Pat
2022-04-26 Pat Haugen
PR testsuite/99685
gcc/
* config/rs6000/rs6000-call.cc (rs6000_function_arg_advance_1): Bump
register count when not splitting IEEE 128-bit Complex.
diff --git
Ping.
On 2/10/22 4:17 PM, Pat Haugen via Gcc-patches wrote:
Per Alan's comment in the bugzilla, fix attr-retain-* tescases for 32-bit
PowerPC.
Bootstrapped and regression tested on powerpc64(32/64) and powerpc64le.
Ok for master?
-Pat
2022-02-10 Pat Haugen
PR testsuite/100407
Ping.
On 1/28/22 12:03 PM, Pat Haugen via Gcc-patches wrote:
Mark Power10 fusion option undocumented and remove sub-options.
Bootstrapped and regression tested on powerpc64le(Power10).
Ok for master?
-Pat
2022-01-28 Pat Haugen
gcc/
* config/rs6000/rs6000.opt (mpower10-fusion
Per Alan's comment in the bugzilla, fix attr-retain-* tescases for 32-bit
PowerPC.
Bootstrapped and regression tested on powerpc64(32/64) and powerpc64le.
Ok for master?
-Pat
2022-02-10 Pat Haugen
PR testsuite/100407
gcc/testsuite/
* gcc.c-torture/compile/attr-retain-1.c
Mark Power10 fusion option undocumented and remove sub-options.
Bootstrapped and regression tested on powerpc64le(Power10).
Ok for master?
-Pat
2022-01-28 Pat Haugen
gcc/
* config/rs6000/rs6000.opt (mpower10-fusion): Mark Undocumented.
(mpower10-fusion-ld-cmpi, mpower10
Ping. I'll note that I recently discovered that this patch also fixes PR93176
and PR97042.
-Pat
On 11/22/21 1:38 PM, Pat Haugen via Gcc-patches wrote:
> Updated version of the patch. Changes made from original are updated
> commentary to hopefully aid readability, no functional c
Ping.
On 11/22/21 1:38 PM, Pat Haugen via Gcc-patches wrote:
> Updated version of the patch. Changes made from original are updated
> commentary to hopefully aid readability, no functional changes.
>
>
> Implement more two insn constants. rotate_and_mask_constant covers
>
Ping.
On 11/22/21 1:38 PM, Pat Haugen via Gcc-patches wrote:
> Updated version of the patch. Changes made from original are updated
> commentary to hopefully aid readability, no functional changes.
>
>
> Implement more two insn constants. rotate_and_mask_constant covers
>
Ping.
On 11/22/21 1:38 PM, Pat Haugen via Gcc-patches wrote:
> Updated version of the patch. Changes made from original are updated
> commentary to hopefully aid readability, no functional changes.
>
>
> Implement more two insn constants. rotate_and_mask_constant covers
>
Somehow there was an issue when a larger patch was backported, and this chunk
did not make it. Tested and committed as obvious.
-Pat
2021-10-04 Pat Haugen
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/fusion-p10-ldcmpi.c: Update counts.
diff --git a/gcc/testsuite/gcc.target
Ping.
On 8/11/21 11:02 AM, Pat Haugen via Gcc-patches wrote:
> Enable store fusion on Power10.
>
> Use the SCHED_REORDER hook to implement Power10 specific ready list
> reordering.
> As of now this is just store fusion.
>
> Things changed in this version of the pat
- Misc coding style changes pointed out in review (parens/braces)
- Add testcases
Bootstrap/regtest on powerpc64(32/64) and powerpc64le(Power10) with no new
regressions.
Ok for master?
-Pat
2021-08-11 Pat Haugen
gcc/ChangeLog:
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER
with no new regressions. Ok for master?
-Pat
2021-08-07 Pat Haugen
gcc/ChangeLog:
* config/rs6000/rs6000.c (is_load_insn1): Verify destination is a
register.
(is_store_insn1): Verify source is a register.
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000
On 8/6/21 11:05 AM, Segher Boessenkool wrote:
> On Fri, Aug 06, 2021 at 10:29:40AM -0500, Pat Haugen wrote:
>> On 8/6/21 10:02 AM, Segher Boessenkool wrote:
>>>> - if (GET_CODE (pat) == SET)
>>>> + if (GET_CODE (pat) == SET && REG_P (SET_DEST (pat)))
&g
On 8/6/21 10:02 AM, Segher Boessenkool wrote:
> On Fri, Aug 06, 2021 at 09:47:40AM -0500, Pat Haugen wrote:
>> Add additional checks to verify destination[source] of a load[store]
>> instruction is a register.
>
>> * config/rs6000/rs6000.c: (is_load_in
Add additional checks to verify destination[source] of a load[store]
instruction is a register.
Bootstrap/regtest on powerpc64le with no new regressions. Ok for master?
-Pat
2021-08-06 Pat Haugen
gcc/ChangeLog:
* config/rs6000/rs6000.c: (is_load_insn1): Verify destination
On 8/4/21 9:23 AM, Bill Schmidt wrote:
> Hi Pat,
>
> Good stuff! Comments below.
>
> On 8/2/21 3:19 PM, Pat Haugen via Gcc-patches wrote:
>> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
>> index 279f00cc648..1460a0d7c5c 100644
>> --- a/gc
Pat Haugen
gcc/ChangeLog:
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add new flag.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Enable
store fusion for Power10.
(is_load_insn1): Verify destination
Ping https://gcc.gnu.org/pipermail/gcc-patches/2020-October/555760.html
I've done a current bootstrap/regtest on powerpc64/powerpc64le with no
regressions.
-Pat
On 6/7/21 3:41 PM, Pat Haugen via Gcc-patches wrote:
> Update Power10 scheduling description for new fused instruction types.
>
> Bootstrap/regtest on powerpc64le(Power10) with no new regressions. Ok for
> trunk?
>
> -Pat
>
>
> 2021-06-07 Pat Haugen
>
> g
Update Power10 scheduling description for new fused instruction types.
Bootstrap/regtest on powerpc64le(Power10) with no new regressions. Ok for
trunk?
-Pat
2021-06-07 Pat Haugen
gcc/ChangeLog:
* config/rs6000/power10.md (power10-fused-load, power10-fused-store,
power10
On 6/2/21 9:19 AM, Segher Boessenkool wrote:
> On Wed, Jun 02, 2021 at 08:23:48AM -0500, Pat Haugen wrote:
>> On 6/2/21 7:01 AM, Richard Biener wrote:
>>> So did you check the RTL (and alias-sets) produced by
>>> __builtin_return_address? Test coverage might
>>
On 6/2/21 7:01 AM, Richard Biener wrote:
> On Wed, Jun 2, 2021 at 1:15 PM Pat Haugen wrote:
>>
>> On 6/2/21 1:51 AM, Richard Biener wrote:
>>> On Tue, Jun 1, 2021 at 10:37 PM Pat Haugen via Gcc-patches
>>> wrote:
>>>>
>>>> Make sure link
On 6/2/21 1:51 AM, Richard Biener wrote:
> On Tue, Jun 1, 2021 at 10:37 PM Pat Haugen via Gcc-patches
> wrote:
>>
>> Make sure link reg save MEM has frame alias set, to match other link reg
>> save/restore code.
>>
>> Bootstrap/regtest on powerpc64/pow
Make sure link reg save MEM has frame alias set, to match other link reg
save/restore code.
Bootstrap/regtest on powerpc64/powerpc64le with no new regressions. Ok for
trunk?
-Pat
2021-06-01 Pat Haugen
gcc/ChangeLog:
* config/rs6000/rs6000-logue.c (rs6000_emit_prologue): Use
On 5/7/21 6:00 PM, Segher Boessenkool wrote:
>> --- a/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c
>> @@ -62,6 +62,6 @@ rlnm_test_2 (vector unsigned long long x, vector unsigned
>> long long y,
>> /* { dg-final { scan-assembler-times
/powerpc64le with no new regressions. Testing
on CPU2017 showed no significant differences. Ok for trunk?
-Pat
2021-05-07 Pat Haugen
gcc/ChangeLog:
* config/rs6000/rs6000.c (rs6000_ira_change_pseudo_allocno_class):
Return ALTIVEC_REGS if that is best_class
ffers from the prior version in that it doesn't modify the
existing settings of the "prefixed" attribute but just adds the new attribute
and sets/tests it appropriately.
Bootstrap/regtest on powerpc64le (Power10) and powerpc64 (Power8 32/64) with no
new regressions. Ok for trunk?
-Pat
On 3/18/21 11:33 AM, will schmidt wrote:
> Per this change:
>
> +;; Whether an insn is a prefixed insn. A prefixed instruction has a prefix
> +;; instruction word that conveys additional information such as a larger
> +;; immediate, additional operands, etc., in addition to the normal
>
structions that are prefixed form.
Bootstrap/regtest on powerpc64le (Power10) and powerpc64 (Power8 32/64) with no
new regressions. Ok for trunk?
-Pat
2021-03-17 Pat Haugen
gcc/
PR target/99133
* config/rs6000/altivec.md (xxspltiw_v4si, xxspltiw_v4sf_inst,
xxspltidp
Ping3
On 2/18/21 2:30 PM, Pat Haugen via Gcc-patches wrote:
> Ping2
>
> On 1/26/21 11:27 AM, Pat Haugen via Gcc-patches wrote:
>> Ping
>>
>> On 12/8/20 3:46 PM, Pat Haugen via Gcc-patches wrote:
>>> Update size attribute for Power10.
>>>
>>&
Ping3
On 2/18/21 2:31 PM, Pat Haugen via Gcc-patches wrote:
> Ping2.
>
> On 1/26/21 11:30 AM, Pat Haugen via Gcc-patches wrote:
>> Ping.
>>
>> On 11/13/20 4:04 PM, Pat Haugen via Gcc-patches wrote:
>>> Add Power10 scheduling description.
>>>
>>&
Rename next_insn_prefixed_p for improved clarity.
Bootstrap/regtest on powerpc64le with no new regressions. Ok for trunk?
-Pat
2021-02-22 Pat Haugen
gcc/
* config/rs6000/rs6000.c (next_insn_prefixed_p): Rename.
(rs6000_final_prescan_insn): Adjust
Ping2.
On 1/26/21 11:30 AM, Pat Haugen via Gcc-patches wrote:
> Ping.
>
> On 11/13/20 4:04 PM, Pat Haugen via Gcc-patches wrote:
>> Add Power10 scheduling description.
>>
>> This patch adds the Power10 scheduling description. Since power10.md was
>> pretty
Ping2.
On 1/26/21 11:28 AM, Pat Haugen via Gcc-patches wrote:
> Ping.
>
> On 12/10/20 3:32 PM, Pat Haugen via Gcc-patches wrote:
>> Update prefixed attribute for Power10.
>>
>>
>> This patch was broken out from my larger patch to update various attributes
&g
Ping2
On 1/26/21 11:27 AM, Pat Haugen via Gcc-patches wrote:
> Ping
>
> On 12/8/20 3:46 PM, Pat Haugen via Gcc-patches wrote:
>> Update size attribute for Power10.
>>
>>
>> This patch was broken out from my larger patch to update various attributes
>> for
Ping.
On 11/13/20 4:04 PM, Pat Haugen via Gcc-patches wrote:
> Add Power10 scheduling description.
>
> This patch adds the Power10 scheduling description. Since power10.md was
> pretty much a complete rewrite (existing version of power10.md is mostly just
> a copy of power
Ping.
On 12/10/20 3:32 PM, Pat Haugen via Gcc-patches wrote:
> Update prefixed attribute for Power10.
>
>
> This patch was broken out from my larger patch to update various attributes
> for
> Power10, in order to make the review process hopefully easier. This patch only
&g
Ping
On 12/8/20 3:46 PM, Pat Haugen via Gcc-patches wrote:
> Update size attribute for Power10.
>
>
> This patch was broken out from my larger patch to update various attributes
> for
> Power10, in order to make the review process hopefully easier. This patch only
> updat
On 12/10/20 8:41 PM, acsawdey--- via Gcc-patches wrote:
> + [(set_attr "type" "logical")
Similar to load-cmp fusion pairs, we need a new insn type here.
-Pat
On 12/4/20 1:19 PM, acsawdey--- via Gcc-patches wrote:
> + print " [(set_attr \"type\" \"load\")\n";
We need to tag these with a new instruction type, such as 'fused-load-cmp', so
the scheduler can distinguish them from normal loads.
-Pat
ith no new regressions. Ok
for trunk?
-Pat
2020-12-14 Pat Haugen
gcc/
* config/rs6000/mma.md (*movxo, mma_, mma_,
mma_, mma_, mma_, mma_,
mma_, mma_, mma_, mma_):
Remove explicit setting of length attribute.
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6
updates to rs6000_insn_cost and
rs6000_adjust_insn_length. I stayed with the new 'always' keyword but added
additional commentary so hopefully is more clear.
Bootstrap/regtest on powerpc64le (Power8/Power10) with no new regressions. Ok
for trunk?
-Pat
2020-11-10 Pat Haugen
gcc
to this portion of the original patch, so nothing is new here.
Bootstrap/regtest on powerpc64le (Power8/Power10) with no new regressions. Ok
for trunk?
-Pat
2020-11-08 Pat Haugen
gcc/
* config/rs6000/dfp.md (extendddtd2, trunctddd2, *cmp_internal1,
floatditd2, ftrunc2, fixdi2
On 11/24/20 8:17 PM, Pat Haugen via Gcc-patches wrote:
> On 11/24/20 12:59 PM, Carl Love via Gcc-patches wrote:
>> +
>> +(define_insn "dives_"
>> + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
>> +(unspec:
On 11/24/20 12:59 PM, Carl Love via Gcc-patches wrote:
> +
> +(define_insn "dives_"
> + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +(unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v")
> + (match_operand:VIlong 2 "vsx_register_operand"
On 11/4/20 10:44 AM, Carl Love via Gcc-patches wrote:
> +
> +(define_insn "vdives_"
> + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +(unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v")
> + (match_operand:VIlong 2 "vsx_register_operand"
On 11/17/20 10:31 PM, will schmidt wrote:
> On Fri, 2020-11-13 at 16:04 -0600, Pat Haugen via Gcc-patches wrote:
>> +(define_automaton "power10dsp,power10issue,power10div")
>> +
>> +; Decode/dispatch slots
>> +(define_cpu_unit "du0_p
as opposed to a diff. This should make it easier to read.
This patch will not apply on current trunk do to that reason.
Bootstrap/regtest on powerpc64le (Power8/Power10) with no new regressions. Ok
for trunk?
-Pat
2020-11-13 Pat Haugen
gcc/
* config/rs6000/rs6000.c (struct
On 11/12/20 10:05 AM, Jeff Law wrote:
>> I have coded up a proof of concept that implements our needs via a new
>> target hook. The hook is passed a pair of dependent insns and returns if
>> they are a fusion candidate. It is called while removing the forward
>> dependencies of the just scheduled
On 11/5/20 4:32 PM, will schmidt wrote:
> On Wed, 2020-11-04 at 14:42 -0600, Pat Haugen via Gcc-patches wrote:
>> * config/rs6000/rs6000.c (rs6000_final_prescan_insn): Only add 'p' for
>> PREFIXED_YES.
>
> The code change reads as roughly
> - next_insn_p
) with no new regressions. Ok
for trunk?
-Pat
2020-11-04 Pat Haugen
gcc/
* config/rs6000/altivec.md (vsdb_, xxspltiw_v4si,
xxspltiw_v4sf_inst, xxspltidp_v2df_inst, xxsplti32dx_v4si_inst,
xxsplti32dx_v4sf_inst, xxblend_, xxpermx_inst,
vstrir_code_
On 9/24/20 10:59 AM, will schmidt via Gcc-patches wrote:
> +;; Move DI value from GPR to TI mode in VSX register, word 1.
> +(define_insn "mtvsrdd_diti_w1"
> + [(set (match_operand:TI 0 "register_operand" "=wa")
> + (unspec:TI [(match_operand:DI 1 "register_operand" "r")]
> +
2020-09-11 Pat Haugen
gcc/
* config/rs6000/power10.md (power10-mffgpr, power10-mftgpr): Rename to
mtvsr/mfvsr.
* config/rs6000/power6.md (X2F_power6, power6-mftgpr, power6-mffgpr):
Remove.
* config/rs6000/power8.md (power8-mffgpr, power8-mftgpr): Rename
On 9/9/20 4:41 PM, Segher Boessenkool wrote:
> Hi!
>
> On Wed, Sep 09, 2020 at 04:14:37PM -0500, Pat Haugen wrote:
>> I noticed that some of the VSR<->GPR move instructions are not typed
>> correctly. This patch fixes those instructions so that the scheduler
>
major differences (a
couple minor
improvements and no degradations). Ok for trunk?
-Pat
2020-09-09 Pat Haugen
gcc/
* gcc/config/rs6000/rs6000.md
(lfiwzx, floatunssi2_lfiwzx, p8_mtvsrwz, p8_mtvsrd_sf): Fix insn
type.
* gcc/config/rs6000/vsx.md
(vsx_c
. Also ran a
CPU2017 benchmark comparison with no major differences (a few minor
improvements and one minor degradation). Ok for trunk?
-Pat
2020-07-23 Pat Haugen
gcc/
* common/config/rs6000/rs6000-common.c
(rs6000_option_optimization_table): Turn off -fcaller-saves.
gcc
On 4/8/20 2:46 AM, Richard Biener wrote:
>> I have coded up a proof of concept that implements our needs via a new
>> target hook. The hook is passed a pair of dependent insns and returns if
>> they are a fusion candidate. It is called while removing the forward
>> dependencies of the just
The Power processor has the ability to fuse certain pairs of dependent
instructions to improve their performance if they appear back-to-back in
the instruction stream. In looking at the current support for
instruction fusion in GCC I saw the following 2 options.
1) TARGET_SCHED_MACRO_FUSION
On 2/3/20 2:17 AM, Jiufu Guo wrote:
> +/* { dg-final { scan-rtl-dump-times "REG_BR_PROB 937042044" 1
> "loop2_unroll"} } */
Sorry I didn't catch this addition to the original testcase earlier, but I
wonder how stable this test is going to be. If there are future changes to
default
The following patch factors out some common code to its own function and also
moves the Power6 specific code to a new function.
Bootstrap/regtest on powerpc64le with no regressions. Ok for trunk?
-Pat
2019-11-18 Pat Haugen
* config/rs6000/rs6000.c (move_to_end_of_ready): New
no new regressions and testcase
now passing. Also ran cpu2006/cpu2017 benchmark comparisons with no notable
differences. Ok for trunk?
-Pat
2019-04-15 Pat Haugen
PR target/84369
* config/rs6000/power9.md: Add store forwarding bypass.
Index: gcc/config/rs6000/pow
, not that a
SAD_EXPR was actually generated. So I've updated the tests also.
Ok for trunk?
-Pat
testsuite/ChangeLog:
2019-02-19 Pat Haugen
* lib/target-supports.exp (check_effective_target_vect_usad_char):
Add PowerPC support.
* gcc.dg/vect/slp-reduc-sad.c: Update scan string
The options were removed in May 2018 (r260109), but documentation was not
updated.
Bootstrap on powerpc64le. Ok for trunk?
-Pat
2019-02-12 Pat Haugen
* doc/invoke.texi (RS/6000 and PowerPC Options): Remove duplicate
-maltivec. Delete -maltivec=be and -maltivec=le
On 1/5/19 11:58 AM, Jan Hubicka wrote:
> @@ -791,7 +791,7 @@ want_inline_small_function_p (struct cgr
>ipa_hints hints = estimate_edge_hints (e);
>int big_speedup = -1; /* compute this lazily */
>
> - if (growth <= 0)
> + if (growth <= PARAM_VALUE (PARAM_VALUE
for trunk?
-Pat
2018-11-28 Pat Haugen
PR rtl-optimization/68212
* cfgloopmanip.c (duplicate_loop_to_header_edge): Adjust scale factor.
testsuite/ChangeLog:
2018-11-28 Pat Haugen
PR rtl-optimization/68212
* gcc.dg/pr68212.c: New test.
Index: gcc
On 11/20/18 10:53 AM, Kyrill Tkachov wrote:
> On 20/11/18 16:48, Pat Haugen wrote:
>> On 11/19/18 2:30 PM, Pat Haugen wrote:
>>>> This is a follow-up from
>>>> https://gcc.gnu.org/ml/gcc-patches/2018-11/msg01525.html
>>>> This version introduces
On 11/19/18 2:30 PM, Pat Haugen wrote:
>> This is a follow-up from
>> https://gcc.gnu.org/ml/gcc-patches/2018-11/msg01525.html
>> This version introduces an "artificial" property of the dependencies
>> produced in
>> sched-deps.c th
On 11/19/18 11:54 AM, Kyrill Tkachov wrote:
> On 16/11/18 18:19, Pat Haugen wrote:
>> On 11/8/18 6:10 AM, Kyrill Tkachov wrote:
>>> The attached patch avoids that by making the alap calculation only
>>> look at true dependencies. This shouldn't be too bad, sin
On 11/8/18 6:10 AM, Kyrill Tkachov wrote:
> The attached patch avoids that by making the alap calculation only
> look at true dependencies. This shouldn't be too bad, since we use
> INSN_PRIORITY as the final tie-breaker than that does take
> anti-dependencies into account.
>
> This reduces the
with no regressions. Committed as obvious.
-Pat
2018-10-31 Pat Haugen
* tree-ssa-loop-ivcanon.c (try_peel_loop): Fix typo and remove dead
initialization.
Index: gcc/tree-ssa-loop-ivcanon.c
===
--- gcc/tree-ssa-loop-ivcanon.c
the testcase now passes, ok for trunk?
-Pat
testsuite/ChangeLog:
2018-07-26 Pat Haugen
PR target/86612
* gcc.target/powerpc/pr58673-2.c: Call strdup.
Index: testsuite/gcc.target/powerpc/pr58673-2.c
===
--- testsuite
testsuite/gcc.target/powerpc/loop_align.c fails with this patch. It just needs
a simple tweak to the scan-assembler line since we're no longer generating the
",,31" portion on the .p2align.
-Pat
On 5/17/18 1:57 PM, Segher Boessenkool wrote:
> On Thu, May 17, 2018 at 07:58:20PM +0200, Richard Biener wrote:
>> On May 17, 2018 6:04:36 PM GMT+02:00, Segher Boessenkool
>> <seg...@kernel.crashing.org> wrote:
>>> On Thu, May 17, 2018 at 10:42:46AM -0500, Pat Ha
unk?
-Pat
2018-05-17 Pat Haugen <pthau...@us.ibm.com>
Segher Boessenkool <seg...@kernel.crashing.org>
PR target/85698
* config/rs6000/rs6000.c (rs6000_output_move_128bit): Check dest
operand.
testsuite/ChangeLog:
2018-05-17 Pat Haugen <pthau..
The following patch fixes a couple typos in ppc-asm.h. Committed as
obvious. Will also backport to GCC 6/7 branches.
-Pat
2017-11-21 Pat Haugen <pthau...@us.ibm.com>
* config/rs6000/ppc-asm.h (f50, vs50): Fix values.
Index: gcc/config/rs6000/ppc
On 09/27/2017 12:56 PM, Pat Haugen wrote:
> The following patch corrects some Power9 resource requirements and
> instruction latencies. Bootstrap/regtest on powerpc64le-linux with no
> new regressions. Ok for trunk?
Updated patch follows. Bootstrap/regtest on powerpc64le-linu
On 11/08/2017 11:30 AM, Segher Boessenkool wrote:
>> --- gcc/config/rs6000/power9.md (revision 254377)
>> +++ gcc/config/rs6000/power9.md (working copy)
>> @@ -436,6 +436,12 @@ (define_insn_reservation "power9-qpdiv"
>> (eq_attr "cpu" "power9"))
>>
regressions. Ok for trunk?
-Pat
2017-11-08 Pat Haugen <pthau...@us.ibm.com>
* rs6000/power9.md (power9-qpmul): New.
* rs6000/rs6000.md ("type" attr): Add qmul.
(mul3, fma4_hw, *fms4_hw, *nfma4_hw,
*nfms4_hw, mul3_odd, fma4_odd, *fms4_odd,
Power9 has efficient unaligned load insns. The following patch fixes the
cost to reflect that. There was no similar code for the unaligned_store
case. Bootstrap/regtest on powerpc64le-linux with no new regressions.
Ok for trunk?
-Pat
2017-10-09 Pat Haugen <pthau...@us.ibm.
The following patch corrects some Power9 resource requirements and
instruction latencies. Bootstrap/regtest on powerpc64le-linux with no
new regressions. Ok for trunk?
-Pat
2017-09-27 Pat Haugen <pthau...@us.ibm.com>
* config/rs6000/power9.md (DU_C2_3_power9): Remove an inc
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