Ping.
On 6/30/23 2:26 PM, Pat Haugen via Gcc-patches wrote:
Updated from prior version to address latest review comment (simplify
umod3).
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues
Ping.
On 6/30/23 2:26 PM, Pat Haugen via Gcc-patches wrote:
Updated from prior version to address latest review comment (simplify
umod3).
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues
On 6/30/23 2:26 PM, Pat Haugen via Gcc-patches wrote:
Updated from prior version to address latest review comment (simplify
umod3).
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues
Ping.
On 6/30/23 2:26 PM, Pat Haugen via Gcc-patches wrote:
Updated from prior version to address latest review comment (simplify
umod3).
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues
Updated from prior version to address latest review comment (simplify
umod3).
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input values. This patch disables
their generation
On 6/27/23 1:52 PM, Pat Haugen via Gcc-patches wrote:
Updated from prior version to address review comments (update
rs6000_rtx_cost,
update scan strings of mod-1.c/mod-2.c)l.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can
Updated from prior version to address review comments (update
rs6000_rtx_cost,
update scan strings of mod-1.c/mod-2.c)l.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input
Ping ^3
On 4/18/23 7:22 AM, Pat Haugen via Gcc-patches wrote:
Updated from prior patch to also disable for int128.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input
Ping.
On 4/18/23 7:22 AM, Pat Haugen via Gcc-patches wrote:
Updated from prior patch to also disable for int128.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input values
Ping.
On 4/18/23 7:22 AM, Pat Haugen via Gcc-patches wrote:
Updated from prior patch to also disable for int128.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input values
Updated from prior patch to also disable for int128.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input values. This patch disables
their generation since the equivalent
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input values. This patch disables
their generation since the equivalent div/mul/sub sequence does not suffer
the same problem.
Updated patch with review comments addressed: fixed up testcase and added
another testcase to verify peephole is functional.
Don't force target of modulo into a distinct register.
The define_insns for the modulo operation currently force the target
register
to a distinct reg in preparation
On 2/27/23 2:53 PM, Segher Boessenkool wrote:
Hi!
On Mon, Feb 27, 2023 at 02:12:23PM -0600, Pat Haugen wrote:
On 2/27/23 11:08 AM, Segher Boessenkool wrote:
On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
The define_insns for the modulo operation currently force the target
On 2/27/23 11:08 AM, Segher Boessenkool wrote:
Hi!
On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
The define_insns for the modulo operation currently force the target
register
to a distinct reg in preparation for a possible future peephole combining
div/mod. But this can lead to
Don't force target of modulo into a distinct register.
The define_insns for the modulo operation currently force the target
register
to a distinct reg in preparation for a possible future peephole combining
div/mod. But this can lead to cases of a needless copy being inserted. Fixed
with the
On 1/4/23 3:20 AM, Kewen.Lin via Gcc-patches wrote:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 88c865b6b4b..6fa084c0807 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4378,9 +4378,15 @@ rs6000_option_override_internal (bool
Ping.
On 4/26/22 3:06 PM, Pat Haugen via Gcc-patches wrote:
Fix register count when not splitting Complex IEEE 128-bit args.
For ABI_V4, we do not split complex args. This created a problem because
even though an arg would be passed in two VSX regs, we were only
advancing the
function arg
Fix register count when not splitting Complex IEEE 128-bit args.
For ABI_V4, we do not split complex args. This created a problem because
even though an arg would be passed in two VSX regs, we were only
advancing the
function arg counter by one VSX register. Fixed with this patch.
Ping.
On 2/10/22 4:17 PM, Pat Haugen via Gcc-patches wrote:
Per Alan's comment in the bugzilla, fix attr-retain-* tescases for 32-bit
PowerPC.
Bootstrapped and regression tested on powerpc64(32/64) and powerpc64le.
Ok for master?
-Pat
2022-02-10 Pat Haugen
PR testsuite/100407
Ping.
On 1/28/22 12:03 PM, Pat Haugen via Gcc-patches wrote:
Mark Power10 fusion option undocumented and remove sub-options.
Bootstrapped and regression tested on powerpc64le(Power10).
Ok for master?
-Pat
2022-01-28 Pat Haugen
gcc/
* config/rs6000/rs6000.opt (mpower10-fusion
Per Alan's comment in the bugzilla, fix attr-retain-* tescases for 32-bit
PowerPC.
Bootstrapped and regression tested on powerpc64(32/64) and powerpc64le.
Ok for master?
-Pat
2022-02-10 Pat Haugen
PR testsuite/100407
gcc/testsuite/
* gcc.c-torture/compile/attr-retain-1.c:
Mark Power10 fusion option undocumented and remove sub-options.
Bootstrapped and regression tested on powerpc64le(Power10).
Ok for master?
-Pat
2022-01-28 Pat Haugen
gcc/
* config/rs6000/rs6000.opt (mpower10-fusion): Mark Undocumented.
(mpower10-fusion-ld-cmpi,
Ping. I'll note that I recently discovered that this patch also fixes PR93176
and PR97042.
-Pat
On 11/22/21 1:38 PM, Pat Haugen via Gcc-patches wrote:
> Updated version of the patch. Changes made from original are updated
> commentary to hopefully aid readability, no functional c
Ping.
On 11/22/21 1:38 PM, Pat Haugen via Gcc-patches wrote:
> Updated version of the patch. Changes made from original are updated
> commentary to hopefully aid readability, no functional changes.
>
>
> Implement more two insn constants. rotate_and_mask_constant covers
>
Ping.
On 11/22/21 1:38 PM, Pat Haugen via Gcc-patches wrote:
> Updated version of the patch. Changes made from original are updated
> commentary to hopefully aid readability, no functional changes.
>
>
> Implement more two insn constants. rotate_and_mask_constant covers
>
Ping.
On 11/22/21 1:38 PM, Pat Haugen via Gcc-patches wrote:
> Updated version of the patch. Changes made from original are updated
> commentary to hopefully aid readability, no functional changes.
>
>
> Implement more two insn constants. rotate_and_mask_constant covers
>
Somehow there was an issue when a larger patch was backported, and this chunk
did not make it. Tested and committed as obvious.
-Pat
2021-10-04 Pat Haugen
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/fusion-p10-ldcmpi.c: Update counts.
diff --git
Ping.
On 8/11/21 11:02 AM, Pat Haugen via Gcc-patches wrote:
> Enable store fusion on Power10.
>
> Use the SCHED_REORDER hook to implement Power10 specific ready list
> reordering.
> As of now this is just store fusion.
>
> Things changed in this version of the pat
Enable store fusion on Power10.
Use the SCHED_REORDER hook to implement Power10 specific ready list reordering.
As of now this is just store fusion.
Things changed in this version of the patch
- Separate patch for additional load/store checks
- Move option check from is_fusable_store() to caller
Add additional checks to verify destination[source] of a load[store]
instruction is a register.
Modified code based on review comment to not change general logic of the flow.
Braces needed on inner if-else to prevent error during bootstrap for ambiguous
'else'.
Bootstrap/regtest on powerpc64le
On 8/6/21 11:05 AM, Segher Boessenkool wrote:
> On Fri, Aug 06, 2021 at 10:29:40AM -0500, Pat Haugen wrote:
>> On 8/6/21 10:02 AM, Segher Boessenkool wrote:
- if (GET_CODE (pat) == SET)
+ if (GET_CODE (pat) == SET && REG_P (SET_DEST (pat)))
return find_mem_ref (SET_SRC (pat),
On 8/6/21 10:02 AM, Segher Boessenkool wrote:
> On Fri, Aug 06, 2021 at 09:47:40AM -0500, Pat Haugen wrote:
>> Add additional checks to verify destination[source] of a load[store]
>> instruction is a register.
>
>> * config/rs6000/rs6000.c: (is_load_insn1): Verify destination is a
>>
Add additional checks to verify destination[source] of a load[store]
instruction is a register.
Bootstrap/regtest on powerpc64le with no new regressions. Ok for master?
-Pat
2021-08-06 Pat Haugen
gcc/ChangeLog:
* config/rs6000/rs6000.c: (is_load_insn1): Verify destination is a
On 8/4/21 9:23 AM, Bill Schmidt wrote:
> Hi Pat,
>
> Good stuff! Comments below.
>
> On 8/2/21 3:19 PM, Pat Haugen via Gcc-patches wrote:
>> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
>> index 279f00cc648..1460a0d7c5c 100644
>> --- a/gc
Enable store fusion on Power10.
Use the SCHED_REORDER hook to implement Power10 specific ready list reordering.
As of now, pairing stores for store fusion is the only function being
performed.
Bootstrap/regtest on powerpc64le(Power10) with no new regressions. Ok for
master?
-Pat
2021-08-02
Ping https://gcc.gnu.org/pipermail/gcc-patches/2020-October/555760.html
I've done a current bootstrap/regtest on powerpc64/powerpc64le with no
regressions.
-Pat
On 6/7/21 3:41 PM, Pat Haugen via Gcc-patches wrote:
> Update Power10 scheduling description for new fused instruction types.
>
> Bootstrap/regtest on powerpc64le(Power10) with no new regressions. Ok for
> trunk?
>
> -Pat
>
>
> 2021-06-07 Pat Haugen
>
> g
Update Power10 scheduling description for new fused instruction types.
Bootstrap/regtest on powerpc64le(Power10) with no new regressions. Ok for
trunk?
-Pat
2021-06-07 Pat Haugen
gcc/ChangeLog:
* config/rs6000/power10.md (power10-fused-load, power10-fused-store,
On 6/2/21 9:19 AM, Segher Boessenkool wrote:
> On Wed, Jun 02, 2021 at 08:23:48AM -0500, Pat Haugen wrote:
>> On 6/2/21 7:01 AM, Richard Biener wrote:
>>> So did you check the RTL (and alias-sets) produced by
>>> __builtin_return_address? Test coverage might
>>> be low here and w/o scheduling
On 6/2/21 7:01 AM, Richard Biener wrote:
> On Wed, Jun 2, 2021 at 1:15 PM Pat Haugen wrote:
>>
>> On 6/2/21 1:51 AM, Richard Biener wrote:
>>> On Tue, Jun 1, 2021 at 10:37 PM Pat Haugen via Gcc-patches
>>> wrote:
>>>>
>>>> Make sure link
On 6/2/21 1:51 AM, Richard Biener wrote:
> On Tue, Jun 1, 2021 at 10:37 PM Pat Haugen via Gcc-patches
> wrote:
>>
>> Make sure link reg save MEM has frame alias set, to match other link reg
>> save/restore code.
>>
>> Bootstrap/regtest on powerpc64/pow
Make sure link reg save MEM has frame alias set, to match other link reg
save/restore code.
Bootstrap/regtest on powerpc64/powerpc64le with no new regressions. Ok for
trunk?
-Pat
2021-06-01 Pat Haugen
gcc/ChangeLog:
* config/rs6000/rs6000-logue.c (rs6000_emit_prologue): Use
On 5/7/21 6:00 PM, Segher Boessenkool wrote:
>> --- a/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c
>> @@ -62,6 +62,6 @@ rlnm_test_2 (vector unsigned long long x, vector unsigned
>> long long y,
>> /* { dg-final { scan-assembler-times
Add ALTIVEC_REGS as pressure class.
Code that has heavy register pressure on Altivec registers can suffer from
over-aggressive scheduling during sched1, which then leads to increased
register spill. This is due to the fact that registers that prefer
ALTIVEC_REGS are currently assigned an allocno
Update prefixed attribute for Power10.
This patch creates a new attribute, "maybe_prefixed", which is used to mark
those instructions that may have a prefixed form. The existing "prefixed"
attribute is now used to mark all instructions that are prefixed form.
This patch differs from the prior
On 3/18/21 11:33 AM, will schmidt wrote:
> Per this change:
>
> +;; Whether an insn is a prefixed insn. A prefixed instruction has a prefix
> +;; instruction word that conveys additional information such as a larger
> +;; immediate, additional operands, etc., in addition to the normal
>
Update prefixed attribute for Power10.
This patch creates a new attribute, prepend_prefixed_insn, which is used to mark
those instructions that are prefixed and need to have a 'p' prepended to their
mnemonic at asm emit time. The existing "prefix" attribute is now used to mark
all instructions
Ping3
On 2/18/21 2:30 PM, Pat Haugen via Gcc-patches wrote:
> Ping2
>
> On 1/26/21 11:27 AM, Pat Haugen via Gcc-patches wrote:
>> Ping
>>
>> On 12/8/20 3:46 PM, Pat Haugen via Gcc-patches wrote:
>>> Update size attribute for Power10.
>>>
>>&
Ping3
On 2/18/21 2:31 PM, Pat Haugen via Gcc-patches wrote:
> Ping2.
>
> On 1/26/21 11:30 AM, Pat Haugen via Gcc-patches wrote:
>> Ping.
>>
>> On 11/13/20 4:04 PM, Pat Haugen via Gcc-patches wrote:
>>> Add Power10 scheduling description.
>>>
>>&
Rename next_insn_prefixed_p for improved clarity.
Bootstrap/regtest on powerpc64le with no new regressions. Ok for trunk?
-Pat
2021-02-22 Pat Haugen
gcc/
* config/rs6000/rs6000.c (next_insn_prefixed_p): Rename.
(rs6000_final_prescan_insn): Adjust.
Ping2.
On 1/26/21 11:30 AM, Pat Haugen via Gcc-patches wrote:
> Ping.
>
> On 11/13/20 4:04 PM, Pat Haugen via Gcc-patches wrote:
>> Add Power10 scheduling description.
>>
>> This patch adds the Power10 scheduling description. Since power10.md was
>> pretty
Ping2.
On 1/26/21 11:28 AM, Pat Haugen via Gcc-patches wrote:
> Ping.
>
> On 12/10/20 3:32 PM, Pat Haugen via Gcc-patches wrote:
>> Update prefixed attribute for Power10.
>>
>>
>> This patch was broken out from my larger patch to update various attributes
&g
Ping2
On 1/26/21 11:27 AM, Pat Haugen via Gcc-patches wrote:
> Ping
>
> On 12/8/20 3:46 PM, Pat Haugen via Gcc-patches wrote:
>> Update size attribute for Power10.
>>
>>
>> This patch was broken out from my larger patch to update various attributes
>> for
Ping.
On 11/13/20 4:04 PM, Pat Haugen via Gcc-patches wrote:
> Add Power10 scheduling description.
>
> This patch adds the Power10 scheduling description. Since power10.md was
> pretty much a complete rewrite (existing version of power10.md is mostly just
> a copy of power
Ping.
On 12/10/20 3:32 PM, Pat Haugen via Gcc-patches wrote:
> Update prefixed attribute for Power10.
>
>
> This patch was broken out from my larger patch to update various attributes
> for
> Power10, in order to make the review process hopefully easier. This patch only
&g
Ping
On 12/8/20 3:46 PM, Pat Haugen via Gcc-patches wrote:
> Update size attribute for Power10.
>
>
> This patch was broken out from my larger patch to update various attributes
> for
> Power10, in order to make the review process hopefully easier. This patch only
> updat
On 12/10/20 8:41 PM, acsawdey--- via Gcc-patches wrote:
> + [(set_attr "type" "logical")
Similar to load-cmp fusion pairs, we need a new insn type here.
-Pat
On 12/4/20 1:19 PM, acsawdey--- via Gcc-patches wrote:
> + print " [(set_attr \"type\" \"load\")\n";
We need to tag these with a new instruction type, such as 'fused-load-cmp', so
the scheduler can distinguish them from normal loads.
-Pat
Fix instruction length for MMA insns.
Prefixed instructions should not have their length explicitly set to '8'. The
function get_attr_length() will adjust the length appropriately based on the
value of the "prefixed" attribute.
Bootstrap/regtest on powerpc64le (Power8/Power10) with no new
Update prefixed attribute for Power10.
This patch was broken out from my larger patch to update various attributes for
Power10, in order to make the review process hopefully easier. This patch only
updates the prefix attribute for various new instructions. Changes in this
version include missed
Update size attribute for Power10.
This patch was broken out from my larger patch to update various attributes for
Power10, in order to make the review process hopefully easier. This patch only
updates the size attribute for various new instructions. There were no changes
requested to this
On 11/24/20 8:17 PM, Pat Haugen via Gcc-patches wrote:
> On 11/24/20 12:59 PM, Carl Love via Gcc-patches wrote:
>> +
>> +(define_insn "dives_"
>> + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
>> +(unspec:
On 11/24/20 12:59 PM, Carl Love via Gcc-patches wrote:
> +
> +(define_insn "dives_"
> + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +(unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v")
> + (match_operand:VIlong 2 "vsx_register_operand"
On 11/4/20 10:44 AM, Carl Love via Gcc-patches wrote:
> +
> +(define_insn "vdives_"
> + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +(unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v")
> + (match_operand:VIlong 2 "vsx_register_operand"
On 11/17/20 10:31 PM, will schmidt wrote:
> On Fri, 2020-11-13 at 16:04 -0600, Pat Haugen via Gcc-patches wrote:
>> +(define_automaton "power10dsp,power10issue,power10div")
>> +
>> +; Decode/dispatch slots
>> +(define_cpu_unit "du0_p
Add Power10 scheduling description.
This patch adds the Power10 scheduling description. Since power10.md was pretty
much a complete rewrite (existing version of power10.md is mostly just a copy
of power9.md), I diffed power10.md with /dev/null so that the full contents of
the file are shown as
On 11/12/20 10:05 AM, Jeff Law wrote:
>> I have coded up a proof of concept that implements our needs via a new
>> target hook. The hook is passed a pair of dependent insns and returns if
>> they are a fusion candidate. It is called while removing the forward
>> dependencies of the just scheduled
On 11/5/20 4:32 PM, will schmidt wrote:
> On Wed, 2020-11-04 at 14:42 -0600, Pat Haugen via Gcc-patches wrote:
>> * config/rs6000/rs6000.c (rs6000_final_prescan_insn): Only add 'p' for
>> PREFIXED_YES.
>
> The code change reads as roughly
> - next_insn_p
Update instruction attributes for Power10.
This patch updates the type/prefixed/dot/size attributes for various new
instructions (and a couple existing that were incorrect) in preparation for the
Power10 scheduling patch that will be following.
Bootstrap/regtest on powerpc64le
On 9/24/20 10:59 AM, will schmidt via Gcc-patches wrote:
> +;; Move DI value from GPR to TI mode in VSX register, word 1.
> +(define_insn "mtvsrdd_diti_w1"
> + [(set (match_operand:TI 0 "register_operand" "=wa")
> + (unspec:TI [(match_operand:DI 1 "register_operand" "r")]
> +
The following is mostly a mechanical change to rename the mffgpr/mftgpr
insn types to mtvsr/mfvsr to be more clear. It also removes Power6
references to those insn types since we no longer generate those
instructions.
Bootstrap/regtest on powerpc64le with no new regressions. Ok for trunk?
-Pat
On 9/9/20 4:41 PM, Segher Boessenkool wrote:
> Hi!
>
> On Wed, Sep 09, 2020 at 04:14:37PM -0500, Pat Haugen wrote:
>> I noticed that some of the VSR<->GPR move instructions are not typed
>> correctly. This patch fixes those instructions so that the scheduler
>> treats them with the correct
I noticed that some of the VSR<->GPR move instructions are not typed
correctly. This patch fixes those instructions so that the scheduler
treats them with the correct latency.
Bootstrap/regtest on powerpc64le with no new regressions. Also ran a
CPU2017 benchmark comparison on Power9 with no major
Disable -fcaller-saves by default.
This patch turns off -fcaller-saves by default so that IRA doesn't try
to use volatile regs for pseudos that are live across a call, which
would then require LRA to save/restore the reg around the call.
Bootstrap/regtest on powerpc64le with no new regressions.
On 4/8/20 2:46 AM, Richard Biener wrote:
>> I have coded up a proof of concept that implements our needs via a new
>> target hook. The hook is passed a pair of dependent insns and returns if
>> they are a fusion candidate. It is called while removing the forward
>> dependencies of the just
The Power processor has the ability to fuse certain pairs of dependent
instructions to improve their performance if they appear back-to-back in
the instruction stream. In looking at the current support for
instruction fusion in GCC I saw the following 2 options.
1) TARGET_SCHED_MACRO_FUSION
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