Hi,
This patch is removing unnecessary armv9-a multilib variant which was
introduced in commit 32ba7860ccaddd5219e6dae94a3d0653e124c9dd (add
armv9-a architecture to -march). Now armv9-a(+simd) multilibs point to
already existing armv8-a(+simd) ones as there are no changes between
the two.
Users
Ping :)
> This patch is sorting issue with LS64 intrinsics tests failing with
> aarch64-linux-gnu_ilp32 target.
>
> Regtested on aarch64-linux-gnu_ilp32, aarch64-elf and aarch64_be-elf
> and no issues.
>
> OK to install?
>
> gcc/ChangeLog:
>
> PR target/103729
> *
This patch is sorting issue with LS64 intrinsics tests failing with
aarch64-linux-gnu_ilp32 target.
Regtested on aarch64-linux-gnu_ilp32, aarch64-elf and aarch64_be-elf
and no issues.
OK to install?
gcc/ChangeLog:
PR target/103729
*
> -Original Message-
> From: Richard Sandiford
> Sent: 16 December 2021 10:46
> To: Przemyslaw Wirkus
> Cc: gcc-patches@gcc.gnu.org; christophe.l...@linaro.org; Richard Earnshaw
> ; Kyrylo Tkachov ;
> Marcus Shawcroft
> Subject: Re: [PATCH][GCC] aarch64: fix: ls64 tests fail on
Hi,
This patch is sorting issue with LS64 intrinsics tests failing with
AArch64_be targets.
Regtested on aarch64_be_elf and aarch64_elf, no issues.
OK to install?
gcc/ChangeLog:
PR target/PR103729
* config/aarch64/aarch64-simd.md (aarch64_movv8di): Allow big endian
> -Original Message-
> From: Richard Sandiford
> Sent: 14 December 2021 11:58
> To: Przemyslaw Wirkus
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
> ; Marcus Shawcroft
> ; Kyrylo Tkachov
> Subject: Re: [PATCH][GCC] aarch64: Add LS64 extension and intrinsics
>
> Przemyslaw Wirkus
Hello Richard,
I've updated my patch following all your comments. Thank you.
Boostrapped on aarch64-linux-gnu and all new ACLE tests pass.
OK to install?
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins):
Define AARCH64_LS64_BUILTIN_LD64B,
> -Original Message-
> From: Richard Sandiford
> Sent: 17 November 2021 10:08
> To: Przemyslaw Wirkus
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
> ; Kyrylo Tkachov ;
> Marcus Shawcroft
> Subject: Re: [PATCH][GCC] aarch64: Add new vector mode V8DI
>
> Oops, only just realised
Hi,
This patch is adding support for LS64 (Armv8.7-A Load/Store 64 Byte extension)
which is part of Armv8.7-A architecture. Changes include missing plumbing for
TARGET_LS64, LS64 data structure and intrinsics defined in ACLE [0]. Machine
description of intrinsics is using new V8DI mode added in a
> > Hi,
> >
> > This patch is adding support for Cortex-A710 CPU [0].
> >
> > [0] https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a710
> >
> > OK for master?
> Ok.
> Thanks,
> Kyrill
commit 9701f153f6dfcc365ac0d96cdcf7df69a2de81dc
> >
> > gcc/ChangeLog:
> >
> > *
Hi,
This patch is adding new V8DI mode which will be used with new Armv8.7-A
LS64 extension intrinsics.
Regtested on aarch64-elf and no issues.
OK for master?
gcc/ChangeLog:
2021-11-10 Przemyslaw Wirkus
* config/aarch64/aarch64-modes.def (VECTOR_MODE): New V8DI mode.
*
> > > -Original Message-
> > > From: Przemyslaw Wirkus
> > > Sent: 18 October 2021 10:37
> > > To: gcc-patches@gcc.gnu.org
> > > Cc: Richard Earnshaw ; Ramana
> > > Radhakrishnan ; Kyrylo Tkachov
> > > ; ni...@redhat.com
> > > Subject: [PATCH][GCC] arm: add armv9-a architecture to -march
>
Ping :)
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 18 October 2021 10:40
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Ramana Radhakrishnan
> ; Kyrylo Tkachov
> ; ni...@redhat.com
> Subject: [PATCH][GCC] arm: enable cortex-a710 CPU
>
> Hi,
>
> This patch is adding
Ping :)
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 18 October 2021 10:37
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Ramana
> Radhakrishnan ; Kyrylo Tkachov
> ; ni...@redhat.com
> Subject: [PATCH][GCC] arm: add armv9-a architecture to -march
>
> Hi,
>
> This patch
Hi,
This patch is adding support for Cortex-A710 CPU [0].
[0] https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a710
OK for master?
gcc/ChangeLog:
* config/arm/arm-cpus.in (cortex-a710): New CPU.
* config/arm/arm-tables.opt: Regenerate.
*
Hi,
This patch is adding `armv9-a` to -march in Arm GCC.
In this patch:
+ Add `armv9-a` to -march.
+ Update multilib with armv9-a and armv9-a+simd.
After this patch three additional multilib directories are available:
$ arm-none-eabi-gcc --print-multi-lib
.;
[...vanilla
m all for it. Maintaining these
> configurations are a pain.
OK, let's discard this patch as there is no consensus it's useful.
Cheers!
/Przemyslaw
> --joel
> On 22/09/2021 09:46, Przemyslaw Wirkus via Gcc-patches wrote:
> > Patch is adding multilib entries for `cortex-r52plus
> Subject: RE: [PATCH][GCC] aarch64: enable cortex-x2 CPU
>
>
>
> > -Original Message-
> > From: Kyrylo Tkachov
> > Sent: Friday, October 1, 2021 1:17 PM
> > To: Przemyslaw Wirkus ; gcc-
> > patc...@gcc.gnu.org
> > Cc: Richard Earnshaw ; Richard Sandiford
> > ; Marcus Shawcroft
> >
> >
> Hi Przemek,
>
> > -Original Message-
> > From: Przemyslaw Wirkus
> > Sent: Wednesday, September 22, 2021 9:35 AM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Richard Earnshaw ; Richard Sandiford
> > ; Marcus Shawcroft
> > ; Kyrylo Tkachov
>
> > Subject: [PATCH][GCC] aarch64: enable
> -Original Message-
> From: Kyrylo Tkachov
> Sent: 01 October 2021 13:16
> To: Przemyslaw Wirkus ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Marcus Shawcroft
>
> Subject: RE: [PATCH][GCC] aarch64: enable cortex-a710 CPU
>
>
>
> > -Original
Patch is fixing AARCH64_FL_V9 flag value which is now wrongly set due to
merge error.
Committed as obvious.
gcc/ChangeLog:
* config/aarch64/aarch64.h (AARCH64_FL_V9): Update value.
---
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index
> > Subject: [PATCH][GCC] aarch64: add armv9-a to -march
> >
> > Patch is adding new command line option 'armv9-a' to -march.
> >
> > OK for master?
>
> Ok.
commit f0688d42c9b74a6999548ff2e79ae440b049b87f
> Thanks,
> Kyrill
>
> >
> > gcc/ChangeLog:
> >
> > 2021-09-22 Przemyslaw Wirkus
> >
>
> Subject: Re: [PATCH][GCC] arm: Enable Cortex-R52+ CPU
>
> This is OK
Applying as r52+ is now in Binutils.
commit cd08eae26ed23497ace5f4ee6f3a41eb5bd36c38
> Ramana
>
> On 22/09/2021, 09:45, "Przemyslaw Wirkus"
> wrote:
>
> Patch is adding Cortex-R52+ as 'cortex-r52plus' command line
>
> Subject: Re: [PATCH][GCC] arm: Add Cortex-R52+ multilib
>
> I think the RTEMS multilibs are based on the products that RTEMS supports,
> so this is really the RTEMS maintainers' call.
>
> Joel?
Ping :)
> On 22/09/2021 09:46, Przemyslaw Wirkus via Gcc-patches wrote
Patch is adding multilib entries for `cortex-r52plus` CPU.
See: https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r52-plus
OK for master?
gcc/ChangeLog:
2021-09-16 Przemyslaw Wirkus
* config/arm/t-rtems: Add "-mthumb -mcpu=cortex-r52plus
-mfloat-abi=hard"
Patch is adding Cortex-R52+ as 'cortex-r52plus' command line
flag for -mcpu option.
See: https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r52-plus
OK for master?
gcc/ChangeLog:
2021-09-22 Przemyslaw Wirkus
* config/arm/arm-cpus.in: Add Cortex-R52+ CPU.
*
Patch is adding 'cortex-x2' to -mcpu command line option.
OK for master?
gcc/ChangeLog:
2021-09-02 Przemyslaw Wirkus
* config/aarch64/aarch64-cores.def (AARCH64_CORE): New
Cortex-X2 core.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Update
Patch is adding 'cortex-a710' to -mcpu command line option.
gcc/ChangeLog:
2021-09-02 Przemyslaw Wirkus
* config/aarch64/aarch64-cores.def (AARCH64_CORE): New
Cortex-A710 core.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Update docs.
Patch is adding 'cortex-a510' to -mcpu command line option.
gcc/ChangeLog:
2021-09-02 Przemyslaw Wirkus
* config/aarch64/aarch64-cores.def (AARCH64_CORE): New
Cortex-A510 core.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Update docs.
Patch is adding new command line option 'armv9-a' to -march.
OK for master?
gcc/ChangeLog:
2021-09-22 Przemyslaw Wirkus
* config/aarch64/aarch64-arches.def (AARCH64_ARCH): Added
armv9-a.
* config/aarch64/aarch64.h (AARCH64_FL_V9): New.
(AARCH64_FL_FOR_ARCH9):
us
> > > Cc: Vladimir Makarov ; ja...@redhat.com;
> > > Richard Earnshaw ; Richard Biener
> > > ; gcc-patches@gcc.gnu.org; Ramana Radhakrishnan
> > >
> > > Subject: Re: [backport gcc10, gcc9] Requet to backport PR97969
> > >
> > > On
0, gcc9] Requet to backport PR97969
>
> On Thu, 3 Jun 2021 at 00:31, Przemyslaw Wirkus via Gcc-patches patc...@gcc.gnu.org> wrote:
> >
> > Hi,
> >
> > > -Original Message-
> > > From: Vladimir Makarov
> > > Sent: 31 May 2021 16:52
>
Hi,
> -Original Message-
> From: Vladimir Makarov
> Sent: 31 May 2021 16:52
> To: Przemyslaw Wirkus ; Richard Biener
>
> Cc: gcc-patches@gcc.gnu.org; ja...@redhat.com; ni...@redhat.com;
> Richard Earnshaw ; Ramana Radhakrishnan
> ; Kyrylo Tkachov
>
> Subject: Re: [backport gcc10, gcc9]
> -Original Message-
> From: Richard Biener
> Sent: 02 February 2021 10:08
> To: Przemyslaw Wirkus
> Cc: Vladimir Makarov ; gcc-patches@gcc.gnu.org;
> ja...@redhat.com; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
> ; Kyrylo Tkachov
>
> Subject: RE: [backport gcc10, gcc9]
> On 2021-01-18 7:50 a.m., Richard Biener wrote:
> > On Mon, 18 Jan 2021, Przemyslaw Wirkus wrote:
> >
> >> Hi all,
> >>
> >> Can we backport PR97969 patch to GCC 10 and (maybe) GCC 9 ?:
> >> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97969
> >>
> >> IMHO bug is severe and could land in GCC 10
Hi,
Can we backport PR94230 patch (add a new diagnostic
flag -flarge-source-files) to GCC 10 ?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94230
PR94230 backport will benefit people moving from
GCC 9 to GCC 10 who face issue while working with
large header/source files.
See example issue on
Hi all,
Can we backport PR97969 patch to GCC 10 and (maybe) GCC 9 ?:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97969
IMHO bug is severe and could land in GCC 10 and 9. Vladimir's original patch:
https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563322.html
applies without changes to both
> Przemyslaw Wirkus writes:
> > > This is a bug in the vectoriser: the vectoriser shouldn't generate
> > > IFN_REDUC_MAX calls that the target doesn't support.
> > >
> > > I think the problem comes from using the wrong interface to get the
> > > index type for a COND_REDUCTION.
> > Subject: [PATCH][GCC] arm: Add support for Cortex-A78C
> >
> > This patch adds support for -mcpu=cortex-a78c command line option.
> > For more information about this processor, see [0]:
> >
> > [0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-
> > a78c
> >
> > OK from
> Przemyslaw Wirkus writes:
> > Hi,
> >
> > Recent 'support SVE comparisons for unpacked integers' patch extends
> > operands of define_expands from SVE_FULL to SVE_ALL. This causes an
> > ICE hence this PR patch.
> >
> > This patch adds this relaxation for:
> > + reduc__scal_ and
> > +
Hi,
Recent 'support SVE comparisons for unpacked integers' patch extends
operands of define_expands from SVE_FULL to SVE_ALL. This causes an ICE
hence this PR patch.
This patch adds this relaxation for:
+ reduc__scal_ and
+ arch64_pred_reduc__
in order to support extra modes. Missing modes were
> > OK for master ?
> >
> > gcc/ChangeLog:
> >
> > * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-
> A78C core.
> > * config/aarch64/aarch64-tune.md: Regenerate.
> > * doc/invoke.texi: Update docs.
>
> OK, thanks.
> Richard
commit
> > Subject: [PATCH][GCC] aarch64: Add +pauth to -march
> >
> > New +pauth (Pointer Authentication from Armv8.3-A) feature option for
> > -march command line option.
> >
> > Please note that majority of PAUTH instructions are implemented behind
> > HINT instruction. PAUTH stays a Armv8.3-A feature
This patch adds support for -mcpu=cortex-a78c command line option.
For more information about this processor, see [0]:
[0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c
OK from master ?
gcc/ChangeLog:
* config/arm/arm-cpus.in: Add Cortex-A78C core.
*
This patch adds support for -mcpu=cortex-a78c command line option.
For more information about this processor, see [0]:
[0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c
OK for master ?
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add
New +pauth (Pointer Authentication from Armv8.3-A) feature option for
-march command line option.
Please note that majority of PAUTH instructions are implemented behind HINT
instruction. PAUTH stays a Armv8.3-A feature but now can be assigned to other
architectures or CPUs.
Patch includes:
- new
> >> >> gcc/ChangeLog:
> >> >>
> >> >> * config/aarch64/aarch64-option-extensions.def
> >> >> (AARCH64_OPT_EXTENSION): New +flagm option in -march for AArch64.
> >> >> * config/aarch64/aarch64.h (AARCH64_FL_FLAGM): Add new flagm
> >> >> extension bit mask.
> >> >> (AARCH64_FL_FOR_ARCH8_4): Add
> >> gcc/ChangeLog:
> >>
> >> * config/aarch64/aarch64-option-extensions.def
> >> (AARCH64_OPT_EXTENSION): New +flagm option in -march for AArch64.
> >> * config/aarch64/aarch64.h (AARCH64_FL_FLAGM): Add new flagm
> >> extension bit mask.
> >> (AARCH64_FL_FOR_ARCH8_4): Add flagm to Armv8.4-A.
> >
New +flagm (Condition flag manipulation from Armv8.4-A) feature option for
-march command line option.
Please note that FLAGM stays an Armv8.4-A feature but now can be
assigned to other architectures or CPUs.
OK for master?
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def
> > Backport of commit 6abd428605e3a279e533fde1cecbc9735ce03b66
> > from master branch.
> >
> > OK for gcc-10 ?
Cherry-picked and applied: commit eb061188276d0ac9ec53fd5619c578a6bce6b129
> Ok.
> Thanks,
> Kyrill
> > This patch is a backport of PR97251 fix already commited to master.
> >
> > OK for gcc-10 branch ?
Cherry-picked and applied: commit d121b3259b77203e62402024add1538c1bdf5fdf
> Ok.
> Thanks,
> Kyrill
Backport of commit 6abd428605e3a279e533fde1cecbc9735ce03b66
from master branch.
OK for gcc-10 ?
This patch fixes ICEs in gcc.dg/torture/float16-basic.c for
-march=armv8.1-m.main+mve -mfloat-abi=hard. The problem was
that an fp16 argument was (rightly) being passed in FPRs,
but the fp16 move
This patch is a backport of PR97251 fix already commited to master.
OK for gcc-10 branch ?
This patch fixes ICEs when compiling
gcc/testsuite/gcc.target/arm/pure-code/no-literal-pool.c with
-mfp16-format=ieee -mfloat-abi=hard -march=armv8.1-m.main+mve
-mpure-code.
The existing conditions in the
> > Subject: [PATCH][GCC][ARM] Add support for Cortex-A78 and Cortex-A78AE
> >
> > This patch introduces support for Cortex-A78 [0] and Cortex-A78AE [1]
> > cpus.
> >
> > [0]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-
> > a78
> > [1]:
> > Subject: [PATCH][GCC][AArch64] Add support for Cortex-A78 and Cortex-
> > A78AE
> >
> > This patch introduces support for Cortex-A78 [0] and Cortex-A78AE [1]
> > cpus.
> >
> > [0]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78
> > [1]:
> >
This patch introduces support for Cortex-A78 [0] and Cortex-A78AE [1]
cpus.
[0]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78
[1]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78ae
OK for master branch ?
kind regards
Przemyslaw Wirkus
This patch introduces support for Cortex-A78 [0] and Cortex-A78AE [1]
cpus.
[0]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78
[1]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78ae
OK for master branch ?
kind regards
Przemyslaw Wirkus
gcc/ChangeLog:
> Ok. Please make sure aarch64-tune.md is properly regenerated when
> committing as Alex has been adding new CPUs in there recently too.
commit f836f3bc8f76ef3e3ad21762590302ad11abc9f8
> Thanks,
> Kyrill
>
> >
> > kind regards,
> > Przemyslaw Wirkus
> >
> > gcc/ChangeLog:
> >
> > *
> Ok, but please make sure this is properly rebased on top of Alex's patches
> that have recently gone in in this area.
commit 0eef5eea2b42d892df52b655e55458f27ac3fb81
> Thanks,
> Kyrill
>
>
> kind regards,
> Przemyslaw Wirkus
>
> gcc/ChangeLog:
>
> * config/arm/arm-cpus.in:
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