On Wed, 31 Oct 2018 at 00:37, James Greenhalgh wrote:
>
> On Tue, Oct 30, 2018 at 05:12:58AM -0500, Sameera Deshpande wrote:
> > On Fri, 26 Oct 2018 at 13:33, Sameera Deshpande
> > wrote:
> > >
> > > Hi!
> > >
> > > Please
On Tue, 30 Oct 2018 at 16:16, Richard Earnshaw (lists)
wrote:
>
> On 30/10/2018 10:09, Sameera Deshpande wrote:
> > On Tue, 9 Oct 2018 at 04:08, Eric Botcazou wrote:
> >>
> >>> Other notes need not be changed, as they don't hold renamed register
> >&
On Fri, 26 Oct 2018 at 13:33, Sameera Deshpande
wrote:
>
> Hi!
>
> Please find attached the patch to add a pipeline description for the
> Qualcomm Saphira core. It is tested with a bootstrap and make check,
> with no regressions.
>
> Ok for trunk?
>
> gcc/
>
On Tue, 9 Oct 2018 at 04:08, Eric Botcazou wrote:
>
> > Other notes need not be changed, as they don't hold renamed register
> > information.
> >
> > Ok for trunk?
>
> No, REG_DEAD & REG_UNUSED note must be recomputed by passes consuming them.
>
>
Hi!
Please find attached the patch to add a pipeline description for the
Qualcomm Saphira core. It is tested with a bootstrap and make check,
with no regressions.
Ok for trunk?
gcc/
Changelog:
2018-10-26 Sameera Deshpande
* config/aarch64/aarch64-cores.def (saphira): Use saphira pipeline
to finally rename the register is made - where the note can
be altered with new regname.
Other notes need not be changed, as they don't hold renamed register
information.
Ok for trunk?
Changelog:
2018-10-09 Sameera Deshpande diff --git a/gcc/regrename.c b/gcc/regrename.c
index 8424093..a3446a2 100644
On Mon 9 Apr, 2018, 2:06 PM Sameera Deshpande,
wrote:
> Hi Richard,
>
> I do not see the said patch applied in ToT yet. When do you expect it
> to be available in ToT?
>
> - Thanks and regards,
> Sameera D.
>
> On 30 March 2018 at 17:01, Sameera Deshpan
On Tue 29 May, 2018, 9:19 PM Siddhesh Poyarekar, <
siddhesh.poyare...@linaro.org> wrote:
> On 29 May 2018 at 21:17, James Greenhalgh
> wrote:
> > On Tue, May 29, 2018 at 05:01:42AM -0500, Sameera Deshpande wrote:
> >> Hi!
> >>
> >> Please find
Hi!
Please find attached the patch to add support of ARMv8.4 in saphira
for Qualcomm server part. Tested on aarch64, without any regressions.
Ok for trunk?
--
- Thanks and regards,
Sameera D.
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index
On Tue 22 May, 2018, 9:26 PM James Greenhalgh, <james.greenha...@arm.com>
wrote:
> On Mon, Apr 30, 2018 at 06:35:11PM -0500, Sameera Deshpande wrote:
> > On 13 April 2018 at 20:21, James Greenhalgh <james.greenha...@arm.com>
> wrote:
> > > On Fri, Apr 13,
On 1 May 2018 at 05:05, Sameera Deshpande <sameera.deshpa...@linaro.org> wrote:
> On 13 April 2018 at 20:21, James Greenhalgh <james.greenha...@arm.com> wrote:
>> On Fri, Apr 13, 2018 at 03:39:32PM +0100, Sameera Deshpande wrote:
>>> On Fri 13 Apr,
On 13 April 2018 at 20:21, James Greenhalgh <james.greenha...@arm.com> wrote:
> On Fri, Apr 13, 2018 at 03:39:32PM +0100, Sameera Deshpande wrote:
>> On Fri 13 Apr, 2018, 8:04 PM James Greenhalgh,
>> <james.greenha...@arm.com<mailto:james.greenha...@arm.com>> wro
On Fri 13 Apr, 2018, 8:04 PM James Greenhalgh, <james.greenha...@arm.com>
wrote:
> On Fri, Apr 06, 2018 at 08:55:47PM +0100, Christophe Lyon wrote:
> > Hi,
> >
> > 2018-04-06 12:15 GMT+02:00 Sameera Deshpande <
> sameera.deshpa...@linaro.org>:
> > > Hi
On 11 April 2018 at 15:53, Sudakshina Das <sudi@arm.com> wrote:
> Hi Sameera
>
>
> On 11/04/18 09:04, Sameera Deshpande wrote:
>>
>> On 10 April 2018 at 20:07, Sudakshina Das <sudi@arm.com> wrote:
>>>
>>> Hi Sameera
On 10 April 2018 at 20:07, Sudakshina Das <sudi@arm.com> wrote:
> Hi Sameera
>
>
> On 10/04/18 11:20, Sameera Deshpande wrote:
>>
>> On 7 April 2018 at 01:25, Christophe Lyon <christophe.l...@linaro.org>
>> wrote:
>>>
>>&
On 7 April 2018 at 01:25, Christophe Lyon <christophe.l...@linaro.org> wrote:
> Hi,
>
> 2018-04-06 12:15 GMT+02:00 Sameera Deshpande <sameera.deshpa...@linaro.org>:
>> Hi Christophe,
>>
>> Please find attached the updated patch with testcases.
>&g
Hi Richard,
I do not see the said patch applied in ToT yet. When do you expect it
to be available in ToT?
- Thanks and regards,
Sameera D.
On 30 March 2018 at 17:01, Sameera Deshpande
<sameera.deshpa...@linaro.org> wrote:
> Hi Richard,
>
> The testcase is working with the patc
Hi Christophe,
Please find attached the updated patch with testcases.
Ok for trunk?
- Thanks and regards,
Sameera D.
2017-12-14 22:17 GMT+05:30 Christophe Lyon <christophe.l...@linaro.org>:
> 2017-12-14 9:29 GMT+01:00 Sameera Deshpande <sameera.deshpa...@linaro.org>:
>>
Hi Richard,
The testcase is working with the patch you suggested, thanks for
pointing that out.
On 30 March 2018 at 16:54, Sameera Deshpande
<sameera.deshpa...@linaro.org> wrote:
> On 30 March 2018 at 16:39, Richard Sandiford
> <richard.sandif...@linaro.org> wrote:
d attached the updated patch.
>>
>> I have tested it for gcc testsuite and the failing testcase. Ok for trunk?
>>
>> On 22 March 2018 at 19:06, Sudakshina Das <sudi....@arm.com> wrote:
>>> Hi Sameera
>>>
>>> On 22/03/18 02:07, Sameera Deshp
Hi Sudakshina,
That testcase cannot be addwd as of now, as it needs approval from client.
On Thu 29 Mar, 2018, 9:01 PM Sudakshina Das, <sudi@arm.com> wrote:
> Hi Sameera
>
> On 29/03/18 11:44, Sameera Deshpande wrote:
> > Hi Sudakshina,
> >
> > Than
, Sudakshina Das <sudi@arm.com> wrote:
> Hi Sameera
>
> On 22/03/18 02:07, Sameera Deshpande wrote:
>>
>> Hi Sudakshina,
>>
>> As per the ARMv8 ARM, for the offset range (-1048576 ,1048572), the
>> far branch instruction offset is inclus
@arm.com> wrote:
> On 15/03/18 15:27, Sameera Deshpande wrote:
>>
>> Ping!
>>
>> On 28 February 2018 at 16:18, Sameera Deshpande
>> <sameera.deshpa...@linaro.org> wrote:
>>>
>>> On 27 February 2018 at 18:25, Ramana Radhakrishnan
>>> &
Ping!
On 28 February 2018 at 16:18, Sameera Deshpande
<sameera.deshpa...@linaro.org> wrote:
> On 27 February 2018 at 18:25, Ramana Radhakrishnan
> <ramana@googlemail.com> wrote:
>> On Wed, Feb 14, 2018 at 8:30 AM, Sameera Deshpande
>> <sameera.de
On 27 February 2018 at 18:25, Ramana Radhakrishnan
<ramana@googlemail.com> wrote:
> On Wed, Feb 14, 2018 at 8:30 AM, Sameera Deshpande
> <sameera.deshpa...@linaro.org> wrote:
>> Hi!
>>
>> Please find attached the patch to fix bug in branches with offsets ove
On 14 February 2018 at 14:00, Sameera Deshpande
<sameera.deshpa...@linaro.org> wrote:
> Hi!
>
> Please find attached the patch to fix bug in branches with offsets over 1MiB.
> There has been an attempt to fix this issue in commit
> 050af05b9761f1979f11c151519e724
, eliminated the
attribute completely, and computed the offset from insn_addresses
instead.
Ok for trunk?
gcc/Changelog
2018-02-13 Sameera Deshpande <sameera.deshpa...@linaro.org>
* config/aarch64/aarch64.md (far_branch): Remove attribute. Eliminate
all the depend
On 30 January 2018 at 09:28, Sameera Deshpande
<sameera.deshpa...@linaro.org> wrote:
> On 30-Jan-2018 2:37 AM, "Richard Sandiford" <richard.sandif...@linaro.org>
> wrote:
>
> Sameera Deshpande <sameera.deshpa...@linaro.org> writes:
>> Hi!
>>
On 30-Jan-2018 2:37 AM, "Richard Sandiford" <richard.sandif...@linaro.org>
wrote:
Sameera Deshpande <sameera.deshpa...@linaro.org> writes:
> Hi!
>
> I am seeing multiple assembler errors with error message "Error:
> conditional branch out of range" for
Hi!
I am seeing multiple assembler errors with error message "Error:
conditional branch out of range" for customer code.
The root cause of the bug is that conditional branches are generated
whose branch target ends up being too far away to be encoded in the
instruction. It appears that there
Hi!
Please find attached the patch implementing vld1_*_x3, vst1_*_x2 and
vst1_*_x3 intrinsics as defined by Neon document.
Ok for trunk?
- Thanks and regards,
Sameera D.
gcc/Changelog:
2017-11-14 Sameera Deshpande <sameera.deshpa...@linaro.org>
* config/aarch64/aarch6
char;
#endif
+struct vec_perm_order_spec;
+
/* Most host source files will require the following headers. */
#if !defined (GENERATOR_FILE) && !defined (USED_FOR_TARGET)
#include "machmode.h"
Index: gcc/genvect-inst-tiles.c
===
Hi Matthew,
Please find attached updated patch as per our offline discussion.
I have disabled return in registers for all vector float types, and updated the
test case accordingly.
Ok for trunk?
- Thanks and regards,
Sameera D.
From: Sameera
Hi Matthew,
Please find attached the patch to fix the calling convention issue,
where argument and result passing convention differed for MSA and
non-MSA variants.
The implementation of TARGET_RETURN_IN_MEMORY is altered to block V4SF to be
returned in registers.
Ok for trunk?
- Thanks and
tree *tmp;
+ tmp = k_arity_promotion_reduction (PT_CHILD (retval, i), to_arity);
+ if (tmp == NULL)
+ return NULL;
+
+ PT_CHILD (retval, i) = tmp;
+ }
+
+ PT_ARITY (retval) = i;
+}
+
+ return retval;
+
+
+}
+
+#endif
Index: gcc/tree-vect-unified.c
=
Hi!
I have created new branch unified-autovect based on ToT.
Please find attached the patch adding information about new branch
"unified-autovect" in the documentation.
Is it ok to commit?
- Thanks and regards,
Sameera D.
unified-autovec-doc.patch
Description: unified-autovec-doc.patch
Hi Richard,
Thanks for the review.
Please find attached updated patch after your review comments.
Changelog:
gcc/
* config/mips/mips.md (JOIN_MODE): New mode iterator.
(join2_load_StoreJOIN_MODE:mode): New pattern.
(join2_loadhi): Likewise.
(define_peehole2): Add
Hi Richard,
Thanks for your comments. I am working on the review comments, and will share
the reworked patch soon.
However, here is clarification on some of the issues raised.
+ if (TARGET_FIX_24K TUNE_P5600)
+error (unsupported combination: %s, -mtune=p5600 -mfix-24k);
+
/*
Hi Richard,
Please find attached the patch implementing load-load/store-store bonding
supported by P5600.
In P5600, 2 consecutive loads/stores of same type which access contiguous
memory locations are bonded together by instruction issue unit to dispatch
single load/store instruction which
Hi,
Please find attached the patch fixing bug 49069.
This patch is tested with check-gcc on trunk and 4.6 without regression.
OK for trunk?
Is it fine to backport to 4.6 branch?
ChangeLog:
2012-01-24 Sameera Deshpande sameera.deshpa...@arm.com
PR target/49069
gcc/config/arm
Hi!
Please find attached revised LDRD generation patch for A15 Thumb-2 mode.
Because of the major rework in ARM and Thumb-2 RTL epilogue patches,
this patch has undergone some changes.
The patch is tested with check-gcc, bootstrap and check-gdb without
regression.
Ok for trunk?
-- diff --git
Hi Ramana,
Please find attached revised LDRD generation patch for A15 ARM mode.
Because of the major rework in ARM RTL epilogue patch, this patch has
undergone some changes.
The patch is tested with check-gcc, bootstrap and check-gdb without
regression.
Ok for trunk?
-- diff --git
On Tue, 2011-11-22 at 10:37 +, Ramana Radhakrishnan wrote:
Xinyu: I seem to have mis-remembered that one of your patches was
turning on Thumb2 for wMMX.
Ramana, in that case, should I add the change you suggested in ARM RTL
epilogue patch only?
The comment in Thumb2 epilogues
...@google.com
+Sameera Deshpandesameera.deshpa...@arm.com
Fran�ois Dumont fdum...@gcc.gnu.org
Benoit Dupont de Dinechin benoit.dupont-de-dinec...@st.com
Michael Eager ea...@eagercon.com
On Fri, 2011-11-18 at 23:12 +, Ramana Radhakrishnan wrote:
On 17 November 2011 15:16, Sameera Deshpande sameera.deshpa...@arm.com
wrote:
Hi!
Please find attached the patch updating NEG_POOL_RANGE from 1008 to
1020 -(8 + data size).
This is OK - can you add a comment around
, this patch guards dereferences
of 'fn' in dump_gimple_call ().
Tests in gcc-dg/vect failing with 'segmentation fault', pass with this
patch.
gcc/Changelog entry:
2011-11-24 Sameera Deshpande sameera.deshpa...@arm.com
* gimple-pretty-print.c (dump_gimple_call): Check if fn is NULL
before
On Fri, 2011-11-18 at 21:45 +, Ramana Radhakrishnan wrote:
On 5 October 2011 17:04, Sameera Deshpande sameera.deshpa...@arm.com wrote:
Ping!
http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01855.html
This should now be rebased given your other changes to the Thumb2
epilogues patch
On Tue, 2011-11-22 at 01:55 +, Xinyu Qi wrote:
At 2011-11-19 07:11:17,Ramana Radhakrishnan
ramana.radhakrish...@linaro.org wrote:
On 10 November 2011 18:07, Sameera Deshpande
sameera.deshpa...@arm.com wrote:
Please find attached the reworked patch.
OK but for a very small bit
with this fix.
gcc/ChangeLog entry:
2011-11-17 Sameera Deshpande sameera.deshpa...@arm.com
* config/arm/arm.md (arm_movdi): Update NEG_POOL_RANGE.
(movdf_soft_insn): Likewise.
* config/arm/fpa.md (thumb2_movdf_fpa): Likewise.
* config/arm/neon.md (neon_movmode): Likewise
Hi Richard,
thanks for your comments.
--
+ if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, offset_adj))) == PLUS)
It's generally best not to use assignments within conditionals unless
there is a strong reason otherwise (that normally implies something like
being deep within a condition
On Thu, 2011-11-10 at 13:44 +, Richard Earnshaw wrote:
On 28/09/11 17:15, Sameera Deshpande wrote:
Hi!
This patch generates Thumb2 epilogues in RTL form.
The work involves defining new functions, predicates and patterns along with
few changes in existing code
On Fri, 2011-10-21 at 13:45 +0100, Ramana Radhakrishnan wrote:
+arm_emit_strd_push (unsigned long saved_regs_mask)
How different is this from the thumb2 version you sent out in Patch 03/05 ?
Thumb-2 STRD can handle non-consecutive registers, ARM STRD cannot.
Because of which we accumulate
On Fri, 2011-10-21 at 13:45 +0100, Ramana Radhakrishnan wrote:
change that. Other than that this patch looks OK and please watch out
for stylistic issues from the previous patch.
Ramana, please find attached reworked patch. The patch is tested with
check-gcc, check-gdb and bootstrap with no
the table here ?
The array REGISTER_NAMES in aout.h use S0, S2, ... names for double
registers. Is there any way to use OVERLAPPING_REGISTER_NAMES? If that
can be done, I can eliminate the table here.
Updated ChangeLog entry:
2011-09-28 Ian Bolton ian.bol...@arm.com
Sameera
I don't believe REG_FRAME_RELATED_EXPR does the right thing for
anything besides prologues. You need to emit REG_CFA_RESTORE
for the pop inside an epilogue.
Richard, here is updated patch that uses REG_CFA_RESTORE instead of
REG_FRAME_RELATED_EXPR.
The patch is tested with check-gcc,
Hi Ramana,
Please find attached reworked patch. The patch is tested with check-gcc,
check-gdb and bootstrap with no regression.
Ok?
- Thanks and regards,
Sameera D.diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 05c9368..334a25f 100644
--- a/gcc/config/arm/arm.c
+++
On Mon, 2011-11-07 at 09:56 +, Paul Brook wrote:
The array REGISTER_NAMES in aout.h use S0, S2, ... names for double
registers. Is there any way to use OVERLAPPING_REGISTER_NAMES? If that
can be done, I can eliminate the table here.
You should be using %P.
Paul,
Thanks for your
This series of 5 patches generate LDRD/STRD instead of POP/PUSH in
epilogue/prologue for ARM and Thumb-2 mode of A15.
Patch [1/5] introduces new field in tune which can be used to indicate
whether LDRD/STRD are preferred over POP/PUSH by the specific core.
Patches [2-5/5] use this field to
for cortex-a15:
2011-10-11 Sameera Deshpande
sameera.deshpa...@arm.com
* config/arm/arm-cores.def (cortex_a15): Update.
* config/arm/arm-protos.h (struct tune_params): Add new field...
(arm_gen_ldrd_strd
for thumb2 epilogue in A15:
2011-10-11 Sameera Deshpande
sameera.deshpa...@arm.com
* config/arm/arm-protos.h (bad_reg_pair_for_thumb_ldrd_strd
are PUSHed.
The patch is tested with check-gcc, check-gdb and bootstrap with no
regression.
Changelog entry for Patch to emit STRD for ARM prologue in A15:
2011-10-11 Sameera Deshpande
sameera.deshpa...@arm.com
to emit LDRD for ARM epilogue in A15:
2011-10-11 Sameera Deshpande
sameera.deshpa...@arm.com
* config/arm/arm.c (arm_emit_ldrd_pop): New static function
Ping!
http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01854.html
On Wed, 2011-09-28 at 17:15 +0100, Sameera Deshpande wrote:
Hi!
This patch generates Thumb2 epilogues in RTL form.
The work involves defining new functions, predicates and patterns along with
few changes in existing code
Ping!
http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01855.html
On Wed, 2011-09-28 at 17:15 +0100, Sameera Deshpande wrote:
Hi!
This patch generates ARM epilogue in RTL form.
The work defines new functions and reuses most of the static functions and
patterns defined in the previous patch
The patch is tested with arm-eabi with no regressions.
ChangeLog:
2011-09-28 Ian Bolton ian.bol...@arm.com
Sameera Deshpande sameera.deshpa...@arm.com
* config/arm/arm-protos.h (load_multiple_operation_p): New
declaration.
(thumb2_expand_epilogue
65 matches
Mail list logo
