Re: [Question on aarch64] Questions on TLB range instructions on aarch64

Hi Kyrill, On 2019/9/17 19:24, Kyrill Tkachov wrote: > Hi Shaokun, > > On 9/17/19 12:17 PM, Shaokun Zhang wrote: >> Hi aarch64 maintainers, >> >> Sorry to noise you again. >> > No problem :) However, this isn't strictly-speaking a gcc issue because... >

[Question on aarch64] Questions on TLB range instructions on aarch64

Hi aarch64 maintainers, Sorry to noise you again. We(HiSilicon) next generation CPU core will support "ARMv8.4-TLBI, TLB maintenance and TLB range instructions" feature, so I try to compile it that tlbi rvae1is is replaced in linux kernel which is in my local branch, there are some error

Re: [PATCH v2] [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

Hi Kyrill, On 2019/9/5 17:41, Kyrill Tkachov wrote: > Hi Shaokun, > > On 9/5/19 10:37 AM, Shaokun Zhang wrote: >> Hi Kyrill, >> >> On 2019/9/3 19:13, Kyrill Tkachov wrote: >>> Hi Shaokun, >>> >>> On 9/3/19 9:35 AM, Shaokun Zhang wrote: &g

Re: [PATCH v2] [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

Hi Kyrill, On 2019/9/3 19:13, Kyrill Tkachov wrote: > Hi Shaokun, > > On 9/3/19 9:35 AM, Shaokun Zhang wrote: >> The DCache clean & ICache invalidation requirements for instructions >> to be data coherence are discoverable through new fields in CTR_EL0. >

[PATCH v2] [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

9-03 Shaokun Zhang * config/aarch64/sync-cache.c: Support CTR_EL0.IDC and CTR_EL0.DIC in __aarch64_sync_cache_range function. --- libgcc/config/aarch64/sync-cache.c | 57 -- 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/libgcc/config/aarch64/

Re: [PATCH] [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

Hi Kyrill, On 2019/9/2 22:31, Kyrill Tkachov wrote: > Hi Shaokun > > On 8/31/19 8:12 AM, Shaokun Zhang wrote: >> The DCache clean & ICache invalidation requirements for instructions >> to be data coherence are discoverable through new fields in CTR_EL0. >

Re: [PATCH] [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

Hi Kyrill, On 2019/9/2 22:24, Kyrill Tkachov wrote: > Hi Shaokun, > > On 8/31/19 8:12 AM, Shaokun Zhang wrote: >> The DCache clean & ICache invalidation requirements for instructions >> to be data coherence are discoverable through new fields in CTR_EL0. >

[PATCH] [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

8-31 Shaokun Zhang * config/aarch64/sync-cache.c: Support CTR_EL0.IDC and CTR_EL0.DIC in __aarch64_sync_cache_range function. --- libgcc/config/aarch64/sync-cache.c | 56 -- 1 file changed, 35 insertions(+), 21 deletions(-) diff --git a/libgcc/config/aarch64/

Re: [RFC] [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

Hi Kyrill, On 2019/8/28 16:57, Kyrill Tkachov wrote: > Hi Shaokun, > > On 8/28/19 9:47 AM, Shaokun Zhang wrote: >> Hi Kyrill, >> >> On 2019/8/27 18:16, Kyrill Tkachov wrote: >>> Hi Shaokun, >>> >>> On 8/22/19 3:10 PM, Shaokun Zhang wrote: &g

Re: [RFC] [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

Hi Kyrill, On 2019/8/27 18:16, Kyrill Tkachov wrote: > Hi Shaokun, > > On 8/22/19 3:10 PM, Shaokun Zhang wrote: >> The DCache clean & ICache invalidation requirements for instructions >> to be data coherence are discoverable through new fields in CTR_EL0. >

[RFC] [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

The DCache clean & ICache invalidation requirements for instructions to be data coherence are discoverable through new fields in CTR_EL0. Let's support the two bits if they are enabled, then we can get some performance benefit from this feature. 2019-08-22 Shaokun Zhang * config/aar

[RFC] Some questions on aarch64 feature about IDC and DIC

Hi aarch64 maintainers, Question 1: In __aarch64_sync_cache_range function, if CTR_EL0.IDC = 0b1, Shall the dc cvau and the dsb ish will be removed or only dc cvau will be removed? - for (; address < (const char *) end; address += dcache_lsize) -asm volatile ("dc\tcvau, %0" -

[PATCH] [aarch64] Revert support for ARMv8.2 in tsv110

insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e9f5baa6557c..842876b0ae90 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-12-19 Shaokun Zhang + +* config/aarch64/aarch64-cores.def (tsv110) : Revert support for ARMv8.2 + in tsv110

[PATCH v4] [aarch64] Add HiSilicon tsv110 CPU support

69e2e14..a040daa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2018-09-19 Shaokun Zhang +Bo Zhou + + * config/aarch64/aarch64-cores.def (tsv110): New CPU. + * config/aarch64/aarch64-tune.md: Regenerated. + * doc/invoke.texi (AArch64 Options/-mtune

[PATCH v3] [aarch64] Add HiSilicon tsv110 CPU support

d9fbc0c..f5538f7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2018-06-21 Shaokun Zhang +Bo Zhou + * config/aarch64/aarch64-cores.def (tsv110): New CPU. + * config/aarch64/aarch64-tune.md: Regenerated. + * doc/invoke.texi (AArch64 Options/-mtune): Add "t

[PATCH v2] [aarch64] Add HiSilicon tsv110 CPU support

@@ -1,3 +1,11 @@ +2018-06-12 Shaokun Zhang +Bo Zhou + * config/aarch64/aarch64-cores.def (tsv110): New CPU. + * config/aarch64/aarch64-tune.md: Regenerated. + * doc/invoke.texi (AArch64 Options/-mtune): Add "tsv110". + * config/aarch64/aarch64.c (tsv1

[RFC] [aarch64] Add HiSilicon tsv110 CPU support.

-05-22 Shaokun Zhang <zhangshao...@hisilicon.com> +Bo Zhou <zbo.z...@hisilicon.com> + + * config/aarch64/aarch64-cores.def (tsv110): New CPU. + * config/aarch64/aarch64-tune.md: Regenerated. + * doc/invoke.texi (AArch61 Options/-mtune): Add "tsv11

[RFC] [aarch64] Add HiSilicon tsv110 CPU support

tsv110 is designed by HiSilicon and supports v8_4A, it also optimizes L1 Icache which can access L1 Dcache. Therefore, DC CVAU is not necessary in __aarch64_sync_cache_range for tsv110, is there any good idea to skip DC CVAU operation for tsv110. Any thoughts and ideas are welcome. Shaokun Zhang