Fortify buffer overflow message reported.
(see https://github.com/earlephilhower/esp-quick-toolchain/issues/36)
gcc/ChangeLog:
* config/xtensa/xtensa.md (bswapsi2_internal):
Enlarge the buffer that is obviously smaller than the template
string given to sprintf().
---
No functional changes.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_emit_move_sequence):
Use can_create_pseudo_p(), instead of using individual
reload_in_progress and reload_completed.
(xtensa_expand_block_set_small_loop): Use xtensa_simm8x256(),
the
These instructions will all be converted to L32R ones with litpool entries
by the assembler.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_is_insn_L32R_p):
Consider relaxed MOVI instructions as L32R.
---
gcc/config/xtensa/xtensa.cc | 22 ++
1 file changed,
erratum:
- extern unsigned int value;
+ extern unsigned short value;
On 2022/06/17 22:47, Takayuki 'January June' Suwa via Gcc-patches wrote:
> Storing integer constants into litpool in the early stage of compilation
> hinders some integer optimizations. In fact, such i
Storing integer constants into litpool in the early stage of compilation
hinders some integer optimizations. In fact, such integer constants are
not subject to the constant folding process.
For example:
extern unsigned int value;
extern void foo(void);
void test(void) {
if
On 2022/06/15 5:17, Max Filippov wrote:
> Hi Suwa-san,
hi!
> This change results in a bunch of new regression test failures:
> The code generated for e.g. gcc.c-torture/execute/921208-2.c looks like this:
oh, PICed...
indirect (incl. via function pointer, virtual functions and of course PIC ones
RTL expansion of substitution to [DS]Cmode hard register includes obstructive
register clobber.
A simplest example:
double _Complex test(double _Complex c) {
return c;
}
will be converted to:
(set (reg:DF 42 [ c ]) (reg:DF 2 a2))
(set (reg:DF 43 [ c+8 ]) (reg:DF 4 a4))
When spilled DFmode registers are reloaded in, once loaded into a pair of
SImode regs and then copied from that regs. Such unwanted reg-reg moves
seems not to be eliminated at the "cprop_hardreg" stage, despite no problem
in output reloads.
Luckily it is easy to resolve such inefficiencies, with
This patch introduces support for sibling call optimization, when call0
ABI is in effect.
gcc/ChangeLog:
* config/xtensa/xtensa-protos.h (xtensa_prepare_expand_call,
xtensa_emit_sibcall): New prototypes.
(xtensa_expand_epilogue): Add new argument that specifies whether
This patch offers better RTL representations against straightforward
derivations from some tree optimizers' canonicalized forms.
- rounding up to even, such as '(x + (x & 1))', is canonicalized to
'((x + 1) & -2)', but the former is one instruction less than the latter
in Xtensa ISA.
- signed
gcc/ChangeLog:
* doc/invoke.texi: Document -mextra-l32r-costs= option.
---
gcc/doc/invoke.texi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b6c0305f198..2a3c638de40 100644
--- a/gcc/doc/invoke.texi
+++
Changes from v1:
(*shift_per_byte_omit_AND_1): changed to be split as early as possible
===
This patch introduces funnel shifter utilization, and rearranges existing
"per-byte shift" insn patterns.
gcc/ChangeLog:
* config/xtensa/predicates.md (logical_shift_operator,
On 2022/06/13 12:49, Max Filippov wrote:
> Hi Suwa-san,
hi!
> This change produces a bunch of regression test failures in big-endian
> configuration:
bad news X(
that point is what i was a little worried about...
> E.g. for the test gcc.c-torture/execute/struct-ini-2.c
> the following assembly
On 2022/06/12 16:51, Max Filippov wrote:
This patch is whitespace-damaged. Please resend.
oh, sorry.
reposted as zip in attachment due to avoiding damage.<>
This patch offers several insn-and-split patterns for bitwise AND with
register and constant that cannot fit into a "MOVI Ax, simm12" instruction,
but can be represented as:
i. 1's least significant N bits and the others 0's (17 <= N <= 31)
ii. 1's most significant N bits and the others 0's
In Xtensa ISA, there is no single machine instruction that calculates unary
bitwise negation, but a few similar fused instructions are exist:
"BALL Ax, Ay, label" // if ((~Ax & Ay) == 0) goto label;
"BNALL Ax, Ay, label" // if ((~Ax & Ay) != 0) goto label;
These instructions have never
No need to describe the "false side" conditional insn patterns anymore.
gcc/ChangeLog:
* config/xtensa/xtensa-protos.h (xtensa_emit_branch):
Remove the first argument.
(xtensa_emit_bit_branch): Remove it because now called only from the
output statement of
This patch introduces funnel shifter utilization, and rearranges existing
"per-byte shift" insn patterns.
gcc/ChangeLog:
* config/xtensa/predicates.md (logical_shift_operator,
xtensa_shift_per_byte_operator): New predicates.
* config/xtensa/xtensa-protos.h
thanks for your report.
On 2022/06/11 18:05, Max Filippov wrote:
It prints
(symbol_ref/f:SI ("*.LC1") [flags 0x2] )
ah, i understand it... that is Pmode (synonym of SImode) of a memory
address that points to 'u.f'.
thus, the correct handling is to fail the split pattern.
---
On 2022/06/11 16:58, Max Filippov wrote:
Hi Suwa-san,
hi!
this change results in a bunch of ICEs in the tests like this:
during RTL pass: split2
gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c: In function 'f':
gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c:13:1: internal
compiler
On 2022/06/11 9:12, Max Filippov wrote:
Hi Suwa-san,
hi!
This change results in a bunch of ICEs in tests that look like this:
gcc/gcc/testsuite/gcc.c-torture/compile/memtst.c: In function 'main':
gcc/gcc/testsuite/gcc.c-torture/compile/memtst.c:28:1: error:
unrecognizable insn:
(insn 7 6 8 2
This patch revises the previous implementation of constant synthesis.
First, changed to use define_split machine description pattern and to run
after reload pass, in order not to interfere some optimizations such as
the loop invariant motion.
Second, not only integer but floating-point is
This patch revises the previous implementation of constant synthesis.
First, changed to use define_split machine description pattern and to run
after reload pass, in order not to interfere some optimizations such as
the loop invariant motion.
Second, not only integer but floating-point is
Now apply to almost any size of aligned block under such circumstances.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_expand_block_set_small_loop):
Pass through the block length / loop count conditions if
zero-overhead looping is configured and active,
---
This patch implements a new target-specific relative RTL insn cost function
because of suboptimal cost estimation by default, and fixes several "length"
insn attributes (related to the cost estimation).
And also introduces a new machine-dependent option "-mextra-l32r-costs="
that tells
umulsidi3 is faster than umuldi3 even if library call, and is also
prerequisite for fast constant division by multiplication.
gcc/ChangeLog:
* config/xtensa/xtensa.md (mulsidi3, umulsidi3):
Split into individual signedness, in order to use libcall
"__umulsidi3" but not
Hi all,
In some targets, initialization code for char array may be split into two
parts even if the initialization consists of all zeros:
/* example */
extern void foo(char*);
void test(void) {
char a[256] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 };
foo(a);
}
;; Xtensa (xtensa-lx106)
.LC0:
> (clrsb:m x)
> Represents the number of redundant leading sign bits in x, represented
> as an integer of mode m, starting at the most significant bit position.
This explanation is just what the NSA instruction (not ever emitted before)
calculates in Xtensa ISA.
gcc/ChangeLog:
*
In Xtensa ISA, there is no single machine instruction that calculates unary
bitwise negation. But a few optimizers assume that bitwise negation can be
done by a single insn.
As a result, '((x < 0) ? ~x : x)' cannot be optimized to '(x ^ (x >> 31))'
ever before, for example.
This patch relaxes
In Xtensa ISA, there is no single machine instruction that calculates unary
bitwise negation.
gcc/ChangeLog:
* config/xtensa/xtensa.md (*andsi3_bitcmpl):
New insn_and_split pattern.
gcc/testsuite/ChangeLog:
* gcc.target/xtensa/check_zero_byte.c: New.
---
This patch adds bswaphi2 insn pattern that is one instruction less than the
default expansion.
gcc/ChangeLog:
* config/xtensa/xtensa.md (bswaphi2): New insn pattern.
---
gcc/config/xtensa/xtensa.md | 10 ++
1 file changed, 10 insertions(+)
diff --git
On 2022/05/27 12:00, Takayuki 'January June' Suwa via Gcc-patches wrote:
On 2022/05/27 1:57, Max Filippov wrote:
is that something that can be addressed in this patch?
seems hard to resolve, because the RTL-generation pass passes only 68
bytes in that case:
the culprit is here, but i don't
On 2022/05/27 1:57, Max Filippov wrote:
is that something that can be addressed in this patch?
seems hard to resolve, because the RTL-generation pass passes only 68
bytes in that case:
void f(char *p);
void g(void)
{
char c[72] = {0};
f(c);
}
without this patch, we would
This patch introduces setmemsi insn pattern of two kinds, unrolled loop and
small loop, for fixed small length and constant initialization value.
gcc/ChangeLog:
* gcc/config/xtensa/xtensa-protos.h
(xtensa_expand_block_set_unrolled_loop,
This patch introduces setmemsi insn pattern of two kinds, unrolled loop and
small loop, for fixed small length and constant initialization value.
gcc/ChangeLog:
* gcc/config/xtensa/xtensa-protos.h
(xtensa_expand_block_set_unrolled_loop,
This patch makes bswap[sd]i2 better register allocation, and reconstructs
bswapsi2 in order to take advantage of GIMPLE manual byte-swapping
recognition.
gcc/ChangeLog:
* gcc/config/xtensa/xtensa.md (bswapsi2): New expansion pattern.
(bswapsi2_internal): Revise the template and
This patch introduces setmemsi insn pattern of two kinds, unrolled loop and
small loop, for fixed small length and constant initialization value.
gcc/ChangeLog:
* gcc/config/xtensa/xtensa-protos.h
(xtensa_expand_block_set_unrolled_loop,
This patch makes counting the number of instructions of the remainder
(modulo 4) part more accurate.
gcc/ChangeLog:
* gcc/config/xtensa/xtensa.cc (xtensa_expand_block_move):
Make instruction counting more accurate, and simplify emitting insns.
---
gcc/config/xtensa/xtensa.cc |
No functional changes.
gcc/ChangeLog:
* gcc/config/xtensa/constraints.md (M, O): Use the macro.
* gcc/config/xtensa/predicates.md (addsubx_operand, extui_fldsz_operand,
sext_fldsz_operand): Ditto.
* gcc/config/xtensa/xtensa.cc (xtensa_simm8, xtensa_simm8x256,
No functional changes.
gcc/ChangeLog:
* gcc/config/xtensa/predicates.md (extui_fldsz_operand): Simplify.
* gcc/config/xtensa/xtensa.cc (xtensa_mask_immediate, print_operand):
Ditto.
---
gcc/config/xtensa/predicates.md | 2 +-
gcc/config/xtensa/xtensa.cc | 24
These patterns were deprecated since GCC 4.8.
gcc/ChangeLog:
* config/xtensa/xtensa.md (extvsi, extvsi_internal, extzvsi,
extzvsi_internal): Rename from extv, extv_internal, extzv and
extzv_internal, respectively.
---
gcc/config/xtensa/xtensa.md | 16
1
On Espressif's ESP8266 (based on Tensilica LX106, no hardware divider),
this patch reduces the size of each:
__moddi3() @ libgcc.a : 969 -> 301 (saves 668)
__divmoddi4() : -> 426 (saves 685)
__udivmoddi4(): 1043 -> 319 (saves 724)
in bytes, respectively.
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