, 2023 at 8:30 AM Tejas Belagod wrote:
From: Richard Biener
Date: Monday, June 26, 2023 at 2:23 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [RFC] GNU Vector Extension -- Packed Boolean Vectors
On Mon, Jun 26, 2023 at 8:24 AM Tejas Belagod via Gcc-patches
wrote:
Hi,
Packed
PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [RFC] GNU Vector Extension -- Packed Boolean Vectors
On Mon, Jun 26, 2023 at 8:24 AM Tejas Belagod via Gcc-patches
wrote:
Hi,
Packed Boolean Vectors
--
I'd like to propose a feature addition to GNU V
Boolean Vectors
On Mon, Jun 26, 2023 at 8:24 AM Tejas Belagod via Gcc-patches
wrote:
Hi,
Packed Boolean Vectors
--
I'd like to propose a feature addition to GNU Vector extensions to add packed
boolean vectors (PBV). This has been discussed in the past here[1]
, 2023 at 8:30 AM Tejas Belagod wrote:
From: Richard Biener
Date: Monday, June 26, 2023 at 2:23 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [RFC] GNU Vector Extension -- Packed Boolean Vectors
On Mon, Jun 26, 2023 at 8:24 AM Tejas Belagod via Gcc-patches
wrote:
Hi
Monday, June 26, 2023 at 2:23 PM
> To: Tejas Belagod
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [RFC] GNU Vector Extension -- Packed Boolean Vectors
>
> On Mon, Jun 26, 2023 at 8:24 AM Tejas Belagod via Gcc-patches
> wrote:
> >
> > Hi,
> >
> > Packed
From: Richard Biener
Date: Monday, June 26, 2023 at 2:23 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [RFC] GNU Vector Extension -- Packed Boolean Vectors
On Mon, Jun 26, 2023 at 8:24 AM Tejas Belagod via Gcc-patches
wrote:
>
> Hi,
>
> Packed Boo
Hi,
Packed Boolean Vectors
--
I'd like to propose a feature addition to GNU Vector extensions to add packed
boolean vectors (PBV). This has been discussed in the past here[1] and a
variant has
been implemented in Clang recently[2].
With predication features being added to v
ov=arm@gcc.gnu.org> On Behalf Of Prathamesh
> Kulkarni via Gcc-patches
> Sent: Wednesday, June 14, 2023 8:13 AM
> To: Tejas Belagod
> Cc: Richard Sandiford ; gcc-
> patc...@gcc.gnu.org
> Subject: Re: [PATCH v2] [PR96339] Optimise svlast[ab]
>
> On Tue, 13 Jun 2023 at 12:
From: Richard Sandiford
Date: Monday, June 12, 2023 at 2:15 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org , Tejas Belagod
Subject: Re: [PATCH v2] [PR96339] Optimise svlast[ab]
Tejas Belagod writes:
> From: Tejas Belagod
>
> This PR optimizes an SVE intrinsics sequence where
> svla
From: Richard Sandiford
Date: Friday, May 19, 2023 at 3:20 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
Tejas Belagod writes:
> Am I correct to understand that we still need to check for the case when
> there's a repeating non-ze
From: Tejas Belagod
This PR optimizes an SVE intrinsics sequence where
svlasta (svptrue_pat_b8 (SV_VL1), x)
a scalar is selected based on a constant predicate and a variable vector.
This sequence is optimized to return the correspoding element of a NEON
vector. For eg.
svlasta (sv
From: Richard Sandiford
Date: Tuesday, May 16, 2023 at 5:36 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
Tejas Belagod writes:
>>> + {
>>> + b = build3 (BIT_FIELD_REF, TREE_TYPE (f.lhs), val,
>>> +
From: Richard Sandiford
Date: Tuesday, May 16, 2023 at 2:15 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
Tejas Belagod writes:
>> + {
>> +int i;
>> +int nelts = vector_cst_encoded_nelts (v);
>> +int first_el = 0;
>>
Thanks for your comments, Richard.
From: Richard Sandiford
Date: Friday, May 12, 2023 at 1:02 AM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org , Tejas Belagod
Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
Tejas Belagod writes:
> From: Tejas Belagod
>
> This PR optimizes an SV
[Ping]
From: Tejas Belagod
Date: Thursday, March 16, 2023 at 5:09 PM
To: gcc-patches@gcc.gnu.org
Cc: Tejas Belagod , Richard Sandiford
Subject: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
From: Tejas Belagod
This PR optimizes an SVE intrinsics sequence where
svlasta (svptrue_pat_b8
From: Tejas Belagod
This PR optimizes an SVE intrinsics sequence where
svlasta (svptrue_pat_b8 (SV_VL1), x)
a scalar is selected based on a constant predicate and a variable vector.
This sequence is optimized to return the correspoding element of a NEON
vector. For eg.
svlasta (sv
The 64-bit variant of PMULL{2} and AES instructions are available if FEAT_AES
is implemented according to the Arm ARM [1]. Similarly FEAT_SHA1 and
FEAT_SHA256 enable the use of SHA1 and SHA256 instruction variants.
This patch fixes arm_neon.h to correctly reflect the feature availability based
on
Transitive closures of architectural extensions have to be manually maintained
for AARCH64_OPT_EXTENSION list. Currently aes, sha2 and sha3 extensions add
AARCH64_FL_SIMD has their dependency - this does not automatically pull in the
transitive dependence of AARCH64_FL_FP from AARCH64_FL_SIMD's de
; From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Tejas Belagod
> via Gcc-patches
> Sent: Monday, January 16, 2023 7:12 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Tejas Belagod ; Richard Sandiford
> ; Richard Earnshaw
>
> Subject: [PATCH] AArch64:
The 64-bit variant of PMULL{2} and AES instructions are available if FEAT_AES
is implemented according to the Arm ARM [1]. Similarly FEAT_SHA1 and
FEAT_SHA256 enable the use of SHA1 and SHA256 instruction variants.
This patch fixes arm_neon.h to correctly reflect the feature availability based
on
Ping for this series.
Thanks,
Tejas.
> -Original Message-
> From: Gcc-patches bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
> Gcc-patches
> Sent: Thursday, October 28, 2021 12:41 PM
> To: Richard Earnshaw ; gcc-
> patc...@gcc.gnu.org
>
Hi,
This patch is part of the series of PACBTI-M patches posted earlier
https://gcc.gnu.org/pipermail/gcc-patches/2021-October/582773.html
This change adds the target function attribute 'branch-protection'. The
options that it can take are the same the command-line option
'mbranch-protection'.
> -Original Message-
> From: Gcc-patches bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
> Gcc-patches
> Sent: Friday, October 8, 2021 1:19 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [Patch 7/7, Arm, GCC] Introduce multilibs for PACBTI ta
> -Original Message-
> From: Gcc-patches bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
> Gcc-patches
> Sent: Friday, October 8, 2021 1:19 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [Patch 6/7, Arm, GCC] Emit build attributes for PA
> -Original Message-
> From: Gcc-patches bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
> Gcc-patches
> Sent: Friday, October 8, 2021 1:18 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [Patch 5/7, Arm. GCC] Add pointer authentication for stack
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, October 11, 2021 2:58 PM
> To: Tejas Belagod ; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch 4/7, Arm. GCC] Implement target feature macros for
> PACBTI.
>
> On 08/10/2021 13:18, Tejas Belagod via G
aw via Gcc-patches wrote:
> > On 08/10/2021 13:17, Tejas Belagod via Gcc-patches wrote:
> >> Hi,
> >>
> >> Add targeting-checking entities for PACBTI in testsuite framework.
> >>
> >> Tested on arm-none-eabi. OK for trunk?
> >>
> >&
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, October 11, 2021 1:58 PM
> To: Tejas Belagod ; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.
>
> On 08/10/2021 13:17, Tejas Belagod via Gcc-patches wrote
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, October 11, 2021 1:29 PM
> To: Tejas Belagod ; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch 1/7, Arm, GCC] Add Armv8.1-M Mainline target feature
> +pacbti.
>
> On 08/10/2021 13:17, Tejas Belag
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, October 11, 2021 1:58 PM
> To: Tejas Belagod ; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.
>
> On 08/10/2021 13:17, Tejas Belagod via Gcc-patches wrote
Hi,
This patch adds a multilib for pacbti target feature.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/ChangeLog:
* config/arm/t-rmprofile: Add multilib rules for +pacbti.
diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile
index
a6036bf0a519
Hi,
This patch emits assembler directives for PACBTI build attributes
as defined by the ABI.
(https://github.com/ARM-software/abi-aa/releases/download/2021Q1/addenda32.pdf)
Tested on arm-none-eabi.
2021-10-04 Tejas Belagod
gcc/ChangeLog:
* config/arm/arm.c (arm_file_start): Emit EA
Hi,
This patch adds authentication for when the stack is unwound when
an exception is taken. All the changes here are done to the runtime
code in libgcc's unwinder code for Arm target. All the changes are
guarded under defined (__ARM_FEATURE_PAC_DEFAULT) and activates only
if the +pacbti feature
Hi,
This patch implements target feature macros when PACBTI is
enabled through the -march option or -mbranch-protection.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/ChangeLog:
* config/arm/arm-c.c (arm_cpu_builtins): Define
__ARM_FEATURE_BTI_DEFAULT a
Hi,
Add targeting-checking entities for PACBTI in testsuite
framework.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/ChangeLog:
* testsuite/lib/target-supports.exp
(check_effective_target_arm_pacbti_hw): New.
diff --git a/gcc/testsuite/lib/target-suppor
Hi,
Add -mbranch-protection option and its associated parsing routines.
This option enables the code-generation of pointer signing and
authentication instructions in function prologues and epilogues.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/ChangeLog:
* co
Hi,
This patch adds the -march feature +pacbti to Armv8.1-M Mainline.
This feature enables pointer signing and authentication instructions
on M-class architectures.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/Changelog:
* config/arm/arm-cpus.in: Define new fe
Hi,
Loops containing long long shifts fail to vectorize due to the vectorizer
not being able to recognize long long right shifts. This is due to a bug
in the iterator used for the vashr and vlshr patterns in aarch64-simd.md.
Tested and bootstrapped on aarch64-linux. OK?
2021-08-05 Tejas Belagod
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