On Thu, Jan 10, 2019 at 03:49:27PM +, James Greenhalgh wrote:
> On Mon, Dec 03, 2018 at 03:55:36AM -0600, Ramana Radhakrishnan wrote:
> > For quite sometime the kernel guys, (more specifically Ard) have been
> > talking about using a system register (sp_el0) and an offset from that
> > for a
On Wed, Oct 31, 2018 at 04:38:53PM +, Richard Henderson wrote:
> On 10/31/18 3:04 PM, Will Deacon wrote:
> > The example test above uses relaxed atomics in conjunction with an acquire
> > fence, so I don't think we can actually use ST at all without a change
> > to the l
DADD has no memory ordering requirements.
> >
> > I'm taking this to mean that even if the result is unused, using XZR is not
> > a valid transformation; it weakens the expected acquire semantics to
> > unordered.
> >
> > The example I have from
On Tue, Mar 11, 2014 at 09:12:53PM +, John Carr wrote:
Will Deacon will.dea...@arm.com wrote:
On Tue, Mar 11, 2014 at 02:54:18AM +, John Carr wrote:
A comment in arm/sync.md notes We should consider issuing a inner
shareability zone barrier here instead. Here is my first attempt
Hi John,
On Tue, Mar 11, 2014 at 02:54:18AM +, John Carr wrote:
A comment in arm/sync.md notes We should consider issuing a inner
shareability zone barrier here instead. Here is my first attempt
at a patch to emit weaker memory barriers. Three instructions seem
to be relevant for user
