[PATCH 3/4] rs6000: Enable vec_insert for P8 with rs6000_expand_vector_set_var_p8

gcc/ChangeLog: 2020-10-10 Xionghu Luo * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Generate ARRAY_REF(VIEW_CONVERT_EXPR) for P8 and later platforms. * config/rs6000/rs6000.c (rs6000_expand_vector_set_var): Update to call different

[PATCH 0/4] rs6000: Enable variable vec_insert with IFN VEC_SET

Originated from https://gcc.gnu.org/pipermail/gcc-patches/2020-September/554240.html with patch split and some refinement per review comments. Patch of IFN VEC_SET for ARRAY_REF(VIEW_CONVERT_EXPR) is committed, this patch set enables expanding IFN VEC_SET for Power9 and Power8 with specfic

[PATCH 1/4] rs6000: Change rs6000_expand_vector_set param

rs6000_expand_vector_set could accept insert either to constant position or variable position, so change the operand to reg_or_cint_operand. gcc/ChangeLog: 2020-10-10 Xionghu Luo * config/rs6000/rs6000-call.c (altivec_expand_vec_set_builtin): Change call param 2 from type int

[PATCH 4/4] rs6000: Update testcases' instruction count

gcc/testsuite/ChangeLog: 2020-10-10 Xionghu Luo * gcc.target/powerpc/fold-vec-insert-char-p8.c: Adjust instruction counts. * gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-double.c: Likewise. *

Re: [PATCH v4 1/3] IFN: Implement IFN_VEC_SET for ARRAY_REF with VIEW_CONVERT_EXPR

On 2020/9/25 21:28, Richard Sandiford wrote: > xionghu luo writes: >> @@ -2658,6 +2659,45 @@ expand_vect_cond_mask_optab_fn (internal_fn, gcall >> *stmt, convert_optab optab) >> >> #define expand_vec_cond_mask_optab_fn expand_vect_cond_mask_optab_fn >> >> +/* Expand VEC_SET internal

[PATCH v4 1/3] IFN: Implement IFN_VEC_SET for ARRAY_REF with VIEW_CONVERT_EXPR

Hi, On 2020/9/24 20:39, Richard Sandiford wrote: > xionghu luo writes: >> @@ -2658,6 +2659,43 @@ expand_vect_cond_mask_optab_fn (internal_fn, gcall >> *stmt, convert_optab optab) >> >> #define expand_vec_cond_mask_optab_fn expand_vect_cond_mask_optab_fn >> >> +/* Expand VEC_SET internal

Re: [PATCH v2 2/2] rs6000: Expand vec_insert in expander instead of gimple [PR79251]

Hi, On 2020/9/24 21:27, Richard Biener wrote: > On Thu, Sep 24, 2020 at 10:21 AM xionghu luo wrote: > > I'll just comment that > > xxperm 34,34,33 > xxinsertw 34,0,12 > xxperm 34,34,32 > > doesn't look like a variable-position insert instruction but > this is a

Re: [PATCH v2 2/2] rs6000: Expand vec_insert in expander instead of gimple [PR79251]

Hi Segher, The attached two patches are updated and split from "[PATCH v2 2/2] rs6000: Expand vec_insert in expander instead of gimple [PR79251]" as your comments. [PATCH v3 2/3] rs6000: Fix lvsl mode and change rs6000_expand_vector_set param This one is preparation work of fix lvsl arg

Re: [PATCH v3 1/2] IFN: Implement IFN_VEC_SET for ARRAY_REF with VIEW_CONVERT_EXPR

Hi, On 2020/9/23 19:33, Richard Biener wrote: >> The first loop is for rhs stmt process, this loop is for lhs stmt process. >> I thought vec_extract also need to generate IFN before, but seems not >> necessary now? And that the first loop needs to update the lhs stmt while >> then second

[PATCH v3 1/2] IFN: Implement IFN_VEC_SET for ARRAY_REF with VIEW_CONVERT_EXPR

Thanks for the review, On 2020/9/21 16:31, Richard Biener wrote: + +static gimple * +gimple_expand_vec_set_expr (gimple_stmt_iterator *gsi) +{ + enum tree_code code; + gcall *new_stmt = NULL; + gassign *ass_stmt = NULL; + + /* Only consider code == GIMPLE_ASSIGN. */ + gassign *stmt =

[PATCH] ipa-inline: Improve growth accumulation for recursive calls

From: Xiong Hu Luo For SPEC2017 exchange2, there is a large recursive functiondigits_2(function size 1300) generates specialized node from digits_2.1 to digits_2.8 with added build option: --param ipa-cp-eval-threshold=1 --param ipa-cp-unit-growth=80 ipa-inline pass will consider inline these

[PATCH] rs6000: Split movsf_from_si from high word before reload[PR89310]

For extracting high part element from DImode register like: {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} split it before reload with "and mask" to avoid generating shift right 32 bit then shift left 32 bit. srdi 3,3,32 sldi 9,3,32 mtvsrd 1,9 xscvspdpn 1,1 => rldicr 3,3,0,31 mtvsrd 1,3

[PATCH] rs6000: Use REAL_TYPE to copy when block move array in structure[PR65421]

Double array in structure as function arguments or return value is accessed by BLKmode, they are stored to stack and load from stack with redundant conversion from DF->DI->DF. This patch checks the homogeneous type and use the actual element type to do block move to by pass the conversions.

[PATCH] [stage1] ipa-cp: Fix PGO regression caused by r278808

resend the patch for stage1: https://gcc.gnu.org/pipermail/gcc-patches/2020-January/538186.html The performance of exchange2 built with PGO will decrease ~28% by r278808 due to profile count set incorrectly. The cloned nodes are updated to a very small count caused later pass cunroll fail to

[PATCH] Add value range info for affine combination to improve store motion (PR83403)

From: Xionghu Luo Get and propagate value range info to convert expressions with convert operation on PLUS_EXPR/MINUS_EXPR/MULT_EXPR when not overflow. i.e.: (long unsigned int)((unsigned int)n * 10 + 1) => (long unsigned int)((unsigned int) n * (long unsigned int)10 + (long unsigned int)1)

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