Richard Sandiford 于2024年5月29日周三 05:28写道：
>
> YunQiang Su writes:
> > If `find_a_program` cannot find `as/ld/objcopy` and we are a cross
> > toolchain,
> > the final fallback is `as/ld` of system. In fact, we can have a try with
> > -as/ld/objcopy before fa
YunQiang Su 于2024年5月22日周三 17:54写道：
>
> If `find_a_program` cannot find `as/ld/objcopy` and we are a cross toolchain,
> the final fallback is `as/ld` of system. In fact, we can have a try with
> -as/ld/objcopy before fallback to native as/ld/objcopy.
>
> This patch is derivat
PR Target/84790.
The gp init sequence
li $2,%hi(_gp_disp)
addiu $3,$pc,%lo(_gp_disp)
sll $2,16
addu$2,$3
is generated directly in `mips_output_function_prologue`, and does
not appear in the RTL.
So the IRA/IPA passes are not aware that $2/$3 have
commit 05daf617ea22e1d818295ed2d037456937e23530
Author: Jeff Law
Date: Sat May 25 12:39:05 2024 -0600
[committed] [v2] More logical op simplifications in simplify-rtx.cc
does some simplifications, and then `bseli.b $w1,$w0,255` is found that
it is same with `or.v $w1,$w0,$w1`. So there
When looking for as/ld/objcopy, `find_a_program/file_at_path` only
try to find the raw name, but won't find the one with -
prefix.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
* gcc.cc(for_each_path): Add more space for -.
(file_at_path):
If `find_a_program` cannot find `as/ld/objcopy` and we are a cross toolchain,
the final fallback is `as/ld` of system. In fact, we can have a try with
-as/ld/objcopy before fallback to native as/ld/objcopy.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
Jakub Jelinek 于2024年5月22日周三 17:33写道：
>
> On Wed, May 22, 2024 at 05:23:33PM +0800, YunQiang Su wrote:
> > Jakub Jelinek 于2024年5月22日周三 17:14写道：
> > >
> > > On Wed, May 22, 2024 at 05:05:30PM +0800, YunQiang Su wrote:
> > > > > --- gcc/gcc.cc
Jakub Jelinek 于2024年5月22日周三 17:14写道：
>
> On Wed, May 22, 2024 at 05:05:30PM +0800, YunQiang Su wrote:
> > > --- gcc/gcc.cc.jj 2024-02-09 14:54:09.141489744 +0100
> > > +++ gcc/gcc.cc 2024-02-09 22:04:37.655678742 +0100
> > > @@ -2410,8 +2410,7 @@ read_sp
pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "o");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "o");
> break;
>
> case 's':
> @@ -1599,8 +1634,8 @@ pp_format (pretty_printer *pp,
> pp_scalar (pp, HOST_WIDE_INT_PRINT_UNSIGNED,
>va_arg (*text->m_args_ptr, unsigned HOST_WIDE_INT));
> else
> - pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "u");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "u");
> break;
>
> case 'f':
> @@ -1629,8 +1664,8 @@ pp_format (pretty_printer *pp,
> pp_scalar (pp, HOST_WIDE_INT_PRINT_HEX,
>va_arg (*text->m_args_ptr, unsigned HOST_WIDE_INT));
> else
> - pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "x");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "x");
> break;
>
> case '.':
> @@ -2774,6 +2809,18 @@ test_pp_format ()
>ASSERT_PP_FORMAT_2 ("17 12345678", "%wo %x", (HOST_WIDE_INT)15,
> 0x12345678);
>ASSERT_PP_FORMAT_2 ("0xcafebabe 12345678", "%wx %x",
> (HOST_WIDE_INT)0xcafebabe,
> 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-27 12345678", "%zd %x", (ssize_t)-27, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-5 12345678", "%zi %x", (ssize_t)-5, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("10 12345678", "%zu %x", (size_t)10, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("17 12345678", "%zo %x", (size_t)15, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("cafebabe 12345678", "%zx %x", (size_t)0xcafebabe,
> + 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-27 12345678", "%td %x", (ptrdiff_t)-27, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-5 12345678", "%ti %x", (ptrdiff_t)-5, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("10 12345678", "%tu %x", (ptrdiff_t)10, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("17 12345678", "%to %x", (ptrdiff_t)15, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("1afebabe 12345678", "%tx %x", (ptrdiff_t)0x1afebabe,
> + 0x12345678);
>ASSERT_PP_FORMAT_2 ("1.00 12345678", "%f %x", 1.0, 0x12345678);
>ASSERT_PP_FORMAT_2 ("A 12345678", "%c %x", 'A', 0x12345678);
>ASSERT_PP_FORMAT_2 ("hello world 12345678", "%s %x", "hello world",
>
> Jakub
>
--
YunQiang Su
Andrew Pinski 于2024年5月21日周二 20:23写道：
>
> On Tue, May 21, 2024 at 5:12 AM YunQiang Su wrote:
> >
> > If `find_a_program` cannot find `as/ld` and we are a cross toolchain,
> > the final fallback is `as/ld` of system. In fact, we can have a try
> > with -as/ld b
If `find_a_program` cannot find `as/ld` and we are a cross toolchain,
the final fallback is `as/ld` of system. In fact, we can have a try
with -as/ld before fallback to native as/ld.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
* gcc.cc(execute):
PR target/113955
The `-mlra` option was introduced in 2014 for MIPS, and was set to
default since then. It's time for us to drop no-lra support by
dropping -m(no-)lra options.
gcc:
* config/mips/mips.cc(mips_option_override):
Drop mips_lra_flag variable;
(mips_lra_p):
Support syntax like:
asm volatile ("fmadd.d %w0, %w1, %w2" : "+w"(a): "w"(b), "w"(c));
gcc
* config/mips/constraints.md: Add new constraint 'w'.
gcc/testsuite
* gcc.target/mips/msa-inline-asm.c: New test.
---
gcc/config/mips/constraints.md | 3 +++
I will apply this patch.
While we still have a problem about
```
float max(float a, float b) { return a>=b?a:b; }
```
If it is compiled with `-ffinite-math-only -fsigned-zeros -O2
-mips32r6 -mabi=32`,
`max.s` can be used.
The max.fmt/min.fmt of MIPSr6 can process +0/-0 correctly.
Xi Ruoyao 于2024年3月26日周二 18:10写道：
>
> On Tue, 2024-03-26 at 11:15 +0800, YunQiang Su wrote:
>
> /* snip */
>
> > With -ffinite-math-only -fno-signed-zeros, it does work with
> > x >= y ? x : y
> > while without `-ffinite-math-only -fno-signed-zeros`, it c
Jeff Law 于2024年1月3日周三 01:00写道：
>
>
>
> On 1/1/24 09:48, YunQiang Su wrote:
> > When building multilib libraries, CC/CXX etc are set with an option
> > -B*/lib/, instead of -B/lib/.
> > This will make some trouble in some case, for example building
> > cro
PR target/113179.
In `store_bit_field_using_insv`, we just use SUBREG if value_mode
>= op_mode, while in some ports, a sign_extend will be needed,
such as MIPS64:
If either GPR rs or GPR rt does not contain sign-extended 32-bit
values (bits 63..31 equal), then the result of the operation is
Xi Ruoyao 于2024年3月20日周三 15:12写道：
>
> We were assuming TYPE_NO_NAMED_ARGS_STDARG_P don't have any named
> arguments and there is nothing to advance, but that is not the case
> for (...) functions returning by hidden reference which have one such
> artificial argument. This is causing
Jie Mei 于2024年3月25日周一 17:46写道：
>
> This patch adds the smin/smax RTL mode for the
> min/max.fmt instructions.
>
> Also, since the min/max.fmt instrucions applies to the
> IEEE 754-2008 "minNum" and "maxNum" operations, this
> patch also provides the new "fmin3" and
> "fmax3" modes.
>
>
Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access,
and RISC-V predefines __riscv_misaligned_avoid.
Let's define __mips_strict_alignment for MIPSr6 and -mstrict-align
is used.
Not that, this macro is always defined for pre-R6.
gcc
config/mips/mips.h
Sam James 于2024年3月17日周日 14:04写道：
>
> YunQiang Su writes:
>
> > Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access,
> > and RISC-V predefines __riscv_misaligned_avoid, while other ports
> > that support -mstrict-align/-mno-unaligned-acces
Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access,
and RISC-V predefines __riscv_misaligned_avoid, while other ports
that support -mstrict-align/-mno-unaligned-access don't have such
macro, and these backend macros are only avaiable for c-family.
Note: Arm64 always predefine
Fixes: acc38ff59976 ("MIPS: Add -m(no-)strict-align option")
gcc/ChangeLog:
* config/riscv/riscv.opt.urls: Regenerated.
* config/rs6000/sysv4.opt.urls: Likewise.
* config/xtensa/xtensa.opt.urls: Likewise.
---
gcc/config/riscv/riscv.opt.urls | 2 +-
for this cases?
Should I push a new commit? Or in fact a single commit is preferred?
--
YunQiang Su
We support options -m(no-)unaligned-access 2 years ago, while
currently most of other ports prefer -m(no-)strict-align.
Let's support -m(no-)strict-align, and keep -m(no-)unaligned-access
as alias.
gcc
* config/mips/mips.opt: Support -mstrict-align, and use
TARGET_STRICT_ALIGN as
The problem is that, there are these lines in mips.opt.urls:
; skipping UrlSuffix for 'mabi=' due to finding no URLs
; skipping UrlSuffix for 'mno-flush-func' due to finding no URLs
; skipping UrlSuffix for 'mexplicit-relocs' due to finding no URLs
These lines is not fixed by this patch due
ation.
>
> But we should first apply this diff. Could you double check it is
> sane/correct?
>
> Thanks,
>
> Mark
--
YunQiang Su
Xi Ruoyao 于2024年2月5日周一 02:01写道：
>
> We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
> wrong because -0.0 is not 0 - 0.0. This causes some Python tests to
> fail when Python is built with MSA enabled.
>
> Use the bnegi.df instructions to simply reverse the sign bit instead.
>
GAS introduced explicit relocs since 2001, and %pcrel_hi/low were
introduced in 2014. In future, we may introduce more.
Let's convert -mexplicit-relocs option, and accpet options:
none, base, pcrel.
We also update gcc/configure.ac to set the value to option
the gas support when GCC itself
From: YunQiang Su
Currently, almost all of the shared libraries of MIPS, rely on $t9
to get the address of current function, instead of PCREL instructions,
even on MIPSr6. So we have to set $t9 properly.
To get the address of preemptible function, we need the help of GOT.
MIPS/O32 has .cpload
estsuite/gcc.c-torture/execute/pr113010.c
> @@ -0,0 +1,9 @@
> +int minus_1 = -1;
> +
> +int
> +main ()
> +{
> + if ((0, 0xul) >= minus_1)
There is a warning option:
-Wsign-compare
Warn when a comparison between signed and unsigned values could
produce an incorrect result when the signed value is converted to unsigned.
> +__builtin_abort ();
> + return 0;
> +}
> --
> 2.34.1
>
--
YunQiang Su
ion is needed to
> > enable vectorizations. For example, ia64,x86,aarch64, and riscv
> > architectures, vectorization is enabled by default.
>
> But no. The default baseline of 32-bit x86 is i686, which is basically
> a Pentium III launched in 1999 without any vector instructions.
>
> We are still missing something here.
>
There is a line
#define vector __attribute__((vector_size(4*sizeof(int
I guess it is the syntax needs to be supported.
--
YunQiang Su
YunQiang Su 于2023年8月25日周五 15:16写道：
>
> When working on LLVM, I found this problem
> https://github.com/llvm/llvm-project/issues/64974.
> Maybe it's time for us to reconsider the way of getting GOT address
> for PIC code.
>
I have my draft patch pushed to GitHub:
https://
$GP is used for expanding GOT load, and in the afterward passes,
we will try to use a temporary register instead.
If sucess, we have no need to store and reload $gp. The example
of failure is that the function calls a preemtive function.
We shouldn't use $GP for any other purpose in the code we
ude --enable-multilib \
--with-arch-32=mips32r2 --with-fp-32=xx \
--enable-multiarch --enable-targets=all \
--with-arch-64=mips64r2 --prefix=/usr --disable-libsanitizer
4. make -j
--
YunQiang Su
Fix build warning:
mips.cc: warning: unused parameter 'decl'.
gcc
* config/mips/mips.cc (mips_start_function_definition):
Add ATTRIBUTE_UNUSED.
---
gcc/config/mips/mips.cc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/mips/mips.cc
I have tested this patch on mips64el: No regression.
gcc/testsuite
* gcc.c-torture/compile/mipscop-1.c: Include stdio.h.
* gcc.c-torture/compile/mipscop-2.c: Ditto.
* gcc.c-torture/compile/mipscop-3.c: Ditto.
* gcc.c-torture/compile/mipscop-4.c: Ditto.
---
gcc/testsuite/gcc.c-torture/compile/mipscop-1.c | 1 +
This match pattern allows combination (zero_extract:DI 8, 24, QI)
with an sign-extend to 32bit INS instruction on TARGET_64BIT.
For SI mode, if the sign-bit is modified by bitops, we will need a
sign-extend operation. Since 32bit INS instruction can be sure that
result is sign-extended, and the
When combine some instructions, the generic `rtx_cost`
may over estimate the cost of result RTL, due to that
the RTL may be quite complex and `rtx_cost` has no
information that this RTL can be convert to simple
hardware instruction(s).
In this case, Let's use `insn_count * perf_ratio` to
estimate
The accurate cost of an pattern can get with
insn_count * perf_ratio
The default value is set to 0 instead of 1, since that
we will need to distinguish the default value and it is
really set for an pattern. Since it is not set for most
patterns yet, to use it, we will need to be sure
When building multilib libraries, CC/CXX etc are set with an option
-B*/lib/, instead of -B/lib/.
This will make some trouble in some case, for example building
cross toolchain based on Debian's cross packages:
If we have libc6-dev-i386-amd64-cross packages installed on
a non-x86 machine.
Richard Sandiford 于2023年12月30日周六 23:35写道：
>
> Ping^3
>
I am testing it on MIPS.
> --- a/gcc/common/config/aarch64/aarch64-common.cc
> +++ b/gcc/common/config/aarch64/aarch64-common.cc
> @@ -55,6 +55,7 @@ static const struct default_options
> aarch_option_optimization_table[] =
> {
make: *** No rule to make target 'check-g++'. Stop.
gcc
* doc/install.texi (Testing): Correct check-g++ to
check-gcc-c++.
---
gcc/doc/install.texi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index
> Right. But that's the whole point behind avoiding the narrowing subreg
> and forcing use of a truncate operation.
>
> So basically the question becomes is there a way to modify those bits in
> a way that GCC doesn't know that it needs to to truncate/extend?
>
I guess that this code may cause
This match pattern allows combination (zero_extract:DI 8, 24, QI)
with an sign-extend to 32bit INS instruction on TARGET_64BIT.
For SI mode, if the sign-bit is modified by bitops, we will need a
sign-extend operation. Since 32bit INS instruction can be sure that
result is sign-extended, and the
When we try to combine RTLs, the result may be very complex,
and `rtx_cost` may think that it need lots of costs. But in
fact, it may match a pattern in machine descriptions, which
may emit only 1 or 2 hardware instructions. This combination
may be refused due to cost comparison failure.
Since
When combine some instructions, the generic `rtx_cost`
may over estimate the cost of result RTL, due to that
the RTL may be quite complex and `rtx_cost` has no
information that this RTL can be convert to simple
hardware instruction(s).
In this case, Let's use `get_attr_insn_count` to estimate
the
The accurate cost of an pattern can get with
insn_count * perf_ratio
The default value is set to 0 instead of 1, since that
we will need to distinguish the default value and it is
really set for an pattern. Since it is not set for most
patterns yet, to use it, we will need to be sure
This match pattern allows combination (zero_extract:DI 8, 24, QI)
with an sign-extend to 32bit INS instruction on TARGET_64BIT.
The problem is that, for SI mode, if the sign-bit is modified by
bitops, we will need a sign-extend operation.
Since 32bit INS instruction can be sure that result is
The accurate cost of an pattern can get with
insn_count * perf_ratio
The default value is set to 0 instead of 1, since that
we will need to distinguish the default value and it is
really set for an pattern. Since it is not set for most
patterns yet, to use it, we will need to be sure
This match pattern allows combination (zero_extract:DI 8, 24, QI)
with an sign-extend to 32bit INS instruction on TARGET_64BIT.
The problem is that, for SI mode, if the sign-bit is modified by
bitops, we will need a sign-extend operation.
Since 32bit INS instruction can be sure that result is
Roger Sayle 于2023年12月29日周五 00:54写道：
>
>
>
> The current (default) behavior is that when the target doesn’t define
>
> TARGET_INSN_COST the middle-end uses the backend’s
>
> TARGET_RTX_COSTS, so multiplications are slower than additions,
>
> but about the same size when optimizing for size (with
In general, I agree with this change.
When gcc12 on RV64, more than one `sext.w` will be produced with our test.
(Note, use -O1).
>
> There are two things that help here. The first is that the most significant
> bit never appears in the middle of a field, so we don't have to worry about
>
Jeff Law 于2023年12月29日周五 02:23写道：
>
>
>
> On 12/28/23 07:59, Roger Sayle wrote:
> >
> > This patch fixes PR rtl-optmization/104914 by tweaking/improving the way
> > that fields are written into a pseudo register that needs to be kept sign
> > extended.
> Well, I think "fixes" is a bit of a
MIPS backend had some information about INSN, including length,
count etc.
And since some instructions are more costly, let's add a new
attr `perf_ratio`. It's default value is (const_int 1).
The return value of mips_insn_cost is
insn_count * perf_ratio * 4.
The magic `4` here, is due to
Roger Sayle 于2023年12月24日周日 16:51写道：
>
>
> > What's exceedingly weird is T_N_T_M_P (DImode, SImode) isn't actually a
> > truncation! The output precision is first, the input precision is second.
> > The docs
> > explicitly state the output precision should be smaller than the input
> >
Roger Sayle 于2023年12月24日周日 08:49写道：
>
>
> Hi YunQiang (and Jeff),
>
> > MIPS claims TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true
> > based on that the hard register is always sign-extended, but here
> > the hard register is polluted by zero_extract.
>
> I suspect that the bug here is
> > Yes. I also guess so. Any new idea?
> Well, I see multiple intertwined issues and I think MIPS has largely
> mucked this up.
>
> At a high level DI -> SI truncation is not a nop on MIPS64. We must
> explicitly sign extend the value from SI->DI to preserve the invariant
> that SI mode objects
Jeff Law 于2023年12月24日周日 00:51写道：
>
>
>
> On 12/23/23 01:58, YunQiang Su wrote:
> > On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms,
> > if 31 or above bits is polluted by an bitops, we will need an
> > truncate. Let's emit one, and m
On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms,
if 31 or above bits is polluted by an bitops, we will need an
truncate. Let's emit one, and mark let's use the same hardreg
as in and out, the RTL may like:
(insn 21 20 24 2 (set (subreg/s/u:SI (reg/v:DI 200 [ val ]) 0)
Users may wish just use -mtune=native for performance tuning only.
Let's don't make trouble for its case.
gcc/
* config/mips/driver-native.cc (host_detect_local_cpu):
don't add nan2008 option for -mtune=native.
---
gcc/config/mips/driver-native.cc | 3 ++-
1 file changed, 2
The function `reconcat` cannot append string(s) to NULL,
as the concat process will stop at the first NULL.
Let's always put the `ret` to the end, as it may be NULL.
We keep use reconcat here, due to that reconcat can make it
easier if we add more hardware features detecting, for example
by
Jakub Jelinek 于2023年12月19日周二 16:40写道：
>
> On Tue, Dec 19, 2023 at 09:30:49AM +0800, YunQiang Su wrote:
> > The function `reconcat` cannot append string(s) to NULL,
> > as the concat process will stop at the first NULL.
> >
> > Let's always put the `ret` to the end,
TRULY_NOOP_TRUNCATION.
>
> Where is the subreg being generated?
>
It's from expand_assignment(tree to, tree from, bool nontemporal) in expr.cc.
to_rtx = expand_expr (tem, NULL_RTX, VOIDmode, EXPAND_WRITE);
--
YunQiang Su
p;& reload_completed && register_operand (operands[1], VOIDmode)"
[(const_int 0)]
{
emit_note (NOTE_INSN_DELETED);
DONE;
}
[(set_attr "move_type" "move,move,load")
(set_attr "mode" "DI")])
--
YunQiang Su
The function `reconcat` cannot append string(s) to NULL,
as the concat process will stop at the first NULL.
Let's always put the `ret` to the end, as it may be NULL.
We keep use reconcat here, due to that reconcat can make it
easier if we add more hardware features detecting, for example
by
Jakub Jelinek 于2023年12月18日周一 16:10写道：
>
> On Mon, Dec 18, 2023 at 11:44:21AM +0800, YunQiang Su wrote:
> > The function `reconcat` cannot append string(s) to NULL,
> > as the concat process will stop at the first NULL.
> >
> > Let's initialize `ret` with `concat
For reconcat, if the `optr` can only be used as the last one
of string list, aka, we cannot append something to it.
Let's add some note into the document.
libiberty:
* concat.c (reconcat): Add note about append string to NULL
into document.
---
libiberty/concat.c | 3 +++
1 file
The function `reconcat` cannot append string(s) to NULL,
as the concat process will stop at the first NULL.
Let's initialize `ret` with `concat (" ", NULL)`, then
it can be used by reconcat.
gcc/
PR target/112759
* config/mips/driver-native.cc (host_detect_local_cpu):
sisa64r2*)
> - tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R2
> MIPS_ABI_DEFAULT=ABI_N32"
> + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R2
> MIPS_ABI_DEFAULT=ABI_N32"
> ;;
> mipsisa64*)
> - tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64
> MIPS_ABI_DEFAULT=ABI_N32"
> + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64
> MIPS_ABI_DEFAULT=ABI_N32"
> ;;
> esac
> ;;
>
> Jakub
>
--
YunQiang Su
Schwab
m68k-motorola-sysv portPhilippe De Muyter
mcore port Nick Clifton
microblaze Michael Eager
-mips port YunQiang Su
+mips port YunQiang Su
mmix port Hans-Peter
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008.
Let's use this behaivor by default in GCC, aka
gcc -mnan=2008 -c fabs.c
will imply `-mabs=2008`.
And of course, `gcc -mnan=2008 -mabs=legacy` can continue workable
like previous.
gcc/ChangeLog
*
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008.
Let's use this behaivor by default in GCC, aka
gcc -mnan=2008 -c fabs.c
will imply `-mabs=2008`.
And of course, `gcc -mnan=2008 -mabs=legacy` can continue workable
like previous.
gcc/ChangeLog:
*
> I think that is too new.
> We still allow building gcc e.g. with GCC 4.8 from ~ 10 years ago and
> I think various boxes where people regularly build gcc will have similarly
> old other tools.
> So, bumping requirement from ~ 20 years old tools to ~ 10 years old tools
> might be ok, but
/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf
Page 404
--
YunQiang Su
an that in the RTL, for this operation:
we should have 3 (insn ) RTX?
(zero_extract )
(truncate_64_to_32)
(sign_extend_32_to_64)
> What piece of code is generating the subreg?
>
> Thanks,
> Richard
--
YunQiang Su
YunQiang Su 于2023年8月3日周四 11:18写道：
>
> PR #104914
>
> On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms,
> zero_extract (SI, SI) can be sign-extended. So, if a zero_extract (DI,
> DI) following with an sign_extend(SI, DI) can be merged to a single
>
PR #104914
On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms,
zero_extract (SI, SI) can be sign-extended. So, if a zero_extract (DI,
DI) following with an sign_extend(SI, DI) can be merged to a single
zero_extract (SI, SI).
gcc/ChangeLog:
PR: 104914.
*
DE (x))
> {
> case CONST_INT:
> case ROTATE:
> case ROTATERT:
> case SIGN_EXTRACT:
> case ZERO_EXTRACT:
> return false;
>
> default:
> return true;
> }
> }
>
> --
> Eric Botcazou
>
>
--
YunQiang Su
Richard Biener 于2023年7月19日周三 17:23写道：
>
> On Wed, 19 Jul 2023, YunQiang Su wrote:
>
> > Richard Biener ?2023?7?19??? 15:22???
> > >
> > > On Wed, 19 Jul 2023, YunQiang Su wrote:
> > >
> > > > Richard Biener via Gcc-patches ?2023?7?19???
&g
[0]))
(reg:SI 102)) "xx.c":3:29 -1
(nil))
YunQiang Su 于2023年7月19日周三 16:25写道：
>
> YunQiang Su 于2023年7月19日周三 16:21写道：
> >
> > Richard Biener 于2023年7月19日周三 15:22写道：
> > >
> > > On Wed, 19 Jul 2023, YunQiang Su wrote:
> >
YunQiang Su 于2023年7月19日周三 16:21写道：
>
> Richard Biener 于2023年7月19日周三 15:22写道：
> >
> > On Wed, 19 Jul 2023, YunQiang Su wrote:
> >
> > > Richard Biener via Gcc-patches ?2023?7?19???
> > > 14:27???
> > > >
> > > > On
Richard Biener 于2023年7月19日周三 15:22写道：
>
> On Wed, 19 Jul 2023, YunQiang Su wrote:
>
> > Richard Biener via Gcc-patches ?2023?7?19???
> > 14:27???
> > >
> > > On Wed, 19 Jul 2023, YunQiang Su wrote:
> > >
> > > > PR #104914
> >
Richard Biener via Gcc-patches 于2023年7月19日周三 14:27写道：
>
> On Wed, 19 Jul 2023, YunQiang Su wrote:
>
> > PR #104914
> >
> > When work with
> > int val;
> > ((unsigned char*))[3] = *buf;
> > if (val > 0) ...
> > The RTX mode is obtaine
PR #104914
When work with
int val;
((unsigned char*))[3] = *buf;
if (val > 0) ...
The RTX mode is obtained from REG instead of SUBREG, which make
D is used instead of . Thus something wrong happens
on sign-extend default architectures, like MIPS64.
Let's use str_rtx and mode of str_rtx as
PR #104914
When work with
int val;
((unsigned char*))[3] = *buf;
if (val > 0) ...
The RTX mode is obtained from REG instead of SUBREG, which make
D is used instead of . Thus something wrong happens
on sign-extend default architectures, like MIPS64.
Let's use str_rtx and mode of str_rtx as
> 2023年7月12日 15:44，Richard Biener 写道：
>
> On Wed, Jul 12, 2023 at 5:20 AM YunQiang Su wrote:
>>
>> PR #104914
>>
>> When work with
>> int val;
>> ((unsigned char*))[0] = *buf;
>> The RTX mode is obtained from REG instead of SUBREG,
>
PR #104914
When work with
int val;
((unsigned char*))[0] = *buf;
The RTX mode is obtained from REG instead of SUBREG,
which make D is used instead of .
Thus something wrong happens on sign-extend default architectures,
like MIPS64.
gcc/ChangeLog:
PR: 104914.
*
{ dg-options "(HAS_MOVN) -mhard-float -mbranch-cost=3" } */
> /* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os" } { "" } } */
> /* { dg-final { scan-assembler "\tmovt\t" } } */
> /* { dg-final { scan-assembler "\tmovf\t" } } */
> --
> 2.40.1
--
YunQiang Su
YunQiang Su 于2023年6月29日周四 14:04写道：
>
> Jovan Dmitrovic 于2023年6月27日周二 16:54写道：
> >
> > Hi,
> > I am sending a revised patch, now with different tests for N64/N32 and O32
> > ABIs.
> > For the O32 ABI, I've skipped the -O0 and -Os pipelines, considering th
s (the registers used
> remain
> the same).
>
> Skipping -flto isn't really necessary, so I've removed that part.
>
> I've fixed the Changelog, hopefully I've corrected the mistakes I made.
>
Looks good.
I will submit this patch with some format improvement.
> Regards,
> Jovan
--
YunQiang Su
igned temp2 = callee (1, identity (vec));
> + assert (callee (1, temp) == 1);
> + assert (temp2 == 1);
> + return 0;
> +}
> +
> +/* { dg-final { scan-assembler "\tsd\t\\\$5,0\\(\\\$\[0-9\]\\)" } } */
> +/* { dg-final { scan-assembler "\tsd\t\\\$6,8\\(\\\$\[0-9\]\\)" } } */
> +/* { dg-final { scan-assembler "\tsd\t\\\$7,16\\(\\\$\[0-9\]\\)" } } */
I guess, this test may fail for mips32 targets?
Maybe we can add 2 tests: one for O32, and one for N32/N64.
Add `-mabi=32`/`-mabi=n32` option into `dg-do compile` line.
> --
> 2.34.1
>
>
>
>
> --
> YunQiang Su
--
YunQiang Su
Richard Earnshaw (lists) via Gcc-patches
于2023年6月8日周四 20:36写道：
>
>
> On 01/06/2023 05:26, YunQiang Su wrote:
> > speculation_barrier for MIPS needs sync+jr.hb (r2+),
> > so we implement __speculation_barrier in libgcc, like arm32 does.
> >
> > gcc/ChangeLog:
>
gt; registers when invoking a function. I don't know whether
> writing this testcase as an assembly check would make sense,
> because that would make the testcase much less readable.
I prefer an assembly check, because the test can be used even
for cross building.
It is not required, I guess.
> __
" } { "" } } */
> +
> +volatile int x1;
> +volatile int x2;
> +volatile int x3;
> +volatile int x4;
> +volatile int x5;
> +volatile int x6;
> +volatile int x7;
> +volatile int x8;
> +volatile int x9;
> +volatile int x10;
> +volatile int x11;
> +
> +MIPS16 __attribute__((code_readable ("yes"))) int
> +foo (int i, volatile int *x)
> +{
> + switch (i)
> +{
> +case 1: return x1 + x[0];
> +case 2: return x2 + x[1];
> +case 3: return x3 + x[2];
> +case 4: return x4 + x[3];
> +case 5: return x5 + x[4];
> +case 6: return x6 + x[5];
> +case 7: return x7 + x[6];
> +case 8: return x8 + x[7];
> +case 9: return x9 + x[8];
> +case 10: return x10 + x[9];
> +case 11: return x11 + x[10];
> +default: return 0;
> +}
> +}
> +
> +extern int k[];
> +
> +MIPS16 __attribute__((code_readable ("yes"))) int *
> +bar (void)
> +{
> + return k;
> +}
> +
> +/* { dg-final { scan-assembler "\tdla\t" } } */
> +/* { dg-final { scan-assembler "\t\\.half\t" } } */
> +/* { dg-final { scan-assembler-not "%hi\\(\[^)\]*L" } } */
> +/* { dg-final { scan-assembler-not "%lo\\(\[^)\]*L" } } */
> +
> +/* { dg-final { scan-assembler "\t\\.dword\tk\n" } } */
> +/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */
> +/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */
> diff --git a/gcc/testsuite/gcc.target/mips/code-readable-attr-5.c
> b/gcc/testsuite/gcc.target/mips/code-readable-attr-5.c
> new file mode 100644
> index 000..0a547a9acfc
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/mips/code-readable-attr-5.c
> @@ -0,0 +1,5 @@
> +/* { dg-options "(-mips16) isa_rev<=5" } */
> +
> + __attribute__((code_readable ("magic"))) int foo () {} /* { dg-warning
> "argument to 'code_readable' attribute is neither no, pcrel nor yes" } */
> +
> + __attribute__((code_readable (1))) int * bar () {} /* { dg-warning
> "'code_readable' attribute requires a string argument" } */
> --
> 2.40.1
--
YunQiang Su
In 4fe6e12204535545edf7f035d4dc79c1404058cf, I should have added
Matthew Fortune to the Write After Approval section, while replacing
the MIPS Maintainer position.
ChangeLog:
* MAINTAINERS (Write After Approval): move Matthew Fortune
to Write After Approval.
---
MAINTAINERS | 1
+mips port YunQiang Su
mmix port Hans-Peter Nilsson
mn10300 port Jeff Law
mn10300 port Alexandre Oliva
@@ -652,7 +652,6 @@ Basile Starynkevitch
Jakub Staszak
speculation_barrier for MIPS needs sync+jr.hb (r2+),
so we implement __speculation_barrier in libgcc, like arm32 does.
gcc/ChangeLog:
* config/mips/mips-protos.h (mips_emit_speculation_barrier): New
prototype.
* config/mips/mips.cc (speculation_barrier_libfunc): New static
ute__ ((aligned(64)));
> +
> +unsigned
> +callee (int x, uint8 a)
> +{
> + return a.v[0];
> +}
> +
> +uint8
> +identity (uint8 in)
> +{
> + return in;
> +}
> +
> +int
> +main (void)
> +{
> + uint8 vec = {{1, 2, 3, 4, 5, 6, 7, 8}};
> + uint8 temp = identity (vec);
> + unsigned temp2 = callee (1, identity (vec));
> + assert (callee (1, temp) == 1);
> + assert (temp2 == 1);
> + return 0;
> +}
> --
> 2.34.1
>
--
YunQiang Su
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