Re: [PATCH] [aarch64] Revert support for ARMv8.2 in tsv110

Hi Richard, On 2018/12/19 18:12, Richard Earnshaw (lists) wrote: > On 19/12/2018 03:11, Shaokun Zhang wrote: >> For HiSilicon's tsv110 cpu core, it supports some v8_4A features, but >> some mandatory features are not implemented. Revert to ARMv8.2 that >> all mandatory features are supported. >>

Re: [PATCH v4] [aarch64] Add HiSilicon tsv110 CPU support

Hi Kyrill, Thanks your reply. On 2018/9/26 19:20, Kyrill Tkachov wrote: > Hi Shaokun, > > On 25/09/18 14:40, Zhangshaokun wrote: >> Hi ARM maintainers, >> >> Any plan to support CTR_EL0.DIC and CTR_EL0.IDC in GCC? >> I saw it has been supported in linux

Re: [PATCH v4] [aarch64] Add HiSilicon tsv110 CPU support

Hi ARM maintainers, Any plan to support CTR_EL0.DIC and CTR_EL0.IDC in GCC? I saw it has been supported in linux mainline(on Mar 7), Patch link: http://lists.infradead.org/pipermail/linux-arm-kernel/2018-March/565090.html Kernel link:

Re: [PATCH v4] [aarch64] Add HiSilicon tsv110 CPU support

Hi Kyrill, On 2018/9/21 20:25, Kyrill Tkachov wrote: > Hi Shaokun, > > On 20/09/18 15:54, Zhangshaokun wrote: >> Hi James, >> >> On 2018/9/20 22:22, James Greenhalgh wrote: >>> On Wed, Sep 19, 2018 at 04:53:52AM -0500, Shaokun Zhang wrote: >>>> Th

Re: [PATCH v4] [aarch64] Add HiSilicon tsv110 CPU support

Hi James, On 2018/9/20 22:22, James Greenhalgh wrote: > On Wed, Sep 19, 2018 at 04:53:52AM -0500, Shaokun Zhang wrote: >> This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A. >> It has been tested on aarch64 and no regressions from this patch. > > This patch is OK for Trunk. > >

Re: [PATCH v3] [aarch64] Add HiSilicon tsv110 CPU support

Hi maintainers, A gentle ping. Thanks, Shaokun On 2018/6/21 19:13, Shaokun Zhang wrote: > This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A. > It has been tested on aarch64 and no regressions from this patch. > > --- > gcc/ChangeLog| 8 +++ >

Re: [PATCH v2] [aarch64] Add HiSilicon tsv110 CPU support

Hi Kyrill, On 2018/6/21 20:56, Kyrill Tkachov wrote: > Hi Shaokun, > > On 21/06/18 12:07, Zhangshaokun wrote: >> Hi Kyrill, >> >> It was the Dragon Boat Festival for a short holiday in China, sorry to >> reply later. >> >> On 2018/6/14 15:58, Kyrill

Re: [PATCH v2] [aarch64] Add HiSilicon tsv110 CPU support

Hi Kyrill, It was the Dragon Boat Festival for a short holiday in China, sorry to reply later. On 2018/6/14 15:58, Kyrill Tkachov wrote: > Hi Shaokun, > > On 14/06/18 02:09, Shaokun Zhang wrote: >> This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A. >> >> --- >> gcc/ChangeLog

Re: [RFC] [aarch64] Add HiSilicon tsv110 CPU support

Hi Kyrill, On 2018/6/6 22:51, Kyrill Tkachov wrote: > Hi Shaokun, > > On 01/06/18 10:56, Zhangshaokun wrote: >> Hi Ramana, >> >> Sorry to reply so later because of short leave. >> >> On 2018/5/23 18:41, Ramana Radhakrishnan wrote: >>> >>>

Re: [RFC] [aarch64] Add HiSilicon tsv110 CPU support

Hi Ramana, Sorry to reply so later because of short leave. On 2018/5/23 18:41, Ramana Radhakrishnan wrote: > > > On 23/05/2018 03:50, Zhangshaokun wrote: >> Hi Ramana, >> >> On 2018/5/22 18:28, Ramana Radhakrishnan wrote: >>> On Tue, May 22, 2018

Re: [RFC] [aarch64] Add HiSilicon tsv110 CPU support.

Hi Kyrill, On 2018/5/23 16:08, Kyrill Tkachov wrote: > > On 23/05/18 05:54, Zhangshaokun wrote: >> Hi Kyrill, >> >> On 2018/5/22 18:52, Kyrill Tkachov wrote: >>> Hi Shaokun, >>> >>> On 22/05/18 09:40, Shaokun Zhang wrote: >>>> This p

Re: [RFC] [aarch64] Add HiSilicon tsv110 CPU support.

Hi Kyrill, On 2018/5/22 18:52, Kyrill Tkachov wrote: > Hi Shaokun, > > On 22/05/18 09:40, Shaokun Zhang wrote: >> This patch adds HiSilicon's an mcpu: tsv110. >> >> --- >> gcc/ChangeLog| 9 +++ >> gcc/config/aarch64/aarch64-cores.def | 5 ++ >>

Re: [RFC] [aarch64] Add HiSilicon tsv110 CPU support

Hi Ramana, On 2018/5/22 18:28, Ramana Radhakrishnan wrote: > On Tue, May 22, 2018 at 9:40 AM, Shaokun Zhang > wrote: >> tsv110 is designed by HiSilicon and supports v8_4A, it also optimizes >> L1 Icache which can access L1 Dcache. >> Therefore, DC CVAU is not