mp; mask__4.12_197;
vect_patt_158.14_199 = .VCOND_MASK (mask_patt_157.13_198, { 1, 1, 1, 1, 1, 1,
1, 1 }, { 0, 0, 0, 0, 0, 0, 0, 0 });
vect_patt_159.15_200 = [vec_unpack_lo_expr] vect_patt_158.14_199;
vect_patt_159.15_201 = [vec_unpack_hi_expr] vect_patt_158.14_199;
juzhe.zh...@rivai.ai
From: R
LGTM. I think removing riscv_vector_abi can be another separate followup patch.
But plz make sure you have passed the regression before committed.
Thanks.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-15 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; lehua.ding
I think you should also remove riscv_vector_abi
since vector ABI is ratified and we should by default enable vector calling
convention by default.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-15 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; lehua.ding; yanzhang.wang
. */
if (!loop_vinfo)
record_stmt_cost (cost_vec, 1, vec_to_scalar, stmt_info, NULL_TREE,
0, vect_epilogue);
Since it's stage 4, I guess we can't change this now.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2024-01-11 17:57
To: Robin Dapp
CC: juzhe.zh
ok.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:24
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Rewrite some instructions using ASM
ok.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:23
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v6] RISC-V: Fix register overlap issue for some
ok
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:22
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v6] RISC-V: Handle differences between XTheadvector
OK.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:21
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Adds the prefix &qu
This patch needs kito review. I can't approve that.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:20
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; kito.cheng; Jun Sha (Joshua); Jin Ma; Xianmiao
Qu
Subject
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-01-12 10:52
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Update the comments of riscv_v_ext_mode_p [NFC]
From: Pan Li
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_ext_mode_p): Update
Good catch. LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-12 09:35
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Modify ABI-name length of vfloat16m8_t
The length of vfloat16m8_t ABI-name should be 17.
gcc/ChangeLog:
* config/riscv
ocal count: 359464610]:
goto ; [100.00%]
}
Final ASM:
main:
lui a5,%hi(a)
li a4,19
sb a4,%lo(a)(a5)
li a0,0
ret
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 20:56
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH
e later pass failed
to CSE it...
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 19:15
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Increase scalar_to_vec_cost from 1 to 3
> I think we sho
for this test.
Is it reasonable ? IMHO, scalar move (vmv.v.x or vfmv.v.f) should be more
costly than normal vadd.vv since it is transferring data between different
pipeline/register class.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 19:15
To: juzhe.zh...@rivai.ai; Richard Biener
CC
times scalar_to_vec costs 3 in prologue
32872 spends 2 scalar instructions + 1 scalar_to_vec cost:
li a4,-32768
addiw a4,a4,104
vmv.v.x v16,a4
It seems reasonable but only can fix test with -march=rv64gcv_zvl256b but
failed on -march=rv64gcv_zvl4096b.
juzhe.zh...@rivai.ai
From: Robin Dapp
Da
.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 19:15
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Increase scalar_to_vec_cost from 1 to 3
> I think we shouldn't vectorize it with any vlen, since the
b, RVV Clang also doesn't vectorize it.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 18:40
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Increase scalar_to_vec_cost from 1 to 3
On 1/11/24 11:
t_26 1 times scalar_to_vec costs 1 in prologue
This cost should be higher since it cost 3 instructions:
li a4,-32768
addiw a4,a4,104
vmv.v.x v16,a4
Am I correct ?
I guess if we cost 1 case as 1 cost and 2 case as 3 cost. Then we will be good.
juzhe.zh...@rivai.ai
From: Robi
And also I have investigate LLVM cost model. They don't cost vsevli in
vectorization cost model.
But their cost model does a good job...
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 18:09
To: Richard Biener
CC: rdapp.gcc; juzhe.zh...@rivai.ai; gcc-patches; kito.cheng; Kito.cheng
>> That said, we also don't really cost all our vsetvls yet (difficult...).
If cost vsetvl, we will need to cost 1 more for each STMT.
However, it is not accurate. Since our VSETVL PASS will eliminate redundancy...
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 18:09
To: R
t;seem that bad.
Yeah... I just noticed. I should set it as 4 to fix it with biggest VLEN size,
that is, -march=rv64gcv_zvl4096b --param=riscv-autovec-lmul=m8...
I am confused now how to fix this case.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 17:52
To: juzhe.zh...@rivai.ai; R
XTRACT (vect_patt_27.14_145, _147);
b_5 = _148;
a = 19;
_14 = b_5 != 0;
_15 = (int) _14;
return _15;
The vect dump tree only compute cost include vector_stmt and scalar_to_vec.
It seems it didn't consider VEC_EXTRACT cost ?
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2024-01-11 1
Thanks Richard.
So you think increase scalar_to_vec cost is not the correct approach to fix
this case?
Or could you give me a suggestion to fix this case ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2024-01-11 17:18
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; kito.cheng
problem if
they tried to use RVV GCC with like zvl8192b.
juzhe.zh...@rivai.ai
Ok from myside. CCing Robin to see whether he has any more concerns.
Thanks.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-11 10:39
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma
So vlb has not only sew = 8 ?
But why do you add intrinsics as follows ?
+DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds,
i8_v_scalar_const_ptr_ops)
Why it is not :
DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds,
all_v_scalar_const_ptr_ops)
?
juzhe.zh...@rivai.ai
发件人
Why do you need to invade existing shapes ?
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-10 15:16
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Handle differences
Foundation, Inc.
Incorrect copyright
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-10 10:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Handle differences between XTheadvector
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html
This patch is ok from my side.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-10 10:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma
LGTM from myside. Give another a few more days that some one want to chime in.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-10 14:51
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma
ing "no")
+ ]
Change it into:
+ (and (eq_attr "group_overlap" "thv_disabled")
+ (match_test "TARGET_XTHEADVECTOR"))
+ (const_string "no")
+
+ (and (eq_attr "group_overlap" "rvv_disabled")
+ (match_test "TARGET
vi, vi, vr, vr, vi, vi")])
+ (match_operand: 2 "vector_merge_operand"" vu,0,
vu,0, vu,0, vu,0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)"
"vms%B3.v%o5\t%0,%4,%v5%p1"
[(set_attr &qu
of RV32 an RV64 of GCC testsuite.
Do you have more patches of theadvector that I didn't review ? plz point them
to me again.
Thanks.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-10 10:22
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw
Yes. It does sufficient. Send a patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642216.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-09 00:45
To: 钟居哲; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; Jeff Law
Subject: Re: [PATCH] RISC-V: Teach liveness computation
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-05 17:23
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Fix avl-type operand index error for ZVBC
This patch fix the rtl-checking error for crypto vector. The root
cause is the avl-type
nst_int 5)
Ah, I knew something go wrong in case of attribute bugs.
I think it should be a separate patch which is "Fix vlmax type attribute bugs
of vclmul and vclmulh instructions".
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-05 16:51
To: gcc-patches
CC: kito.cheng; jeffreyalaw
I have reverted those 2 commits:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=960c2620db254a1edc2cd61e608df73073b3de0d
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b3ec98d458f2b285bb7b3fa4fcd93fd830fee069
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2024-01-05 11:24
To: juzhe.zhong
he patch, then commit it after he fixes the ICE with
enabling RTL check.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2024-01-05 11:24
To: juzhe.zhong
CC: gcc-patches; Kito Cheng; Kito.cheng
Subject: Re: [committed] RISC-V: Add crypto vector builtin function.
On Thu, 04 Jan 2024 19:17:21 PS
:
../../configure --enable-gcc-checking=rtl.
Plz enable rtl check in the regression tests.
juzhe.zh...@rivai.ai
\ No newline at end of file
Each file needs newline.
I am not able to review arch stuff. This needs kito.
Besides, Andrew Pinski want us defer theadvector to GCC-15.
I have no strong opinion here.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-04 17:15
收件人： 钟居哲; Jeff Law; gcc-patches
抄送
While working on PR113209, I noticed it is same issue so this patch not only
fixes PR113206 bug, but also fixes
PR113209.
Send V2 with adding PR113209 test and PR target/113209:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641740.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-03 13:21
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v7 2/2] RISC-V: Add crypto vector api-testing cases.
Patch v7: Add newline at the end of file.
Patch v6: Move intrinsic tests into rvv/base
No. It will need to change all patterns in vector.md.
It's a nightmare.
You should note I will refine vector.md in GCC-15, mixing theadvector things
make me impossible to maintain
RVV1.0.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2024-01-03 11:19
To: juzhe.zh...@rivai.ai
CC
We have no choice. You should know theadvector is totally unrelated with RVV1.0
standard ISA.
Adding `%^' which missing totally unrelated ISA makes no sens to me.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2024-01-03 10:54
To: 钟居哲
CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilson.gcc
\ No newline at end of file
All files Need newline.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-03 09:01
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v6 2/2] RISC-V: Add crypto vector api-testing cases.
Patch v6: Move intrinsic tests into rvv/base
Move all tests into gcc.target/riscv/rvv/base
All of these:
#include
change them into:
#include "riscv_vector.h"
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-02 15:47
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v5 2/2] RISC-V: Add cry
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-02 17:18
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v6 1/2] RISC-V: Add crypto vector builtin function.
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def
+/* Static information about a set of crypto vector functions. */
+struct crypto_function_group_info
+{
+ struct function_group_info rvv_function_group_info;
+ /* Whether the function is available. */
+ unsigned int (*avail) (void);
+};
What is this used for ?
juzhe.zh...@rivai.ai
From
LGTM assume you have passed the regression.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-29 12:10
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4] RISC-V
LGTM assume you have passed the regression.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-29 12:06
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4] RISC-V
send V2 with test tweak:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641447.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-12-27 09:52
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Disallow transformation
OK.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-25 16:14
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4 4/6] RISC-V: Adds the prefix &qu
OK. This sub-patch is ok to commit after adding new line to prefix.c
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2023-12-25 15:08
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： 回复：[PATCH v4 4/6] RISC-V
e
New line should be added into prefix.c
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-25 14:25
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4 4/6] RISC-
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_VECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4&qu
constraint using attribute, More details
you can learn from
(set_attr "group_overlap"
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2023-12-22 11:33
收件人： 钟居哲; gcc-patches
抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Jeff Law; Christoph
Müllner; jinma; Cooper Qu
主题： 回复：[PATCH v3 0
Machine description part is ok from my side.
But I don't know the plan of vector crypto.
I'd like to wait kito or Jeff to make sure we allow vector-crypto intrinsics as
part of GCC-14 release.
Thanks.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-22 09:59
To: gcc-patches
CC
Also the copy right is incorrect:
+;; Copyright (C) 2022-23 Free Software Foundation, Inc.
It should be:
Copyright (C) 2023 Free Software Foundation, Inc.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-22 09:38
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject
\ No newline at end of file
Still no new line in vector-iterator.md
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-22 09:38
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v7 2/3] RISC-V: Add crypto machine descriptions
Patch v7: Remove mode
ntrinsics s
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
\ No newline at end of file
Each file needs a newline.
+ (match_operand:VSI 1 "vector_merge_operand"
erand"))
(match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero")]
UNSPEC_SEL))]
"TARGET_SVE"
)
Otherwise, LGTM. But I'd like to expect Kito chime in.
Thanks.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-21 10:48
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzh
OK. Sounds reasonable.
But from my side, I used to commit patches after full coverage testing.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-12-21 11:28
To: 钟居哲; cooper.joshua; gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma;
Cooper Qu
Subject: Re
I see. LGTM. Thanks for explanation.
I will ask Li Pan commit it for you.
Thanks.
juzhe.zh...@rivai.ai
From: Demin Han
Date: 2023-12-20 19:10
To: juzhe.zh...@rivai.ai; gcc-patches
CC: pan2.li
Subject: Re: [PATCH] RISC-V: Fix calculation of max live vregs
Hi juzhe,
The live ranges
(I am happy with those 2 cases be changed as using larger
LMUL )?
It seems this patch is ignoring the first vectorized statement during the live
calculation ?
Thanks.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2023-12-20 16:15
To: gcc-patches@gcc.gnu.org
CC: juzhe.zh...@rivai.ai; pan2
OK。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-20 17:35
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng; jeffreyalaw
Subject: [PATCH v3] RISC-V: Bugfix for the const vector in single steps
From: Pan Li
This patch would like to fix the below execution failure when
>> The description in the spec is"Each bit of Op1 is inverted and logically
>> ANDed with the corresponding bits in vs2",
>> so I think the "and" should be placed outside.
Ah. Yes.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-20 16:09
To
tch_operand: 4 "register_operand" " r, r, r, r")))
->
+ (and:VI_QHS+ (not:VI_QHS+(vec_duplicate:VI_QHS
+(match_operand: 4 "register_operand" " r, r, r, r")))
+ (match_operand:VI_QHS 3 "register_operand" "vr, v
ass rvv_builder
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-20 14:56
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng; jeffreyalaw
Subject: [PATCH v2] RISC-V: Bugfix for the const vector in single steps
From: Pan Li
This patch would like to fix the below execution fail
+ if (known_eq (ele_0 - 0, ele_n - v.npatterns ()))
->
for (i = 0; i < v.npatterns (); )
check each nelt of npatterns is equal to vid.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-20 10:39
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PA
?
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2023-12-20 10:04
To: Richard Biener; juzhe.zh...@rivai.ai; Robin Dapp; gcc-patches; pan2.li;
Richard Biener; pinskia; richard.sandiford
Subject: Re: [PATCH] fold-const: Handle AND, IOR, XOR with stepped vectors
[PR112971].
On Tue, Dec 19, 2023
or RVV.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-12-19 18:40
To: Richard Biener
CC: juzhe.zhong\@rivai.ai; Robin Dapp; gcc-patches; pan2.li; Richard Biener;
pinskia
Subject: Re: [PATCH] fold-const: Handle AND, IOR, XOR with stepped vectors
[PR112971].
Richard Biener writes:
> O
| code == BIT_IOR_EXPR
|| code == BIT_XOR_EXPR);
juzhe.zh...@rivai.ai
From: Jakub Jelinek
Date: 2023-12-19 17:45
To: juzhe.zh...@rivai.ai
CC: rguenther; Robin Dapp; gcc-patches; pan2.li; richard.sandiford; Richard
Biener; pinskia
Subject: Re: Re: [PATCH] fold-const: Handle AND,
|| code == BIT_IOR_EXPR
|| code == BIT_XOR_EXPR);
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-12-19 17:12
To: juzhe.zh...@rivai.ai
CC: Robin Dapp; gcc-patches; pan2.li; richard.sandiford; Richard Biener; pinskia
Subject: Re: Re: [PATCH] fold-const: Handle AND, IOR, XOR with st
ng at the implementation it's odd that we can handle
VECTOR_CST_NELTS_PER_PATTERN == 1 (duplicate) and
== 3 (stepped) but not == 2 (not sure what that would be).
Maybe the tests can be re-formulated in terms of
VECTOR_CST_NELTS_PER_PATTERN?
Richard.
> Thanks.
>
>
>
> juzhe.zh.
OK。
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-19 09:44
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] testsuite: Fix cpymem-2.c dump checks under different
riscv-sim for RVV.
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem
Thanks for refactor it. You can commit it today.
Thanks.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-18 11:28
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Add required_extensions in function_group
In order to add other vector related
Update in V2 with more information in commit log:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640863.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-12-18 18:59
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V
OK. LGTM. It's an obvious fix and not easy to add the test (No need to add such
test).
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-18 15:35
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Bugfix for the RVV const vector
From: Pan Li
check according to this suggestion.
Also, rename the test from const-vector-0.c into bug-7.c
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-18 15:04
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for the RVV const vector
From:
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-18 15:05
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] testsuite: Fix cpymem-1.c dump checks under different
riscv-sim for RVV.
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base
Could you add -fno-schedule-insns -fno-schedule-insns2 ?
So that the test won't be fragile to break a again when we tune the scheduling
model and cost model.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-18 14:40
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH
LGTM from my side.
Give kito 1 day to chime in,
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-18 11:28
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Add required_extensions in function_group
In order to add other vector related extensions
r_p && !vec_len.is_constant ())
return false;
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-15 20:44
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Fix vmerge optimization bug in vec_perm
vectorization
> Oh. I t
<< GET_MODE_BITSIZE (GET_MODE_INNER (vmode)));
if (GET_MODE_BITSIZE (GET_MODE_INNER (vmode)) == 8
&& indices_not_fit_selector_p
&& !vec_len.is_constant ())
return false;
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-15 20:25
To: juzhe.zh...@rivai.ai; gcc
ITSIZE (GET_MODE_INNER (vmode)) == 8、
&& indices_fit_selector_p
&& !vec_len.is_constant ())
return false;
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-15 20:25
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PAT
s but that will probably clash if there are more than
>>two npatterns.
No, we definitely can not use this. more details you can see the current test
vmerge-*.c .
We have various patterns:
E.g.
0, nunits + 1, nunits+ 2, ... it is 011
nunits, 1, 2 it 100.
....
Many different kinds of patte
CCing Kito.
I am sorry I can't review ABI even though it is vector related, this patch
needs kito's review.
But I will be available on reviewing the following real vector BF16 intrinsic
and auto-vectorization support.
Thanks.
juzhe.zh...@rivai.ai
From: Xiao Zeng
Date: 2023-12-15 09:22
Thanks Richard. Committed.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-12-14 23:10
To: Juzhe-Zhong
CC: gcc-patches; richard.sandiford
Subject: Re: [PATCH] Middle-end: Do not model address cost for SELECT_VL style
vectorization
On Thu, 14 Dec 2023, Juzhe-Zhong wrote:
> Fol
is better than COST=2.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-12-14 18:46
To: juzhe.zhong
CC: gcc-patches; richard.sandiford; jeffreyalaw
Subject: Re: [PATCH] Middle-end: Adjust decrement IV style partial
vectorization COST model
Am 14.12.2023 um 09:28 schrieb
ion is the COST should be 1 or 2.
It seems that COST = 1 is better for using SELECT_VL.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-12-13 18:17
To: Juzhe-Zhong
CC: gcc-patches; richard.sandiford; jeffreyalaw
Subject: Re: [PATCH] Middle-end: Adjust decrement IV style partial
APE, PREDS, OPS_INFO},
3. Recover all DEF_RVV_FUNCTION back to the original.
4. In the following vector crypto intrinsic, you should add like
DEF_RVV_CRYPTO_FUNCTION like aarch64 does for SME.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-13 21:00
To: juzhe.zh...@rivai.ai; gcc-patches
CC:
LGTM.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2023-12-13 19:12
To: gcc-patches@gcc.gnu.org
CC: juzhe.zh...@rivai.ai; pan2...@intel.com
Subject: [PATCH v2] RISC-V: Fix dynamic lmul tests depended on abi
Some toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file
-intrinsic v0.11)?
Intrinsics stuff should be very safe.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-12-13 18:09
To: Feng Wang
CC: gcc-patches; jeffreyalaw; juzhe.zhong; zhusonghe; panciyan
Subject: Re: [PATCH v2 1/4] RISC-V:Add crypto vector implied ISA info.
LGTM
On Wed, Dec 13, 2023 at 5:14
for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i)
if (avail)
builder.register_function_group (function_groups[i]);
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-13 17:12
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; zhusonghe; panciyan; Feng Wang
Subje
ot:
+ (match_operand: 4 "register_operand" " r, r, r, r")))
+ (match_operand:VI 2 "vector_merge_operand" "vu, vu, 0, 0")))]
+ "TARGET_ZVBB || TARGET_ZVKB"
+ "vandn.vx\t%0,%3,%4%p1"
+ [(set_attr "type" "v
disable multilib. */
#ifndef _RISCV_VECTOR_WRAP_H
#define _GCC_WRAP_STDINT_H
#include "stdint-gcc.h"
#include_next
#define _RISCV_VECTOR_WRAP_H
#endif
juzhe.zh...@rivai.ai
From: demin.han
Date: 2023-12-12 18:01
To: gcc-patches@gcc.gnu.org
CC: juzhe.zh...@rivai.ai; pan2...@intel.c
lgtm.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-12 16:28
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation
From: Pan Li
This patch would like to disable the avl propagation for the follow
reasons
Thanks Richard.
Committed with V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640172.html
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-12-11 20:12
To: juzhe.zhong\@rivai.ai
CC: Robin Dapp; gcc-patches
Subject: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA
else if (partial_subreg_p (use->mode (), mode))
use->set_mode (mode);
}
use->record_reference (ref, false);
}
Is it reasonable to you ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-12-11 19:45
To: juzhe.zhong\@rivai.ai
CC: Robin Dapp; g
. */
+
+static bool
+select_appropriate_lmul (HOST_WIDE_INT length_in,
+HOST_WIDE_INT _out)
+{
I don't think we need this, you only need to use TARGET_MAX_LMUL
juzhe.zh...@rivai.ai
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