eneficial we support high stride lane load/store
which can help us vectorize more cases.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-09 20:41
To: Juzhe-Zhong
CC: gcc-patches; jeffreyalaw
Subject: Re: [PATCH] RISC-V Regression test: Fix FAIL of fast-math-slp-38.c for
RVV
On Mon, 9
Thanks Robin. Could you send V3 to Richi ? And commit it if Richi is ok with
that.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-09 18:26
To: Andreas Schwab; juzhe.zhong
CC: rdapp.gcc; gcc-patches; rguenther; jeffreyalaw
Subject: Re: [PATCH V2] TEST: Fix vect_cond_arith_* dump checks
,
OPTAB_DIRECT);
For srl, you should use:
rtx tmp
= expand_binop (Pmode, lshiftrt_optab, op_1,
gen_int_mode (8, Pmode), NULL_RTX, 0,
OPTAB_DIRECT);
For or, you should use:
expand_binop (Pmode, ior_optab, tmp, dest, NULL_RTX, 0,
OPTAB_DIRECT);
juzhe.zh...@rivai.ai
Thanks Richi.
I will try to figure out a better way to adapt the tests without adding riscv*
specific targets variant.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-09 16:17
To: Juzhe-Zhong
CC: gcc-patches; jeffreyalaw
Subject: Re: [PATCH] TEST: Fix XPASS of outer loop
ict-align) is not appropriate, which means I
need additional compile option.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-09 16:01
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Support movmisalign of RVV VLA modes
Yes. We do have && enable char -> long conversion (vsext.vf8/vzext.vf8)
Thanks for the comment, I will adapt test as you suggested.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-09 15:31
To: Jeff Law
CC: Juzhe-Zhong; gcc-patches; richard.sandiford
Subject: Re: [PATCH
Hi, Richi and Robin.
Turns out COND(_LEN)?_ADD can't work.
Is this patch Ok ? Or do you have another solution to change the dump check for
RVV?
Thanks.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-08 09:33
To: gcc-patches
CC: rguenther; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject
Hi, Jeff.
Address your comments and fix on V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632239.html
I think it look reasonable good for a long term maintenance now.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-10-07 23:09
To: Juzhe-Zhong; gcc-patches
CC
Also I have reverted your commit:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=066a43ce72ab6559ba14af9628df19daa0b85cdf
Plz test the patch and verify it doesn't cause any FAILs if the toolchain
doesn't have "zvfh_zfh".
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-1
These testcases cause multiple FAILs:
I think you should
/* { dg-do run { target { riscv_v && riscv_zvfh_hw && riscv_zfh_ok } } } */
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-07 14:25
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-07 14:25
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add more run test for FP rounding autovec
From: Pan Li
For _Float16 types, add run test for:
* ceil
* floor
* nearbyint
* rint
OK.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-10-07 11:18
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Fix scan-assembler-times of RVV test case
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Adjust
"vect" {
target vect_strided5 && vect_load_lanes } } } */
Could you verify it whether it work for you ?
Thanks.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-10-06 22:29
To: Juzhe-Zhong; gcc-patches@gcc.gnu.org
CC: rguent...@suse.de; jeffreya...@gmail.com; richard.sandif...@arm.com
Plz add "!flag_trapping_math"
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-28 13:59
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support {U}INT64 to FP16 auto-vectorization
From: Pan Li
This patch would like to suppor
LGTM. Thanks for fixing it.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-28 09:33
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
From: xuli
Consider the flowing situation:
BB5: local_dem(RVV Insn 1, AVL(reg zero))
RVV
pattern.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-27 18:07
To: juzhe.zh...@rivai.ai
CC: kito.cheng; gcc-patches; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
I can understand why remove mem to mem pattern, but why the normal mov
>> Why add `can_create_pseudo_p ()` here? this will split after reload,
>> but we forbid that pattern between reload and split2?
I have no ideal. Some fortran tests just need recognization of mem-to-mem
pattern before RA.
I don't know the reason.
juzhe.zh...@rivai.ai
From: Kit
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-27 16:20
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP roundeven auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
roundeven API
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-27 11:28
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP trunc auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
trunc API in math.h
_vl (insn->rtl ()) : dem.get_avl ();
+ = (has_vl_op (insn->rtl ()) && REG_P (get_vl (insn->rtl (
+ ? get_vl (insn->rtl ())
+ : dem.get_avl ();
How about:
rtx avl = dem.get_avl_or_vl_reg ();
I wonder whether it is possible add a testcase for this issue ?
juzhe.zh...@riva
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-26 19:00
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP round auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
round API in math.h
Address comments：
V3
COND_LEN_ADD：https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631350.html
V2 COND_ADD:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631352.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-09-26 17:41
To: Juzhe-Zhong
CC: gcc
Hi, Richi.
Addresse comments.
One is V2 patch for COND_LEN_ADD reduction:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631340.html
The second one is optimize COND_ADD reduction:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631341.html
juzhe.zh...@rivai.ai
From
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-26 15:24
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP rint auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
rint API in math.h
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-26 15:19
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Support FP nearbyint auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
nearbyint API
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-26 11:12
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Rename rounding const fp function for refactor
From: Pan Li
The rounding related API shared one const, rename it to avoid
)
{
/* The floor needs the same floating point const as ceil. */
return gen_ceil_const_fp (inner_mode);
}
So rename it :
gen_ceil_const_fp (machine_mode inner_mode)
into:
get_fp_rounding_coefficient
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-26 10:39
To: gcc-patches
CC: juzhe.zhong; pan2.li
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 20:16
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Refine the code gen for ceil auto vectorization.
From: Pan Li
We vectorized below ceil code already.
void
test_ceil (float *out
I prefer change expand_vec_copysign into emit_vec_copysign。
Likewise， emit_fabs. ...etc.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 19:19
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Refine the code gen for ceil auto vectorization
ok
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 17:11
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Move ceil test cases to unop folder
From: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/math-ceil-0.c: Moved
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 11:39
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Remove arch and abi option for run test case.
From: Pan Li
Remove the -march and -mabi.
gcc/testsuite/ChangeLog:
* gcc.target
LGTM. You can commit it after you pass the regression.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-22 10:37
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH V2] RISC-V: Optimization of vrgather.vv into
vrgatherei16.vv[PR111451]
From: xuli
Consider
Sorry. It should be:
else if (CONST_VECTOR_P (sel)
&& GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)).to_constant () > 16
&& riscv_get_v_regno_alignment (data_mode) > 1)
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-09-22 09:39
To: Li Xu; gcc-patches
CC: kit
lmul == LMUL_8))
change it into:
else if (CONST_VECTOR_P (sel)
&& GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)).to_constant () > 16
&& riscv_get_v_regno_alignment (data_mode) > LMUL_1)
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-22 09:33
To: gcc-patches
CC: kito.cheng; pal
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 09:12
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Leverage __builtin_xx instead of math.h for test
From: Pan Li
The math.h may have problems in some environment, take __builtin__xx
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 08:12
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v4] RISC-V: Support ceil and ceilf auto-vectorization
From: Pan Li
Update in v4:
* Add test for _Float16.
* Remove unnecessary macro in def.h
Hi, Patrick.
GNU rvv intrinsic api test-generator has been merged:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/commits/main
Could you include the full RVV intrinsic API test in your test CI?
Currently, we don't include all API test in the GCC testsuite since it's too
big.
juzhe.zh
Also。 Remove math.h include。
Instead, plz use __builtin_ceil.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-21 18:32
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Support ceil and ceilf auto-vectorization
From: Pan Li
This patch would
operand")]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations
&& (flag_fp_int_builtin_inexact || !flag_trapping_math))
|| (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MAT
LGTM
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-21 11:44
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more
generic names
This little rename
Thanks a lot. LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-21 11:12
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Optimized for strided load/store with stride ==
element width[PR111450]
From: xuli
When stride == element width, vlsse should
Yes. We could wait for a more few days to backport.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-21 00:41
To: Juzhe-Zhong
CC: GCC Patches; Kito Cheng; Jeff Law; Robin Dapp
Subject: Re: [Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS]
Does it also happened on gcc 13 branch
reasonable.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-20 17:14
To: Lehua Ding; gcc-patches
CC: rdapp.gcc; juzhe.zhong; kito.cheng; palmer; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Support combine cond extend and reduce sum to
widen reduce sum
Hi Lehua,
I think this is better
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-20 15:03
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Reorganize and rename combine patterns in
autovec-opt.md
This patch reorganize and rename the combine patterns
t;VF" so that you could also support VLS CEIL.
Besides, I want to see this following case:
a[i] = cond[i] ? CEIL (b[i]): c[i];
Ideally, we should be able to combine vfcvt + vmerge into vfcvt with mask.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-20 10:30
To: gcc-patches
CC: juzhe.
/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -1,5 +1,4 @@
#include
-#include
and commit it.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-20 08:52
To: 钟居哲
CC: Patrick O'Neill; Robin Dapp; gcc-patches; Kito.cheng; jeffreyalaw; palmer;
Edwin Lu; joern.rennecke
I didn't see this issue.
They should be the bogus FAILs.
We should either fix testcases or ignore them.
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-09-20 08:34
To: Juzhe-Zhong; Robin Dapp; gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; Palmer Dabbelt; Edwin Lu;
joern.rennecke
ve (dest, XEXP (XEXP (src, 0), 0));
+ riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (XEXP (src, 0),
1));
If it can fix your issue, plz send a patch and commit it.
Thanks.
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-09-19 01:38
To: Li, Pan2; Kito Cheng
CC: gcc-pat
Thanks for the refactoring.
This patch is needed in VLS fma support and undefined value enabling support.
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-18 19:37
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V
Sorry for I made a mistake here.
Change 'mayb_lt' into '!ordered_p' in V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630835.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-09-19 10:25
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
LGTM
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-18 20:29
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Removed misleading comments in testcases
This patch removed the misleading comments in testcases since we
support
LGTM。
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-18 20:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Add fixed PR111255 testcase by other patch
This patch add the missed PR111255 testcase which is fixed
Thanks Richard.
Address comments on V3:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630699.html
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-09-17 23:29
To: Juzhe-Zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V2] internal-fn: Support undefined rtx
Thanks for fixing it.
I am ok remove phase 6 optimization which has many latent bugs (in GCC 14 kito
has refactored it) there.
But I think we need kito's more comments about that.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-18 12:19
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
of the function_instance.
Then we can get the non-overloaeded function.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-09-15 10:02
To: pan2.li; gcc-patches
CC: pan2.li; yanzhang.wang; kito.cheng
Subject: Re: [PATCH v3] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV
intrinsic
Sorry
es::alu
should already known since it is a known function_base.
The last 3 arguments may need some elegant analysis or map table to quickly
grep.
So, I think we should consider this framework seriously.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-12 16:46
To: gcc-patches
CC: juzhe.z
}
return true;
}
ASM:
vsetivli zero,2,e32,mf2,ta,ma
vslidedown.vi v2,v1,1
vmv.x.s a5,v2
slli a5,a5,32
vmv.x.s a0,v1
or a0,a5,a0
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 17:26
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PA
../../../../gcc/gcc/cfgexpand.cc:4044
0x10699f3 expand_gimple_basic_block
Thanks for catching this.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 17:20
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode
You mean try pr111391.c
that I added with rv64gcv_zve32x ?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 17:20
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode
move[PR111391]
Could you
Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in
vec_extract optab ?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 16:11
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar
index);
+ expand_insn (icode, 3, ops);
This code is copied from optabs-query.cc
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 16:11
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]
On Th
Just realize this patch cause some unexpected ICE FAILs in GCC regression.
Now, V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630194.html
has fully passed the regression.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-09-13 21:01
To: gcc-patches
CC: kito.cheng
>> Do we need the additional helper function?
Yes. We need the additional helper function since I will cal emit_insn
(gen_vec_extract (mode, mode)
in the following patch which fixes PR111391 ICE.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-13 20:31
To: Juzhe-Zhong; gcc-patc
+ cond_len_fma -> cond_len_fnma/cond_len_fms/cond_len_fnms.
That's what I want to support in gimple fold.
Let's see more comments from Richard and Richi.
juzhe.zh...@rivai.ai
Ok add it in V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630048.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 21:29
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support VECTOR BOOL vcond_mask
Then you don't need to waste time on reduce the case from SPEC.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-09-12 17:36
To: Robin Dapp; gcc-patches
CC: Robin Dapp; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: Re: [PATCH V4] RISC-V: Support Dynamic LMUL Cost model
testsuite (I belive we can reproduce with some case in GCC testsuite in the
future).
Is that reasonable ? If yes, I will fix all your comments and send V5.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 17:31
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng
ree lhs = gimple_get_lhs (stmt);
mode = TYPE_MODE (TREE_TYPE (lhs));
If it is not a STORE, I assume it always has a LHS. Turns out that my original
thought is incorrect.
I think I know the fix.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 17:17
To: Juzhe-Zhong;
Thanks Robin.
I have tried your codes. It works fine and tests passes.
Does your code O(nlogn) complexity ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 16:19
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH V4] RISC-V: Support
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-12 16:57
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Add missed cond autovec testcases
This patch adds all missed cond autovec testcases. For not support
cond
It looks reasonable to me now.
But let's wait for kito's more comments.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-12 16:46
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v3] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV
intrinsic
From: Pan
intrinsic api ci with this patch?
I am worrying that the resolve stuff will destroy the existing APi support.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-12 15:20
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Implement
}
}
Could you revise this piece of codes ?
Other comments has been addressed in V4:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629959.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 04:31
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; j
Thanks for support it.
LGTM from my side.
Wait for kito's more comments.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-12 10:08
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; pan2.li; gaofei; wangfeng; xuli
Subject: [PATCH] RISC-V: Add vcreate intrinsics for RVV tuple types
From: xuli
Add a function call get_non_overloaded_instance into instance.
The instance already know it is void vmv (void).
In this function search the arglist. and return the real non-overloaded decl.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-09-12 09:20
To: 钟居哲
CC: kito.cheng; gcc-patches; Wang
>> What about one test with global live ranges? Not a necessity IMHO we can
>> still
>> add it later.
We already have.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 04:31
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re:
shape, mode, types, pred);
registered_function *rfn
= function_table->find_with_hash (instance, instance.hash ());
return rfn ? rfn->decl : NULL_TREE;
}
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-11 17:04
To: juzhe.zh...@rivai.ai
CC: pan2.li; gcc-patches; yanzhang.wang
Subject: Re
Thanks for supporting it even though I don't like this feature :).
The framework is LGTM.
Let's wait for kito's more comments.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-11 15:57
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Implement
Committed. Thanks kito.
>> I guess you will remove get_all_predecessors once LMUL cost
>> model can use dominator info as well?
Yes. I am trying but there is a failed case for dynamic LMUL.
Not sure whether it can work now.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023
ADDRESS\n" 1
FAIL: gcc.dg/tree-ssa/split-path-11.c scan-tree-dump-times split-paths "join
point for if-convertable half-diamond" 1
These are bogus dump FAILs and I have 100% confirm each of them, we are having
same behavior as SVE.
So is this patch ok for trunk ?
juzhe.zh...@rivai.ai
Sure. Thanks kito.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-11 10:57
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Add VLS modes VEC_PERM support[PR111311]
OK, but could you split this patch into two patches? pre-approved for both.
On Mon
de),
insn_flags, operands, operands[2]);
}
DONE;
}
[(set_attr "type" "vmov")]
)
We split special case use emit_insn (gen_rtx_SET (operands[0], operands[1]));
Missing this pattern will cause ICE but current testcases didn't produce such
issues.
This issue is reco
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-05 18:32
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP SGNJ autovec for VLS mode
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary
simple patch for dynamic cost model:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629212.html
committed.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-09-04 17:08
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix
Ok for trunk. But not sure whether it's ok for GCC-13.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-08-30 17:51
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
This patch fix pr111234 (a vsetvl pass ICE) when fuse
Ping. This patch also fixed issue occurred in RISC-V backend:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71
Thanks.
juzhe.zh...@rivai.ai
>> Juzhe mentioned he doesn't want to commit this before
>> all/most bugs are addresses anyway, right?
Yes.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-28 22:27
To: Kito Cheng; Juzhe-Zhong
CC: rdapp.gcc; gcc-patches; kito.cheng
Subject: Re: [PATCH V4] RISC-V: Enable vec_i
Ok.
It reduced some failures, and new report is updated on the commit log in V4:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628580.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-28 18:29
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Ok. Add -Wno-psabi which reduce 5 FAILS.
V3:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628572.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-28 16:22
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Enable
Address comments:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628568.html
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-08-28 16:58
To: Robin Dapp
CC: Juzhe-Zhong; gcc-patches; kito.cheng
Subject: Re: [PATCH] RISC-V: Disable user vsetvl fusion into EMPTY block
Is it possible
the top, we will be missing fuse user vsetvl (in bb 3 e32 m1)
into user vsetvl (in bb 2 e8 mf4).
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-08-28 16:58
To: Robin Dapp
CC: Juzhe-Zhong; gcc-patches; kito.cheng
Subject: Re: [PATCH] RISC-V: Disable user vsetvl fusion into EMPTY block
Is
Address comment:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628546.html
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-08-28 11:48
To: Juzhe-Zhong
CC: gcc-patches; lehua.ding; kito.cheng
Subject: Re: [PATCH] RISC-V: Enable vec_init testsuite for RVV VLA vectorization
Thanks for taking care of this issue.
Ok to backport GCC-13.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-08-28 10:33
To: xuli1; gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: Re: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
instructions satisfying REG_P(operand[1
Ok.
I am not familiar with scheduling stuff but I hope you can fix those 2 issues.
I have no objection with this patch and I prefer Jeff or kito make the decision
for this patch.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-23 22:56
To: 钟居哲; gcc-patches; palmer; kito.cheng
Thanks kito.
Address all comments and committed with V3:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628423.html
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-08-25 01:01
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V2] RISC-V: Refactor
,e8,mf8,ta,ma
addi a5,a5,1
vle8.v v1,0(a6)
vse8.v v1,0(a4)
addi a0,a0,4
addi a1,a1,4
beq a2,a5,.L10
.L5:
addi a4,a1,-1200
addi a6,a0,-1200
bltu a3,a5,.L12
vsetvli t1,zero,e8,m8,ta,ma
addi a5,a5,1
vlm.v v1,0(a0)
vsm.v v1,0(a1)
addi a0,a0,4
addi a1,a1,4
bne a2,a5,.L5
.L10:
ret
juzhe.zh...@rivai.ai
h a separate patch.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-08-22 23:35
To: Kito Cheng
CC: Robin Dapp; Juzhe-Zhong; GCC Patches; Jeff Law
Subject: Re: [PATCH] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS
It's really great improvement, it's drop some state lik
eil, floor,
etc.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-22 15:33
To: juzhe.zhong; Andrew Pinski
CC: rdapp.gcc; Lehua Ding; gcc-patches@gcc.gnu.org; kito.ch...@gmail.com;
pal...@rivosinc.com; jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V: Add conditional unary neg/ab
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-08-22 11:02
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Change fnms testcases assertion to xfail
Hi,
This patch fixes inappropriate assertions in fnms testcases since
we want
report this.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-08-21 22:16
To: Juzhe-Zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH] gimple_fold: Support
COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS gimple fold
Juzhe-Zhong writes:
> Hi, Richard and Richi.
>
> Current
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