The implementation is copied directly from ARM SVE.
I applied in my downstream GCC for a year and there is no issue so far.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-13 19:44
To: gcc-patches
CC: kito.cheng; palmer; rdapp.gcc; jeffreyalaw; Juzhe-Zhong
Subject: [PATCH
vec_init is auto-vectorization pattern.
The test is not loop since using vector type is easier to test the patterns.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-12 16:53
To: Li, Pan2; Kito Cheng; juzhe.zh...@rivai.ai
CC: gcc-patches@gcc.gnu.org; pal...@dabbelt.com; jeffreya
sending patch for GCC
to make sure
the implementation is correct.
The slidedown method is totally the same as LLVM.
Sorry about that, I won't send any information related to LLVM gain. Thanks :)
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-12 10:23
To: juzhe.zhong
CC: gcc-patches
This patch has tested on both RV32/RV64, and all fails in RVV are cleaned up.
Ok for trunk?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-12 07:29
To: gcc-patches
CC: kito.cheng; palmer; jeffreyalaw; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix RVV binary auto-vectorizaiton test fails
From
->max_nscalarper_iter != 1
Case 3 : rgc->max_nscalarper_iter == 1 but rgc->factor != 1?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-11 19:29
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V4] VECT: Add decrement IV iteration loop control by
variab
Oh, I see. But I saw there is a variable using_partial_vectors_p
in the loop data structure.
Can I add a variable call using_select_vl_p ?
Since it may increase the size of data structure, I am not sure whether it is
appropriate.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date
I just saw Kito has LGTM in V1 patch.
Let's wait for Kito LGTM for V2.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:36
To: juzhe.zh...@rivai.ai; gcc-patches; kito.cheng; collison; palmer; jeffreyalaw
Subject: Re: [PATCH v2] RISC-V: Add vectorized binops and insn_expander helpers
LGTM. You should commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:26
To: 钟居哲; gcc-patches; kito.cheng; Michael Collison; palmer; Jeff Law
CC: rdapp.gcc
Subject: [PATCH v2] RISC-V: Add vectorized binops and insn_expander helpers
LGTM. Plz commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:33
To: Palmer Dabbelt
CC: gcc-patches; juzhe.zhong; Kito Cheng; collison; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Split off shift patterns for autovectorization
LGTM. Plz commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:29
To: Kito Cheng; Palmer Dabbelt
CC: gcc-patches; juzhe.zhong; collison; jeffreyalaw
Subject: [PATCH v2] RISC-V: Clarify vlmax and length handling.
Changes from v1:
- Change
LGTM. Plz commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:27
To: Kito Cheng; Palmer Dabbelt
CC: gcc-patches; juzhe.zhong; collison; jeffreyalaw
Subject: [PATCH v2] RISC-V: Add autovectorization tests for binary integer,
operations
ns it is Case 2 or Case 3. We
always force MIN_EXPR using VF in non-final iteration.So the data reference IV
is added by constant value (poly or non-poly). Maybe the codes here is ugly
with using loop_lens->length () == 1?Could you give me the suggestions for this?
I am gonna fix this patch by
OK, thanks for Richard Sandiford.
Waiting for Richard Biener comment before commit.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-11 16:14
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V5] VECT: Add tree_code into "creat_iv" and allow it can
handle
Thank you so much.
Can you take a look at this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618110.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-11 12:50
To: 钟居哲
CC: gcc-patches; rguenther
Subject: Re: [PATCH V4] VECT: Add decrement IV iteration loop
LGTM.
The whole implementation is your own work, but tests are mostly base on Michael
so add Michael as co-author in testcase patch and then commit.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-10 23:24
To: gcc-patches; juzhe.zh...@rivai.ai; Kito Cheng; Michael Collison; palmer
This part LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-10 23:24
To: gcc-patches; juzhe.zh...@rivai.ai; Kito Cheng; Michael Collison; palmer;
jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] riscv: Clarify vlmax and length handling.
Hi,
this patch tries to improve the wrappers
LGTM. Let's wait for kito's feedback.
Thanks :)
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-05-10 12:02
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
instructions satisfying REG_P(operand[1]) in -O0
re each file has a newline at the end of file.
After these change, it LGTM.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-05-10 10:18
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
instructions satisfyin
implementation are in the isolated
function "vect_set_loop_controls_by_select_vl",
it's easier to review the implementation.
Maybe we can first make the whole implementation codes in
"vect_set_loop_controls_by_select_vl" to be stable after review,
then we can try to incorporate these codes of
"vect_set_l
Hi，Richards. Would you mind reviewing this patch?
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-05-07 23:19
To: juzhe.zhong; gcc-patches
CC: richard.sandiford; rguenther
Subject: Re: [PATCH V4] VECT: Add decrement IV iteration loop control by
variable amount support
On 5/4/23 07
in to incorporate those
codes into "vect_set_loop_controls_directly" when they
finish the review process of "vect_set_loop_controls_by_select_vl".
Thanks.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-05-08 15:55
To: juzhe.zh...@rivai.ai
CC: gcc-patches; rguenther; richard.sandiford
Subject: Re
r wants to degenerate select_vl to min, it can
>>just adopt the same
>>handlings with min by not defining select_vl optab.
You mean like this:
doing this inside vect_set_loop_controls_directly ?
if (use_while_len_p)
return vect_set_loop_controls_by_while_len (...)
T
Gentle ping this patch.
Is this Ok for trunk? Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-06 19:14
To: gcc-patches
CC: kito.cheng; Juzhe-Zhong
Subject: [PATCH] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli
[PR 109743]
From: Juzhe-Zhong
This patch
Yeah, you should also swap mode and code in rtx_def according to Richard
suggestion
since it will not change the rtx_def data structure.
I think the only problem is the mode in tree data structure.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-06 09:53
To: Li, Pan2
CC: Richard Biener
I have sent V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617504.html
adding more comments.
Is that OK?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-05 14:21
To: juzhe.zhong
CC: gcc-patches; palmer; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Fix PR109615
Could you
vluxei32.v v1,(0),v1 is not correct assembly.
Instead, it should be vluxei32.v v1,(zero),v1
You should change the assembly print: (%1) --> (%z1)
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-05-04 16:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subj
atch more? Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-04-29 00:10
To: gcc-patches; Kito Cheng; Kito.cheng; palmer; juzhe.zh...@rivai.ai; Michael
Collison; jeffreyalaw
Subject: [PATCH] riscv: Allow vector constants in riscv_const_insns.
Hi,
I figured I'm going to start sending som
to implement VEC_PACK_TRUNC to
test your idea.
Thanks
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-26 17:06
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH] VECT: Add decrement IV iteration loop control by variable
amount support
"juzhe.zh...@rivai.
t;controls.is_empty ()
&& vect_maybe_permute_loop_masks (_seq, rgc, half_rgc))
continue;
}
Is that correct?
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-04-26 16:55
To: richard.sandiford
CC: gcc-patches; rguenther
Subject: Re: Re: [PATCH] VECT: Add decrement IV iteration loop
vect__7.10_33 = VEC_PACK_TRUNC_EXPR ;
...
.LEN_STORE (_13, 16B, X, vect__7.10_33); (INT16)
Is this correct ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-26 16:06
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH] VECT: Add decrement IV iteration
ould need to be updated,
>>but IMO that's OK. Not sure what others think though.
>>The patch doesn't seem to change vect_estimate_min_profitable_iters though,
>>so the comment doesn't seem accurate.
Address all comments and fix patch V3:
https://gcc.gnu.org/pipermail/gcc-patches
/4/8 so far.
Then we can support the feature of picking LMUL during auto-vectorization in
the future when we figure out how to do that.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-25 14:00
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Add RVV auto
I can push codes yet. Can you push them for me?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-22 04:42
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx
codegen
On 3/22/23 06:15, juzhe.zh...@rivai.ai wrote
.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-22 04:36
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Fine tune gather load RA constraint
On 3/13/23 02:28, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> For DEST EEW < SOURCE EEW, we can par
LGTM。
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-04-21 14:49
To: gcc-patches
CC: Juzhe-Zhong
Subject: [committed v2] RISC-V: Add local user vsetvl instruction elimination
[PR109547]
From: Juzhe-Zhong
This patch is to enhance optimization for auto-vectorization.
Before this patch
function.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-20 17:54
To: Richard Biener
CC: juzhe.zhong\@rivai.ai; gcc-patches; jeffreyalaw
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
Richard Biener writes:
> On Thu, 20 Apr 20
L = 1/2/4/8 auto-vectorization (You can see the codes in rvv.exp).
Then, he let me add --param options.
I can change compile option as you suggested.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-04-20 17:42
To: juzhe.zh...@rivai.ai; kito.cheng
CC: gcc-patches; palmer; jeffreyalaw
Subje
Ahhh. Thanks kito.
Can you give more comments about Robin's opinion that he want to change into
"fixed" vs "varying" or "fixed vector size" vs "dynamic vector size" ?
I am Ok with any of them.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-04-20
ot;WHILE_LEN" pattern.
Overall the global reviewers accept our RVV loop control mechanism in
middle-end,
I am going to support RVV loop control mechanism in middle-end first. Then, we
can
have perfect codegen like RVV ISA example soon.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date:
date patch.
Is that right? Feel free to correct me.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-20 17:11
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther; jeffreyalaw
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
r, it was objected by LLVM
community.
https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/33
I think in case of compile options, Kito may give more comments since he is the
RISC-V ABI and convention maintainer.
I develop this patch following his order.
Thanks.
juzhe.zh...@riv
Thanks Richard reminding me. I originally think community does not allow me
support variable amount IV and let me do this in RISC-V backend.
It seems that I can do that in middle-end. Thank you so much. I will update the
patch. Really appreciate it!
juzhe.zh...@rivai.ai
From: Richard
vv/base/spill-10.c":28:1
>>727 {*movvnx8qi_whole}
>>(nil))
Oh, I see. According to your situation, the LMUL = 1 is 128bit. VNx8QImode is
MF2 which is 64bit size.
GCC tie VNx8QI into a scalar register. I think it can be easily fixed in the
backend but yes, I agree with you
= get_tail_policy_no_pred();
+ rtx mask = CONSTM1_RTX(mode);
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
These operands preparation codes should be added into a wrapper.
How to add a wrapper, you can reference "emit_nonvlmax_op" , "emit_pred_op"...
functions.
Thanks.
juzhe.z
ook at "preferred_simd_mode" function.
And also, I have a bunch of -march combinations of testcase, make sure compiler
will not auto-vectorize the codes
if we don't want it:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616224.html
juzhe.zh...@rivai.ai
From: Michael Collison
ave sent the patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616223.html to initial
basic auto-vectorization.
juzhe.zh...@rivai.ai
From: Michael Collison
Date: 2023-04-18 02:36
To: gcc-patches
Subject: [PATCH v4 04/10] RISC-V:autovec: Add target vectorization hooks
2023-03-02
Thanks Jeff.
Address Jeff's comment and resend fix patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616170.html
This patch also added a testcase coming from Kito (Kito reduced google/highway
testcase from over 10W lines codes into 100 lines codes!!!).
juzhe.zh...@rivai.ai
From
).
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-04-19 17:34
To: Li, Pan2
CC: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang,
Yanzhang
Subject: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Hi Pan:
>rtx expand (function_expan
ee "vl" operand only serves as "avl" which is used already
in vsetvli instructions before, so this operand is not used anymore in
"vadd.vx" instruction,
I removed this operand and dependency.
Feel free to give me more comments. Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
mind giving me more suggestions?
Thanks
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-19 09:11
To: juzhe.zh...@rivai.ai; kito.cheng; Richard Biener
CC: gcc-patches; palmer
Subject: Re: [PATCH] RISC-V: Fix bug reported by PR109535
On 4/18/23 19:04, juzhe.zh...@rivai.ai wrote:
> The b
(reg:DI s0) then file
assertion in RTL_SSA.
Instead, we should not eliminate "s0" dependency.
Thanks
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-19 08:56
To: Kito Cheng; juzhe.zhong; Richard Biener
CC: gcc-patches; palmer
Subject: Re: [PATCH] RISC-V: Fix bug reported by PR109535
On
with length
>> exploitation since
>> the existing vector with length support already works well on functionality.
Ok, I get your point. I am gonna refine the patch to make it work for both RVV
and IBM.
Thanks all your comments.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-04
can switch to this flow ?
Is it more reasonable ?
Thanks.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-04-14 10:54
To: 钟居哲
CC: gcc-patches; Jeff Law; rdapp; richard.sandiford; rguenther
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
Hi Juzhe,
on 2023/
cept of this patch?
Would you mind giving more suggestions that I can fix this patch to make more
benefits for IBM (s390 or rs6000)?
For example, will you try this patch to see whether it can work for IBM in case
of multiple rgroup of SLP?
Thanks.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2
LGTM. Wait for Kito more comments.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-04-14 10:45
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; pan2.li
Subject: [PATCH v2] RISC-V: Add test cases for the RVV mask insn shortcut.
From: Pan Li
There are sorts of shortcut codegen
\s+v[0-9]+,\s*v[0-9]+} } } */
It's better add more assembler check
check how many vmclr.m or vmset.m should be.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-04-14 10:32
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; pan2.li
Subject: [PATCH] RISC-V: Add test cases for the RVV mask
ulator generate "vl" = VLMAX. (Sorry about that)
Expecting any suggestions and comments.
Thank you so much.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-04-13 14:47
To: 钟居哲
CC: richard.sandiford; gcc-patches; Jeff Law; rdapp; linkw; kito.cheng
Subject: Re: Re: [PATCH] VECT: Ad
ing.
I think I must missed something, would you mind giving me some hints so that I
can study on ivopts
to find out which case may generate inferior codegens for varialble IV step?
Thank you so much.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-12 19:17
To: Richard Biener
CC: juz
Sorry for incorrect typo.We can predicate vadd.vv with v1 - v31.
>
We can't predicate vadd.vv with v1 - v31.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-04-12 17:15
To: rguenther
CC: richard.sandiford; gcc-patches; jeffreyalaw
Subject: Re: Re: [PATCH] VECT: Add WHILE_
parison)
I think we can CC IBM folks to see whether we can make WHILE_LEN works
for both IBM and RVV ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-04-12 16:42
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; gcc-patches; jeffreyalaw
Subject: Re: Re: [PATCH] VECT: Add WHILE_
egister to predicate RVV operation
vle32.v v25,(a1),v0.t
vadd.vv v24,v24,v25
vse32.v v24,(a0),v0.t
add a2,a2,a4
add a0,a0,a4
add a1,a1,a4
bne a3,zero,.L3
.L1:
ret
This is the how RVV works.
Feel free to comment if you h
Hi, Richards.
Kindly Ping this patch.
This is the most important patch for RVV auto-vectorization support.
Bootstraped on X86 has passed.
Feel free to comments.
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-04-07 09:47
To: gcc-patches
CC: richard.sandiford; rguenther
gh.
Some instructions like comparison instructions, they don't care about tail
policy
Some instructions like vmv.x.s, doesn't care about VL.
etc.
Quite complicated, so we have defined several fusion rules in VSETVL PASS
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-04-1
9 bit (512 modes) mode should be enough for RVV.
In the future, I would expect we will have BF16 vector, FP16 vector,.. matrix
modes.
And I think it will not be more 512 modes in the future.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-11 19:11
To: Richard Biener
CC
rand 0)
(set dest operand 1)
(set dest operand 2)...])
...
NF = 7:
define_insn "vlseg7"
[(parallel_with_continguous_reg
(set dest operand 0)
(set dest operand 1)
(set dest operand 2)
(set dest operand 2)
(set dest operand 2)...])
juzhe.zh...@rivai.ai
From: Jakub Jel
it?
Thanks for all comments.
juzhe.zh...@rivai.ai
From: Jakub Jelinek
Date: 2023-04-11 17:59
To: juzhe.zhong; Jeff Law; gcc-patches; kito.cheng; palmer; rguenther;
richard.sandiford
Subject: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to
16-bit
On Tue, Apr 11, 2023 at 10:46
ot;vint8mf8x3_t", I don't known
how to define such instruction RTL pattern. Should its dest operand mode be
BLKmode?
But we want the dest operand is a register operand.
juzhe.zh...@rivai.ai
From: Jakub Jelinek
Date: 2023-04-11 17:16
To: juzhe.zhong
CC: Jeff Law; gcc-patches; kito.cheng; pal
sion generate a new vsetvl instructions "vsetvl e8,mf8,TU"
which is available for both RVV instructions "vadd" and "vle",
and update the first vsetvl "vsetvl e8,mf8,TA" to "vsetvl e8,mf8,TU"
Then, I tell LCM "vsetvl e8,mf8,TU" is available
Hi, I have checked SDnode in LLVM which is a similiar data structure with RTX
in GCC.
The SDnode in LLVM occupy 80bytes.
Can we have some tool to test the memory consuming of the whole GCC with
extended-size RTX?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-11 04:42
To: juzhe.zhong
Address all comments, and fix all of them in these splitted patches:
These 5 patches only including RISC-V port changes:
https://patchwork.sourceware.org/project/gcc/patch/20230407011143.46004-1-juzhe.zh...@rivai.ai/
https://patchwork.sourceware.org/project/gcc/patch/20230407012129.63142-1
riscv_vector {
+extern HARD_REG_SET riscv_zero_call_used_regs (HARD_REG_SET);
+}
namespace riscv_vector should be put in the riscv-protos.h. Since there is
already a riscv_vector namespace there.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2023-04-06 21:34
To: gcc-patches
CC: juzhe.zhong
.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-03 12:13
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Fix SEW64 of vrsub.vx runtime fail in RV32 system
On 4/2/23 18:38, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> It's quite obvious that
Thanks Richard && Pan.
Pan has passed the bootstrap and I will merge this patch when GCC 14 is open (I
have write access now).
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-03-29 17:24
To: pan2.li
CC: gcc-patches; juzhe.zhong; kito.cheng; yanzhang.wang
Subject: Re: [PATCH v2
would you mind looking at this
issue?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108016
Thanks.
juzhe.zh...@rivai.ai
would you mind looking at this
issue?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108016
Thanks.
juzhe.zh...@rivai.ai
RVV auto-vectorization. I think we can have a sync up meeting
(share my current new ideas) before I start to support RVV auto-vectorization
before GCC 14.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2023-03-18 00:57
To: gcc-patches; Vineet Gupta
CC: Kito Cheng; collison; juzhe.zhong; gcc
The last patch. Kito is still keep testing with pressure tests.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-03-20 01:03
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Fix bugs of ternary integer and floating-point
ternary intrinsics.
On 3/15/23 00:37
It's ok to defer them GCC-14. I will keep testing and fix bugs during these 2
months.
I won't support any more feature or optimizations until GCC-14 is open.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-03-20 00:55
To: juzhe.zh...@rivai.ai; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH
nt to make it into GCC-13.
More patches I am gonna to send are going to expected to be merged into GCC-14.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-03-15 02:08
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Fine tune gather load RA constraint
On 3/1
commit patch for me.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-03-15 02:13
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Fix Bug 109092
On 3/13/23 08:17, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> This patch fix bug: https://gcc.gnu.org
Thank you for fixing this. I am not familiar with this.
This generator code (genrvv-type-indexer.cc) is written by @kito.
Kito ? Can you take a look at this?
juzhe.zh...@rivai.ai
From: Sam James
Date: 2023-03-14 08:23
To: gcc-patches
CC: Kito Cheng; Palmer Dabbelt; Andrew Waterman; Jim
y (1,1) size.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-02 17:39
To: juzhe.zhong\@rivai.ai
CC: rguenther; pan2.li; gcc-patches; incarnation.p.lee; Kito.cheng
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Thanks for the explanation about the sizes.
Fortunately, we won't have aggregates, arrays of vbool*_t in the future.
I think it's not an issue.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-03-02 16:25
To: juzhe.zhong
CC: richard.sandiford; pan2.li; gcc-patches; Pan Li; kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv
?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-01 20:03
To: 盼 李 via Gcc-patches
CC: 盼 李; juzhe.zhong\@rivai.ai; pan2.li; Kito.cheng; rguenther
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
盼 李 via Gcc-patches writes:
> Just have a t
, 4/8 byte, 1/8 bytes. I think we can't
access in bit alignment. so they will the same in the access.
However, if VNx8BI occupty 8 byte, Well, VNx2BI,VN4BI, VNx1BI are 1byte,
2bytes, 4bytes. They are accessing different size.
This is my comprehension of RVV ISA, feel free to correct me.
Thanks.
he precision btw.
>
> Richard.
>
> > Thanks.
> > Replied Message
> > From
> > incarnation.p@outlook.com
> > Date
> > 02/16/2023 23:12
> > To
> > gcc-patches@gcc.gnu.org
> > Cc
> > juzhe.zh...@rivai.ai,
> > kito.ch...@sifi
VL PASS) of RVV now.
Now, I am pulling as many resources as possible to do the testing.
From now to April (until GCC 14 is open), I will only keep testing and fix bugs
or some codes refine && simplification.
I won't push any more features especially autovec until GCC 14 is open.
juzhe.zh..
the mature and better test-generator (much better than mine)
to commit since rvv-intrinsic doc is their work.
As long as we can make kito's test-generator embedded into GCC regression, this
issue will be fixed. And I believe we can fix it soon.
So...Let's wait for kito.
juzhe.zh...@rivai.ai
From
is
quite huge and not easy to maintain.
So.. I think I can reduce the tests into 1/3 of them in the next. But it's
still very big (you can take a look at LLVM).
Let's see whether kito has more comments about it.
juzhe.zh...@rivai.ai
From: Jakub Jelinek
Date: 2023-02-16 17:38
To: juzhe.zhong
mpile-time unknown)
vsm.v v8,a2
(Note: both vlm.v are loading same address)
Such asm will not happen in GCC. It will become like this since bool modes are
tied:
vsetvl e8,mf8
vlm.v v8, a0 (v8 is a N x 1-bit mask, N is compile-time unknown))
vsm.v v8,a0
vsm.v v8,a1
Such asm codegen is incorre
: both vlm.v are loading same address)
Such asm will not happen in GCC. It will become like this since bool modes are
tied:
vsetvl e8,mf8
vlm.v v8, a0 (v8 is a 8-bit mask)
vsm.v v8,a0
vsm.v v8,a1
I am not sure whether it's correct. Maybe I should ask RVV ISA community.
juzhe.zh...@rivai.ai
but byteszie are all same.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-02-13 17:41
To: Richard Biener
CC: juzhe.zhong\@rivai.ai; incarnation.p.lee; gcc-patches; Kito.cheng; ams
Subject: Re: [PATCH] RISC-V: Bugfix for mode tieable of the rvv bool types
Richard Biener writes:
> On M
I am not sure changing the precision inner mode of BImode is correct for RVV.
Since by definition , each single 1-bit mask in RVV mask layout are consecutive.
Maybe we can wait for Kito answer this question ?
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-02-13 16:46
To: juzhe.zh
VNx8BI (vbool8_t ) in VNx4BI (vbool16_t ).
In this example, GCC thinks data loaded for vbool8_t v3 can be replaced by
vbool16_t v4 which is already loaded
It's incorrect for RVV.
Maybe @kito can give us more information about RVV ISA if I don't explain it
clearly.
juzhe.zh...@rivai.ai
From: R
Sorry for the wrong title, it should be add vwsubu.wv C API tests
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-02-07 14:17
To: gcc-patches
CC: kito.cheng; Ju-Zhe Zhong
Subject: [PATCH] RISC-V: Add vwsubu.wx C API tests
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target
Thank you so much. Kito helped me fix it already.
RVV instruction patterns can have CSE optimizations now.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-02-02 20:26
To: juzhe.zh...@rivai.ai
CC: gcc-patches; kito.cheng; richard.sandiford; jeffreyalaw; apinski
Subject: Re: Re: [PATCH
VL_REGNUM] = NO_REGS;
riscv_regno_to_class [VTYPE_RENUM] = NO_REGS;
The CSE now can do the optimization now!
1) Would you mind telling me the difference between them?
2) If I set these 2 global status register as NO_REGS, will it create issues
for the global status configuration of each RVV instruc
m not sure
whether CSE can propagate the 151 pseudo
to the second pred_add ??
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-02-01 20:51
To: juzhe.zh...@rivai.ai
CC: gcc-patches; kito.cheng; richard.sandiford; jeffreyalaw; apinski
Subject: Re: Re: [PATCH] CPROP: Allow cprop optimization
PROP remove the second the "pred_broadcast" instruction and
propagate the result to the second "pred_add" instruction。
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-02-01 20:40
To: Ju-Zhe Zhong
CC: gcc-patches; kito.cheng; richard.sandiford; jeffreyalaw; apinski
Subject: R
In case of RVV intrinsic support, there is no changes outside RISC-V backend
since we don't do the autovectorization support for now.
I will postpone autovectorization until GCC14 is open.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2022-11-29 10:56
To: juzhe.zhong
CC: Kito Cheng
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