Bernd Schmidt ber...@codesourcery.com writes:
On 09/14/11 11:03, Richard Sandiford wrote:
...I didn't see from an admittedly quick read of the patch how you
handle memory disambiguation between iterations. If a loop includes:
lb $3,($4)
sb $5,1($4)
then the two instructions
On 10/03/11 10:23, Richard Sandiford wrote:
Bernd Schmidt ber...@codesourcery.com writes:
On 09/14/11 11:03, Richard Sandiford wrote:
...I didn't see from an admittedly quick read of the patch how you
handle memory disambiguation between iterations. If a loop includes:
lb $3,($4)
Bernd Schmidt bernds_...@t-online.de writes:
On 10/03/11 10:23, Richard Sandiford wrote:
Bernd Schmidt ber...@codesourcery.com writes:
On 09/14/11 11:03, Richard Sandiford wrote:
...I didn't see from an admittedly quick read of the patch how you
handle memory disambiguation between
On 10/03/11 16:21, Richard Sandiford wrote:
so inter-iteration dependencies aren't a problem. Whereas I thought your
modulo instruction did:
A1
B1 A2
C1 B2 A3
D1 C2 B3
D2 C3
D3
so if D1 writes to memory that A2 (but not A1) _might_ load, then the
loop
On 10/03/11 16:21, Richard Sandiford wrote:
I'm not sure I follow. Unrolling a loop {A, B, C, D} gives:
A1
B1
C1
D1
A2
B2
C2
D2
A3
B3
C3
D3
so inter-iteration dependencies aren't a problem.
Expanding on the previous
Bernd Schmidt bernds_...@t-online.de writes:
On 10/03/11 16:21, Richard Sandiford wrote:
so inter-iteration dependencies aren't a problem. Whereas I thought your
modulo instruction did:
A1
B1 A2
C1 B2 A3
D1 C2 B3
D2 C3
D3
so if D1 writes to memory that
On 10/03/11 17:26, Richard Sandiford wrote:
are necessarily equivalent to:
Loop 3:
A
B A
C B A
D C B A
A D C B
B A D C
C B A D
D C B A
D C B
D C
D
Sort of. The insns wouldn't rotate like this in a modulo-scheduled loop.
Is that right? So if D
Bernd Schmidt bernds_...@t-online.de writes:
Reason for asking is that (AIUI) SMS used to use stronger memory
disambiguation, but had to pull back to something more conservative
for similar reasons.
Pointers? All I could find is a thread where rth seems to be of the same
opinion as me:
On 10/03/11 19:23, Richard Sandiford wrote:
Bernd Schmidt bernds_...@t-online.de writes:
Reason for asking is that (AIUI) SMS used to use stronger memory
disambiguation, but had to pull back to something more conservative
for similar reasons.
Pointers? All I could find is a thread where rth
Bernd Schmidt bernds_...@t-online.de writes:
On 10/03/11 19:23, Richard Sandiford wrote:
Bernd Schmidt bernds_...@t-online.de writes:
Reason for asking is that (AIUI) SMS used to use stronger memory
disambiguation, but had to pull back to something more conservative
for similar reasons.
On 10/03/11 20:12, Richard Sandiford wrote:
But what I'm trying to say is that you're not just doing loop
unrolling followed by scheduling. You're doing loop unrolling,
followed by scheduling, followed by an overlapping of the unrolled loop
iterations. It just felt strange that the
On 09/27/2011 08:36 AM, Bernd Schmidt wrote:
Ping:
http://gcc.gnu.org/ml/gcc-patches/2011-09/msg00811.html
Bernd, sorry for the delay.
I thought for long time about this approach because we already have
selective scheduler which with some modifications could be used for
this. Selective
On 09/29/11 23:32, Vladimir Makarov wrote:
Bernd, sorry for the delay.
No problem.
I thought for long time about this approach because we already have
selective scheduler which with some modifications could be used for
this. Selective scheduler was implemented for Itanium, designed to
Ping:
http://gcc.gnu.org/ml/gcc-patches/2011-09/msg00811.html
Bernd
Bernd Schmidt ber...@codesourcery.com writes:
I have added support for this to haifa-sched.c. I expect the question
why not use SMS to come up; there were a number of reasons why I felt
that code is unsuitable:
Fully agree that SMS is unsuitable here FWIW, but...
There are (or were, when I
On 09/14/11 11:03, Richard Sandiford wrote:
...I didn't see from an admittedly quick read of the patch how you
handle memory disambiguation between iterations. If a loop includes:
lb $3,($4)
sb $5,1($4)
then the two instructions can be reordered by normal ebb scheduling,
but
C6X has some rather nifty hardware support for modulo scheduling.
Consider the following loop:
.L13:
ldh .d1t1 *++A5[1], A7
|| add .s1 -1, A0, A0
ldh .d2t1 *B5++[1], A8
nop 1
[A0]b .s1 .L13
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