No functional changes. 2016-11-28 Uros Bizjak <ubiz...@gmail.com>
* config/i386/i386.md (*and<mode>_1): Merge insn pattern from *andsi_1 and *andhi_1 using SWI24 mode iterator. Use multi-line output template string. (*anddi_1): Use multi-line output template string. (*andqi_1): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros.
Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 242925) +++ config/i386/i386.md (working copy) @@ -8172,20 +8172,11 @@ (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)" -{ - switch (get_attr_type (insn)) - { - case TYPE_IMOVX: - return "#"; - - default: - gcc_assert (rtx_equal_p (operands[0], operands[1])); - if (get_attr_mode (insn) == MODE_SI) - return "and{l}\t{%k2, %k0|%k0, %k2}"; - else - return "and{q}\t{%2, %0|%0, %2}"; - } -} + "@ + and{l}\t{%k2, %k0|%k0, %k2} + and{q}\t{%2, %0|%0, %2} + and{q}\t{%2, %0|%0, %2} + #" [(set_attr "type" "alu,alu,alu,imovx") (set_attr "length_immediate" "*,*,*,0") (set (attr "prefix_rex") @@ -8221,24 +8212,18 @@ [(set_attr "type" "alu") (set_attr "mode" "SI")]) -(define_insn "*andsi_1" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya") - (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm") - (match_operand:SI 2 "x86_64_general_operand" "re,rm,L"))) +(define_insn "*and<mode>_1" + [(set (match_operand:SWI24 0 "nonimmediate_operand" "=rm,r,Ya") + (and:SWI24 (match_operand:SWI24 1 "nonimmediate_operand" "%0,0,qm") + (match_operand:SWI24 2 "<general_operand>" "r<i>,rm,L"))) (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (AND, SImode, operands)" -{ - switch (get_attr_type (insn)) - { - case TYPE_IMOVX: - return "#"; - - default: - gcc_assert (rtx_equal_p (operands[0], operands[1])); - return "and{l}\t{%2, %0|%0, %2}"; - } -} + "ix86_binary_operator_ok (AND, <MODE>mode, operands)" + "@ + and{<imodesuffix>}\t{%2, %0|%0, %2} + and{<imodesuffix>}\t{%2, %0|%0, %2} + #" [(set_attr "type" "alu,alu,imovx") + (set_attr "length_immediate" "*,*,0") (set (attr "prefix_rex") (if_then_else (and (eq_attr "type" "imovx") @@ -8246,36 +8231,8 @@ (match_operand 1 "ext_QIreg_operand"))) (const_string "1") (const_string "*"))) - (set_attr "length_immediate" "*,*,0") - (set_attr "mode" "SI")]) + (set_attr "mode" "<MODE>,<MODE>,SI")]) -(define_insn "*andhi_1" - [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,Ya") - (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm") - (match_operand:HI 2 "general_operand" "rn,rm,L"))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (AND, HImode, operands)" -{ - switch (get_attr_type (insn)) - { - case TYPE_IMOVX: - return "#"; - - default: - gcc_assert (rtx_equal_p (operands[0], operands[1])); - return "and{w}\t{%2, %0|%0, %2}"; - } -} - [(set_attr "type" "alu,alu,imovx") - (set_attr "length_immediate" "*,*,0") - (set (attr "prefix_rex") - (if_then_else - (and (eq_attr "type" "imovx") - (match_operand 1 "ext_QIreg_operand")) - (const_string "1") - (const_string "*"))) - (set_attr "mode" "HI,HI,SI")]) - (define_insn "*andqi_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") @@ -8282,18 +8239,10 @@ (match_operand:QI 2 "general_operand" "qn,qmn,rn"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (AND, QImode, operands)" -{ - switch (which_alternative) - { - case 0: - case 1: - return "and{b}\t{%2, %0|%0, %2}"; - case 2: - return "and{l}\t{%k2, %k0|%k0, %k2}"; - default: - gcc_unreachable (); - } -} + "@ + and{b}\t{%2, %0|%0, %2} + and{b}\t{%2, %0|%0, %2} + and{l}\t{%k2, %k0|%k0, %k2}" [(set_attr "type" "alu") (set_attr "mode" "QI,QI,SI") ;; Potential partial reg stall on alternative 2.