Hello! Attached patch removes various *_not_xmm0_operand hacks. These were used to prevent combine from moving xmm0 register to the wrong place, but recently we implemented better approach.
2012-09-05 Uros Bizjak <ubiz...@gmail.com> * config/i386/sse.md (<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>): Use register_operand instead of reg_not_xmm0_operand{,_maybe_avx}. Use nonimmediate_operand instead of nonimm_not_xmm0_operand{,_maybe_avx}. (<sse4_1_avx2>_pblendvb): Ditto. (sse4_2_pcmpestr): Ditto. (*sse4_2_pcmpestr_unaligned): Ditto. (sse4_2_pcmpistr): Ditto. (*sse4_2_pcmpistr_unaligned): Ditto. * config/i386/predicates.md (reg_not_xmm0_operand): Remove predicate. (nonimm_not_xmm0_operand): Ditto. (nonimm_not_xmm0_operand_maybe_avx): Ditto. (nonimm_not_xmm0_operand_maybe_avx): Ditto. * config/i386/i386.md (rdpmc): Do not force operand 1 into ecx. Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32} and committed to mainline SVN. Uros.
Index: predicates.md =================================================================== --- predicates.md (revision 190984) +++ predicates.md (working copy) @@ -93,33 +93,6 @@ (match_test "TARGET_64BIT") (match_test "REGNO (op) > BX_REG"))) -;; Return true if op is not xmm0 register. -(define_predicate "reg_not_xmm0_operand" - (match_operand 0 "register_operand") -{ - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - - return !REG_P (op) || REGNO (op) != FIRST_SSE_REG; -}) - -;; As above, but also allow memory operands. -(define_predicate "nonimm_not_xmm0_operand" - (ior (match_operand 0 "memory_operand") - (match_operand 0 "reg_not_xmm0_operand"))) - -;; Return true if op is not xmm0 register, but only for non-AVX targets. -(define_predicate "reg_not_xmm0_operand_maybe_avx" - (if_then_else (match_test "TARGET_AVX") - (match_operand 0 "register_operand") - (match_operand 0 "reg_not_xmm0_operand"))) - -;; As above, but also allow memory operands. -(define_predicate "nonimm_not_xmm0_operand_maybe_avx" - (if_then_else (match_test "TARGET_AVX") - (match_operand 0 "nonimmediate_operand") - (match_operand 0 "nonimm_not_xmm0_operand"))) - ;; Return true if VALUE can be stored in a sign extended immediate field. (define_predicate "x86_64_immediate_operand" (match_code "const_int,symbol_ref,label_ref,const") Index: sse.md =================================================================== --- sse.md (revision 190984) +++ sse.md (working copy) @@ -8593,10 +8593,10 @@ (set_attr "mode" "<MODE>")]) (define_insn "<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>" - [(set (match_operand:VF 0 "reg_not_xmm0_operand_maybe_avx" "=x,x") + [(set (match_operand:VF 0 "register_operand" "=x,x") (unspec:VF - [(match_operand:VF 1 "reg_not_xmm0_operand_maybe_avx" "0,x") - (match_operand:VF 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm") + [(match_operand:VF 1 "register_operand" "0,x") + (match_operand:VF 2 "nonimmediate_operand" "xm,xm") (match_operand:VF 3 "register_operand" "Yz,x")] UNSPEC_BLENDV))] "TARGET_SSE4_1" @@ -8691,10 +8691,10 @@ (set_attr "mode" "TI")]) (define_insn "<sse4_1_avx2>_pblendvb" - [(set (match_operand:VI1_AVX2 0 "reg_not_xmm0_operand" "=x,x") + [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x") (unspec:VI1_AVX2 - [(match_operand:VI1_AVX2 1 "reg_not_xmm0_operand_maybe_avx" "0,x") - (match_operand:VI1_AVX2 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm") + [(match_operand:VI1_AVX2 1 "register_operand" "0,x") + (match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm") (match_operand:VI1_AVX2 3 "register_operand" "Yz,x")] UNSPEC_BLENDV))] "TARGET_SSE4_1" @@ -9164,9 +9164,9 @@ (define_insn_and_split "sse4_2_pcmpestr" [(set (match_operand:SI 0 "register_operand" "=c,c") (unspec:SI - [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x") + [(match_operand:V16QI 2 "register_operand" "x,x") (match_operand:SI 3 "register_operand" "a,a") - (match_operand:V16QI 4 "nonimm_not_xmm0_operand" "x,m") + (match_operand:V16QI 4 "nonimmediate_operand" "x,m") (match_operand:SI 5 "register_operand" "d,d") (match_operand:SI 6 "const_0_to_255_operand" "n,n")] UNSPEC_PCMPESTR)) @@ -9224,7 +9224,7 @@ (define_insn_and_split "*sse4_2_pcmpestr_unaligned" [(set (match_operand:SI 0 "register_operand" "=c") (unspec:SI - [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x") + [(match_operand:V16QI 2 "register_operand" "x") (match_operand:SI 3 "register_operand" "a") (unspec:V16QI [(match_operand:V16QI 4 "memory_operand" "m")] @@ -9365,8 +9365,8 @@ (define_insn_and_split "sse4_2_pcmpistr" [(set (match_operand:SI 0 "register_operand" "=c,c") (unspec:SI - [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x") - (match_operand:V16QI 3 "nonimm_not_xmm0_operand" "x,m") + [(match_operand:V16QI 2 "register_operand" "x,x") + (match_operand:V16QI 3 "nonimmediate_operand" "x,m") (match_operand:SI 4 "const_0_to_255_operand" "n,n")] UNSPEC_PCMPISTR)) (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz") @@ -9416,7 +9416,7 @@ (define_insn_and_split "*sse4_2_pcmpistr_unaligned" [(set (match_operand:SI 0 "register_operand" "=c") (unspec:SI - [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x") + [(match_operand:V16QI 2 "register_operand" "x") (unspec:V16QI [(match_operand:V16QI 3 "memory_operand" "m")] UNSPEC_MOVU) Index: i386.md =================================================================== --- i386.md (revision 190984) +++ i386.md (working copy) @@ -17983,10 +17983,7 @@ rtx reg = gen_reg_rtx (DImode); rtx si; - /* Force operand 1 into ECX. */ - rtx ecx = gen_rtx_REG (SImode, CX_REG); - emit_insn (gen_rtx_SET (VOIDmode, ecx, operands[1])); - si = gen_rtx_UNSPEC_VOLATILE (DImode, gen_rtvec (1, ecx), + si = gen_rtx_UNSPEC_VOLATILE (DImode, gen_rtvec (1, operands[1]), UNSPECV_RDPMC); if (TARGET_64BIT)