Re: [PATCH, rs6000] Generate lvx and stvx without swaps for aligned vector loads and stores

2018-01-12 Thread Segher Boessenkool
On Fri, Jan 12, 2018 at 01:55:26PM -0600, Kelvin Nilsen wrote: > On Power 7 and Power 8 little endian, the code generator has been > emitting two instructions for each vector load and each vector store. > One instruction does a swapping load or store, and the second > instruction does an

[PATCH, rs6000] Generate lvx and stvx without swaps for aligned vector loads and stores

2018-01-12 Thread Kelvin Nilsen
On Power 7 and Power 8 little endian, the code generator has been emitting two instructions for each vector load and each vector store. One instruction does a swapping load or store, and the second instruction does an in-register swap. This patch replaces the two-instruction sequences with a