Ramana Radhakrishnan writes:
> On Thu, Dec 13, 2018 at 10:15 AM Richard Sandiford
> wrote:
>>
>> Thanks for doing this.
>>
>> "Kyrill Tkachov" writes:
>> > @@ -15716,16 +15716,19 @@ an effect when SVE is enabled.
>> >
>> > GCC supports two forms of SVE code generation: ``vector-length
>> >
On Thu, Dec 13, 2018 at 10:15 AM Richard Sandiford
wrote:
>
> Thanks for doing this.
>
> "Kyrill Tkachov" writes:
> > @@ -15716,16 +15716,19 @@ an effect when SVE is enabled.
> >
> > GCC supports two forms of SVE code generation: ``vector-length
> > agnostic'' output that works with any size
Thanks for doing this.
"Kyrill Tkachov" writes:
> @@ -15716,16 +15716,19 @@ an effect when SVE is enabled.
>
> GCC supports two forms of SVE code generation: ``vector-length
> agnostic'' output that works with any size of vector register and
> -``vector-length specific'' output that only
Hi all,
We've received reports about the -msve-vector-bits=128 bits being somewhat
ambiguous.
It isn't clear whether -msve-vector-bits=128 forces vector-length-agnostic code
or whether
-msve-vector-bits=scalable forces 128-bit vector-lengh-specific code.
The latter is a, perhaps unintuitive,
