Re: [PATCH][AArch64] Leveraging the use of STP instruction for vec_duplicate

2021-04-21 Thread Richard Sandiford via Gcc-patches
Victor Do Nascimento via Gcc-patches writes: > The backend pattern for storing a pair of identical values in 32 and 64-bit > modes with the machine instruction STP was missing, and multiple instructions > were needed to reproduce this behavior as a result of failed RTL pattern > match in combin

[PATCH][AArch64] Leveraging the use of STP instruction for vec_duplicate

2021-03-18 Thread Victor Do Nascimento via Gcc-patches
The backend pattern for storing a pair of identical values in 32 and 64-bit modes with the machine instruction STP was missing, and multiple instructions were needed to reproduce this behavior as a result of failed RTL pattern match in combine pass. For the test case : typedef long long v2di _

Re: [PATCH][AArch64] Leveraging the use of STP instruction for vec_duplicate

2021-02-15 Thread Richard Sandiford via Gcc-patches
Hi Victor, Thanks for the patch. I have a couple of very minor comments below, but otherwise it looks good to go. However, it will need to wait for stage 1 to open, unless it fixes a regression. Victor Do Nascimento via Gcc-patches writes: > diff --git a/gcc/config/aarch64/aarch64-simd.md > b

[PATCH][AArch64] Leveraging the use of STP instruction for vec_duplicate

2021-02-11 Thread Victor Do Nascimento via Gcc-patches
Dear GCC community, The backend pattern for storing a pair of identical values in 32 and 64-bit modes with the machine instruction STP was missing, and multiple instructions were needed to reproduce this behavior as a result of failed RTL pattern match in combine pass. For the test case : ty