Hi,
>> I've noticed that your patch caused a regression:
>> FAIL: gcc.dg/tree-prof/pr77698.c scan-rtl-dump-times alignments
>> "internal loop alignment added" 1
I've created https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93007
Cheers,
Wilco
On 16/10/2019 13:13, Wilco Dijkstra wrote:
Hi Christophe,
I've noticed that your patch caused a regression:
FAIL: gcc.dg/tree-prof/pr77698.c scan-rtl-dump-times alignments
"internal loop alignment added" 1
That's just a testism - it only tests for loop alignment and doesn't
consider the
Hi Christophe,
> I've noticed that your patch caused a regression:
> FAIL: gcc.dg/tree-prof/pr77698.c scan-rtl-dump-times alignments
> "internal loop alignment added" 1
That's just a testism - it only tests for loop alignment and doesn't
consider the possibility of the loop being jumped into
On Sat, 12 Oct 2019 at 02:52, Ramana Radhakrishnan
wrote:
>
> On Fri, Oct 11, 2019 at 6:19 PM Wilco Dijkstra wrote:
> >
> > Hi Ramana,
> >
> > > Can you see what happens with the Cortex-A8 or Cortex-A9 schedulers to
> > > spread the range across some v7-a CPUs as well ? While they aren't that
>
On Fri, Oct 11, 2019 at 10:42 PM Wilco Dijkstra wrote:
>
> Hi,
>
> > the defaults for v7-a are still to use the
> > Cortex-A8 scheduler
>
> I missed that part, but that's a serious bug btw - Cortex-A8 is 15 years old
> now so
> way beyond obsolete. Even Cortex-A53 is ancient now, but it has an
On Fri, Oct 11, 2019 at 6:19 PM Wilco Dijkstra wrote:
>
> Hi Ramana,
>
> > Can you see what happens with the Cortex-A8 or Cortex-A9 schedulers to
> > spread the range across some v7-a CPUs as well ? While they aren't that
> > popular today I
> > would suggest you look at them because the
Hi,
> the defaults for v7-a are still to use the
> Cortex-A8 scheduler
I missed that part, but that's a serious bug btw - Cortex-A8 is 15 years old
now so
way beyond obsolete. Even Cortex-A53 is ancient now, but it has an accurate
scheduler
that performs surprisingly well on both in-order
Hi Ramana,
> Can you see what happens with the Cortex-A8 or Cortex-A9 schedulers to
> spread the range across some v7-a CPUs as well ? While they aren't that
> popular today I
> would suggest you look at them because the defaults for v7-a are still to use
> the
> Cortex-A8 scheduler and the
On Tue, Jul 30, 2019 at 4:16 PM Wilco Dijkstra wrote:
>
> Hi all,
>
> >On 30/07/2019 10:31, Ramana Radhakrishnan wrote:
> >> On 30/07/2019 10:08, Christophe Lyon wrote:
>
> >>> Hi Wilco,
> >>>
> >>> Do you know which benchmarks were used when this was checked-in?
> >>> It isn't clear from
>
ping
Currently the Arm backend selects the alternative sched pressure algorithm.
The issue is that this doesn't take register pressure into account, and so
it causes significant additional spilling on Arm where there are only 14
allocatable registers. SPEC2006 shows significant
ping
Currently the Arm backend selects the alternative sched pressure algorithm.
The issue is that this doesn't take register pressure into account, and so
it causes significant additional spilling on Arm where there are only 14
allocatable registers. SPEC2006 shows
ping
Currently the Arm backend selects the alternative sched pressure algorithm.
The issue is that this doesn't take register pressure into account, and so
it causes significant additional spilling on Arm where there are only 14
allocatable registers. SPEC2006 shows significant
ping
Currently the Arm backend selects the alternative sched pressure algorithm.
The issue is that this doesn't take register pressure into account, and so
it causes significant additional spilling on Arm where there are only 14
allocatable registers. SPEC2006 shows significant codesize
Hi all,
>On 30/07/2019 10:31, Ramana Radhakrishnan wrote:
>> On 30/07/2019 10:08, Christophe Lyon wrote:
>>> Hi Wilco,
>>>
>>> Do you know which benchmarks were used when this was checked-in?
>>> It isn't clear from
>>> https://gcc.gnu.org/ml/gcc-patches/2012-07/msg00706.html
>>
>>
On 30/07/2019 10:31, Ramana Radhakrishnan wrote:
On 30/07/2019 10:08, Christophe Lyon wrote:
On Mon, 29 Jul 2019 at 18:49, Wilco Dijkstra
wrote:
Currently the Arm backend selects the alternative sched pressure
algorithm.
The issue is that this doesn't take register pressure into account,
On 30/07/2019 10:08, Christophe Lyon wrote:
On Mon, 29 Jul 2019 at 18:49, Wilco Dijkstra wrote:
Currently the Arm backend selects the alternative sched pressure algorithm.
The issue is that this doesn't take register pressure into account, and so
it causes significant additional spilling on
On Mon, 29 Jul 2019 at 18:49, Wilco Dijkstra wrote:
>
> Currently the Arm backend selects the alternative sched pressure algorithm.
> The issue is that this doesn't take register pressure into account, and so
> it causes significant additional spilling on Arm where there are only 14
> allocatable
Currently the Arm backend selects the alternative sched pressure algorithm.
The issue is that this doesn't take register pressure into account, and so
it causes significant additional spilling on Arm where there are only 14
allocatable registers. SPEC2006 shows significant codesize reduction
with
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