[PATCH][ARM] Update max_cond_insns settings

2018-11-09 Thread Wilco Dijkstra
The existing setting of max_cond_insns for most cores is non-optimal. Thumb-2 IT has a maximum limit of 4, so 5 means emitting 2 IT sequences. Also such long sequences of conditional instructions can increase the number of executed instructions significantly, so using 5 for max_cond_insns is non-op

Re: [PATCH][ARM] Update max_cond_insns settings

2017-06-27 Thread Wilco Dijkstra
  ping     Richard Earnshaw (lists) wrote: > On 05/05/17 13:42, Wilco Dijkstra wrote: >> Richard Earnshaw (lists) wrote: >>> On 04/05/17 18:38, Wilco Dijkstra wrote: >>> > Richard Earnshaw wrote: >>> > > -  5, /* Max cond insns.  */ > +  2, 

Re: [PATCH][ARM] Update max_cond_insns settings

2017-06-13 Thread Wilco Dijkstra
ping   Richard Earnshaw (lists) wrote: > On 05/05/17 13:42, Wilco Dijkstra wrote: >> Richard Earnshaw (lists) wrote: >>> On 04/05/17 18:38, Wilco Dijkstra wrote: >>> > Richard Earnshaw wrote: >>> > > -  5, /* Max cond insns.  */ > +  2,   

Re: [PATCH][ARM] Update max_cond_insns settings

2017-05-05 Thread Wilco Dijkstra
Richard Earnshaw (lists) wrote: > On 05/05/17 13:42, Wilco Dijkstra wrote: >> Richard Earnshaw (lists) wrote: >>> On 04/05/17 18:38, Wilco Dijkstra wrote: >>> > Richard Earnshaw wrote: >>> > > -  5, /* Max cond insns.  */ > +  2, 

Re: [PATCH][ARM] Update max_cond_insns settings

2017-05-05 Thread Richard Earnshaw (lists)
On 05/05/17 13:42, Wilco Dijkstra wrote: > Richard Earnshaw (lists) wrote: >> On 04/05/17 18:38, Wilco Dijkstra wrote: >> > Richard Earnshaw wrote: >> > - 5, /* Max cond insns. */ + 2, /* Max cond insns.

Re: [PATCH][ARM] Update max_cond_insns settings

2017-05-05 Thread Wilco Dijkstra
Richard Earnshaw (lists) wrote: > On 04/05/17 18:38, Wilco Dijkstra wrote: > > Richard Earnshaw wrote: > > >>> -  5, /* Max cond insns.  */ >>> +  2, /* Max cond insns.  */ >> >>> This parameter is also used for A32 c

Re: [PATCH][ARM] Update max_cond_insns settings

2017-05-05 Thread Richard Earnshaw (lists)
On 04/05/17 18:38, Wilco Dijkstra wrote: > Richard Earnshaw wrote: > >> - 5, /* Max cond insns. */ >> + 2, /* Max cond insns. */ > >> This parameter is also used for A32 code. Is that really the right >> number t

Re: [PATCH][ARM] Update max_cond_insns settings

2017-05-04 Thread Wilco Dijkstra
Richard Earnshaw wrote: > -  5, /* Max cond insns.  */ > +  2, /* Max cond insns.  */ > This parameter is also used for A32 code.  Is that really the right > number there as well? Yes, this parameter has always been

Re: [PATCH][ARM] Update max_cond_insns settings

2017-05-04 Thread Richard Earnshaw (lists)
On 12/04/17 14:02, Wilco Dijkstra wrote: > The existing setting of max_cond_insns for most cores is non-optimal. > Thumb-2 IT has a maximum limit of 4, so 5 means emitting 2 IT sequences. > Also such long sequences of conditional instructions can increase the number > of executed instructions signi

Re: [PATCH][ARM] Update max_cond_insns settings

2017-04-20 Thread Wilco Dijkstra
ping From: Wilco Dijkstra Sent: 12 April 2017 14:02 To: GCC Patches Cc: nd; Kyrylo Tkachov Subject: [PATCH][ARM] Update max_cond_insns settings   The existing setting of max_cond_insns for most cores is non-optimal. Thumb-2 IT has a maximum limit of 4, so 5 means emitting 2 IT sequences

[PATCH][ARM] Update max_cond_insns settings

2017-04-12 Thread Wilco Dijkstra
The existing setting of max_cond_insns for most cores is non-optimal. Thumb-2 IT has a maximum limit of 4, so 5 means emitting 2 IT sequences. Also such long sequences of conditional instructions can increase the number of executed instructions significantly, so using 5 for max_cond_insns is non-op