On 06/10/15 18:27, Renlin Li wrote:
> Hi all,
>
> Previously, the compiler will generate the following pattern, which will
> cause an ICE during postreload pass. Meanwhile, the instruction itself
> produces UNKNOWN result when the source and destination register are the same
> according to AR
Hi all,
Previously, the compiler will generate the following pattern, which will
cause an ICE during postreload pass. Meanwhile, the instruction itself
produces UNKNOWN result when the source and destination register are the
same according to ARM instruction manual. The same rule applies to vt
