On 17/02/15 06:18, Jeff Law wrote:
On 02/14/15 04:23, Maxim Kuvyrkov wrote:
FYI, (and not related to the core issue of this patch)
The use of mult vs shift by combine is a problem that Venkat is
working on, see [RFC] Tighten memory type assumption in RTL combiner
pass . The combiner uses
On 02/14/15 04:23, Maxim Kuvyrkov wrote:
FYI, (and not related to the core issue of this patch)
The use of mult vs shift by combine is a problem that Venkat is
working on, see [RFC] Tighten memory type assumption in RTL combiner
pass . The combiner uses MULTs instead of SHIFTs for rtx'es that
On Feb 13, 2015, at 1:47 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 13/02/15 10:10, pins...@gmail.com wrote:
On Feb 13, 2015, at 1:48 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
In my tree added a pattern to the arm backend that's supposed to match:
(set
Hi all,
In my tree added a pattern to the arm backend that's supposed to match:
(set (reg:SI r0)
(subreg:SI
(plus:DI
(mult:DI (sign_extend:DI (reg:SI r1))
(sign_extend:DI (reg:SI r2)))
(const_int 2147483648 [0x8000])) 4))
That is, take two
On 13/02/15 10:10, pins...@gmail.com wrote:
On Feb 13, 2015, at 1:48 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
In my tree added a pattern to the arm backend that's supposed to match:
(set (reg:SI r0)
(subreg:SI
(plus:DI
(mult:DI (sign_extend:DI (reg:SI
On Feb 13, 2015, at 1:48 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
In my tree added a pattern to the arm backend that's supposed to match:
(set (reg:SI r0)
(subreg:SI
(plus:DI
(mult:DI (sign_extend:DI (reg:SI r1))
(sign_extend:DI
