[PATCH][committed] aarch64: Add =r, m and =m, r alternatives to 64-bit vector move patterns

[Kyrylo Tkachov via Gcc-patches]

Hi all,

We can use the X registers to load and store 64-bit vector modes, we just need 
to add the alternatives
to the mov patterns. This straightforward patch does that and for the pair 
variants too.
For the testcase in the code we now generate the optimal assembly without any 
superfluous
GP<->SIMD moves.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill

gcc/ChangeLog:

        * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>):
        Add =r,m and =r,m alternatives.
        (load_pair<DREG:mode><DREG2:mode>): Likewise.
        (vec_store_pair<DREG:mode><DREG2:mode>): Likewise.

gcc/testsuite/ChangeLog:

        * gcc.target/aarch64/xreg-vec-modes_1.c: New test.

rm64.patch
Description: rm64.patch