From: David Miller da...@davemloft.net
Date: Wed, 02 Nov 2011 16:17:33 -0400 (EDT)
From: Eric Botcazou ebotca...@adacore.com
Date: Wed, 2 Nov 2011 13:29:45 +0100
This has reintroduced PR target/49965.
I am working on fixing this right now, thanks for reporting Eric.
This took longer than
Anyways, instead what I do here is normalize all expansions of
conditional moves to be of the form:
(set op0 (if_then_else (cmp X Y)
op3
op0))
and in the instruction patterns I use register_operand and
constraint 0 for
From: Eric Botcazou ebotca...@adacore.com
Date: Wed, 2 Nov 2011 13:29:45 +0100
This has reintroduced PR target/49965.
I am working on fixing this right now, thanks for reporting Eric.
The background is that I was putting together some test cases for
gcc.target/sparc that make sure the most optimal setcc sequences
are being generated.
When v9, and thus conditional moves, are enabled we sometimes fall
back to conditional moves even when the addx/subx sequence is more
efficient.
