More extensive testing showed that we have to force the usage of
v9 scc patterns when comparing DImode values with comparison codes
other than EQ and NE.
Soon we'll be able to add exceptions this this, because VIS3 has addxc
and addxccc instructions which test the 64-bit carry condition.
Committed to trunk.
gcc/
* config/sparc/sparc.c (emit_scc_insn): Force attempt of v9 sequences
if we're comparing DImode and comparison is other than EQ or NE.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180558
138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/ChangeLog | 3 +++
gcc/config/sparc/sparc.c | 5 +++++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3a51510..124b17c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
2011-10-26 David S. Miller <da...@davemloft.net>
+ * config/sparc/sparc.c (emit_scc_insn): Force attempt of v9 sequences
+ if we're comparing DImode and comparison is other than EQ or NE.
+
* config/sparc/sparc.c (emit_scc_insn): Do not try v9 sequences until
LEU/LTU/GEU/GTU is attempted.
* config/sparc/sparc.md (*neg_snesi_sign_extend): New 64-bit insn
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 80e05a6..ea9fdef 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2541,6 +2541,11 @@ emit_scc_insn (rtx operands[])
}
}
+ if (TARGET_V9
+ && GET_MODE (x) == DImode
+ && gen_v9_scc (operands[0], code, x, y))
+ return true;
+
/* We can do LTU and GEU using the addx/subx instructions too. And
for GTU/LEU, if both operands are registers swap them and fall
back to the easy case. */
--
1.7.6.401.g6a319
