On Thu, Jan 21, 2021 at 2:25 AM Levy wrote:
> Added implementation for builtin overflow detection, new patterns are
> listed below.
>
For rv32 SImode and rv64 DImode, the unsigned add/sub and signed/unsigned
mul patterns seem to give the same result as the default code generation.
That has me wo
Added implementation for builtin overflow detection, new patterns are listed
below.
signed addition:
add t0, t1, t2
sltit3, t2, 0
slt t4, t0, t1
bne t3, t4, overflow
unsigned addition:
add t0, t1, t2
bltut0, t1, overflow
sig
