Re: [PATCH] RISC-V: Disallow negative step for interleaving [PR117682].

2025-01-13 Thread Jeff Law
On 12/17/24 8:27 AM, Robin Dapp wrote: Hi, in PR117682 we build an interleaving pattern { 1, 201, 209, 25, 161, 105, 113, 185, 65, 9, 17, 89, 225, 169, 177, 249, 129, 73, 81, 153, 33, 233, 241, 57, 193, 137, 145, 217, 97, 41, 49, 121 }; with negative step expecting wraparo

Re: [PATCH] RISC-V: Disallow negative step for interleaving [PR117682].

2024-12-18 Thread Jeff Law
On 12/18/24 1:17 PM, Patrick O'Neill wrote: On 12/18/24 15:09, Jeff Law wrote: On 12/17/24 8:27 AM, Robin Dapp wrote: Hi, in PR117682 we build an interleaving pattern    { 1, 201, 209, 25, 161, 105, 113, 185, 65, 9, 17, 89, 225, 169, 177, 249, 129, 73, 81, 153, 33, 233, 241, 5

Re: [PATCH] RISC-V: Disallow negative step for interleaving [PR117682].

2024-12-18 Thread Jeff Law
On 12/17/24 8:27 AM, Robin Dapp wrote: Hi, in PR117682 we build an interleaving pattern { 1, 201, 209, 25, 161, 105, 113, 185, 65, 9, 17, 89, 225, 169, 177, 249, 129, 73, 81, 153, 33, 233, 241, 57, 193, 137, 145, 217, 97, 41, 49, 121 }; with negative step expecting wraparo

Re: [PATCH] RISC-V: Disallow negative step for interleaving [PR117682].

2024-12-17 Thread Robin Dapp
> +/* { dg-require-effective-target riscv_v } */ > +/* { dg-require-effective-target rvv_zvl256b_ok } */ > +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -fwrapv" } > */ Ah, I forgot _zvl256b in the -march string. It seems to still fail with the settings as posted but I'll st

[PATCH] RISC-V: Disallow negative step for interleaving [PR117682].

2024-12-17 Thread Robin Dapp
Hi, in PR117682 we build an interleaving pattern { 1, 201, 209, 25, 161, 105, 113, 185, 65, 9, 17, 89, 225, 169, 177, 249, 129, 73, 81, 153, 33, 233, 241, 57, 193, 137, 145, 217, 97, 41, 49, 121 }; with negative step expecting wraparound semantics due to -fwrapv. For building inte