RE: [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32

Committed, thanks Robin. Pan -Original Message- From: Robin Dapp Sent: Monday, October 30, 2023 3:42 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: rdapp@gmail.com; kito.ch...@sifive.com; kito.ch...@gmail.com; jeffreya...@gmail.com Subject: Re: [PATCH] RISC-V: Fix bugs of

Re: [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32

Thanks, LGTM. Regards Robin

[PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32

sew64_scalar_helper is handling SEW64 vx instruction pattern on RV32 system. According to RVV ISA, we can directly use vx instruction of SEW64 on RV32 system since RV32 GR reg is 32bit. Consider this following case: vsetvl e64m1 vadd.vx v,v,x will be transform by sew64_scalar_helper: vsetvl