Re: Re: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]

Committed, thanks Juzhe. -- Li Xu >Thanks a lot. LGTM. > > > >juzhe.zh...@rivai.ai > >From: Li Xu >Date: 2023-09-21 11:12 >To: gcc-patches >CC: kito.cheng; palmer; juzhe.zhong; xuli >Subject: [PATCH] RISC-V: Optimized for strided load/store with s

Re: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]

Thanks a lot. LGTM. juzhe.zh...@rivai.ai From: Li Xu Date: 2023-09-21 11:12 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli Subject: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450] From: xuli When stride == element width, vlsse should

[PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]

From: xuli When stride == element width, vlsse should be optimized into vle.v. vsse should be optimized into vse.v. PR target/111450 gcc/ChangeLog: *config/riscv/constraints.md (c01): const_int 1. (c02): const_int 2. (c04): const_int 4. (c08): const_int