Re: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

PATCH] RISC-V: Support vfwmul.vv combine lowering On 7/3/23 02:42, juzhe.zh...@rivai.ai wrote: > We failed to merge it since it's been rejected. > https://patchwork.sourceware.org/project/gcc/patch/20230628041512.188243-1-juzhe.zh...@rivai.ai/ > > <https://patchwork.sourcew

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

On 7/3/23 02:42, juzhe.zh...@rivai.ai wrote: We failed to merge it since it's been rejected. https://patchwork.sourceware.org/project/gcc/patch/20230628041512.188243-1-juzhe.zh...@rivai.ai/ Tha

Re: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

Commited, thanks Robin and Jeff. -- Original -- From: "juzhe.zh...@rivai.ai"

Re: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

OK. Thanks. Will commit with your cleanup patch. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-07-03 16:49 To: juzhe.zh...@rivai.ai CC: rdapp.gcc; jeffreyalaw; gcc-patches; kito.cheng; Kito.cheng; palmer; palmer Subject: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering On 7/3/23 10

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

or merge adjustments on my branch. Regards Robin >From 29b12a473a31b2caa64fa2d1d97920a460ced0a2 Mon Sep 17 00:00:00 2001 From: Juzhe-Zhong Date: Wed, 28 Jun 2023 12:15:12 +0800 Subject: [PATCH] RISC-V: Support vfwmul.vv combine lowering Consider the following complicate case: #define TEST_TYPE(T

Re: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

We can apply it but not sure why the patchwork shows it's rejected. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-07-03 16:44 To: juzhe.zh...@rivai.ai CC: rdapp.gcc; jeffreyalaw; gcc-patches; kito.cheng; Kito.cheng; palmer; palmer Subject: Re: [PATCH] RISC-V: Support vfwmul.vv co

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

> We failed to merge it since it's been rejected. > https://patchwork.sourceware.org/project/gcc/patch/20230628041512.188243-1-juzhe.zh...@rivai.ai/ > > >   Err, who rejected? Or is this about the

Re: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

almer; palmer Subject: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering > Thanks. Ok for trunk？ OK from my side. As agreed with Jeff, I'm going to get back to this and revisit/change if needed in the future. Regards Robin

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

> Thanks. Ok for trunk？ OK from my side. As agreed with Jeff, I'm going to get back to this and revisit/change if needed in the future. Regards Robin

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

> There has to be some kind of mismatch between the patch or testcase > or what we're looking at to judge success. Yeah I think the initially posted example was misleading because it contained an already working example. > While I really don't see the need to have the bridge pattern, I'm > still

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

On 6/30/23 04:14, Robin Dapp wrote: The explicit conversions I see are because we need the output of the conversion in multiple vfmul instructions. That won't be helped by the patch you've proposed. FWIW on my local branch and the patch applied I see that the vfwmuls are being generated (al

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

> The explicit conversions I see are because we need the output of the > conversion in multiple vfmul instructions. That won't be helped by > the patch you've proposed. FWIW on my local branch and the patch applied I see that the vfwmuls are being generated (all of the vfmuls are replaced). > It

Re: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

nks. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-06-30 07:48 To: juzhe.zhong CC: gcc-patches; kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc Subject: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering On 6/29/23 17:46, juzhe.zhong wrote: > You should try the example check the

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

On 6/29/23 17:46, juzhe.zhong wrote: You should try the example check the codegen before and after the patch. You will understand it. I've already done that. It makes _no_ difference on the godbold example. Jeff

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

On 6/28/23 16:00, 钟居哲 wrote: You can see here: https://godbolt.org/z/d78646hWb You patch doesn't help that code and your patch is a result of fundamentally misunderstanding combine's capabilities AFAICT. Jeff

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

On 6/28/23 16:00, 钟居哲 wrote: You can see here: https://godbolt.org/z/d78646hWb So just to be explicit, I see no difference with that test before/after your proposed change. Nor would I expect one based on my understanding of the patch. The explicit conve

Re: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

Or do you have better solution to make the case succeed to combine into vfwmul? I am ok with any solution. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-06-30 06:59 To: 钟居哲; gcc-patches CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc Subject: Re: [PATCH] RISC-V: Support vfwmul.vv

Re: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

* (TYPE1) b2[i];\ }\ } TEST_TYPE (double, float) You should try this, then you will know I am saying. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-06-30 06:59 To: 钟居哲; gcc-patches CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc Subject: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

On 6/28/23 16:00, 钟居哲 wrote: You can see here: https://godbolt.org/z/d78646hWb The first case can't genreate vfwmul.vv but second case succeed. Failed to match this instruction: (set (reg:VNx2DF 150 [ vect__11.50 ])     (if_then_else:VNx2DF (unspec:VNx2BI

Re: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

he.zh...@rivai.ai From: Jeff Law Date: 2023-06-29 00:24 To: Juzhe-Zhong; gcc-patches CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc Subject: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering On 6/27/23 22:15, Juzhe-Zhong wrote: > Consider the following complicate case: > #define TEST

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

On 6/27/23 22:15, Juzhe-Zhong wrote: Consider the following complicate case: #define TEST_TYPE(TYPE1, TYPE2)\ __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \ TYPE1 *__restrict dst, TYPE1 *__restrict dst2, T

[PATCH] RISC-V: Support vfwmul.vv combine lowering

Consider the following complicate case: #define TEST_TYPE(TYPE1, TYPE2)\ __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \ TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \ TYPE1 *__res